1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/pci.h> 31 32 #include <drm/drm_print.h> 33 34 #include "ast_dram_tables.h" 35 #include "ast_drv.h" 36 37 static void ast_post_chip_2300(struct drm_device *dev); 38 static void ast_post_chip_2500(struct drm_device *dev); 39 40 void ast_enable_vga(struct drm_device *dev) 41 { 42 struct ast_device *ast = to_ast_device(dev); 43 44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); 45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); 46 } 47 48 void ast_enable_mmio(struct drm_device *dev) 49 { 50 struct ast_device *ast = to_ast_device(dev); 51 52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); 53 } 54 55 56 bool ast_is_vga_enabled(struct drm_device *dev) 57 { 58 struct ast_device *ast = to_ast_device(dev); 59 u8 ch; 60 61 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); 62 63 return !!(ch & 0x01); 64 } 65 66 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; 67 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff }; 68 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff }; 69 70 static void 71 ast_set_def_ext_reg(struct drm_device *dev) 72 { 73 struct ast_device *ast = to_ast_device(dev); 74 struct pci_dev *pdev = to_pci_dev(dev->dev); 75 u8 i, index, reg; 76 const u8 *ext_reg_info; 77 78 /* reset scratch */ 79 for (i = 0x81; i <= 0x9f; i++) 80 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); 81 82 if (ast->chip == AST2300 || ast->chip == AST2400 || 83 ast->chip == AST2500) { 84 if (pdev->revision >= 0x20) 85 ext_reg_info = extreginfo_ast2300; 86 else 87 ext_reg_info = extreginfo_ast2300a0; 88 } else 89 ext_reg_info = extreginfo; 90 91 index = 0xa0; 92 while (*ext_reg_info != 0xff) { 93 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); 94 index++; 95 ext_reg_info++; 96 } 97 98 /* disable standard IO/MEM decode if secondary */ 99 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ 100 101 /* Set Ext. Default */ 102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); 103 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); 104 105 /* Enable RAMDAC for A1 */ 106 reg = 0x04; 107 if (ast->chip == AST2300 || ast->chip == AST2400 || 108 ast->chip == AST2500) 109 reg |= 0x20; 110 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); 111 } 112 113 u32 ast_mindwm(struct ast_device *ast, u32 r) 114 { 115 uint32_t data; 116 117 ast_write32(ast, 0xf004, r & 0xffff0000); 118 ast_write32(ast, 0xf000, 0x1); 119 120 do { 121 data = ast_read32(ast, 0xf004) & 0xffff0000; 122 } while (data != (r & 0xffff0000)); 123 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); 124 } 125 126 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v) 127 { 128 uint32_t data; 129 ast_write32(ast, 0xf004, r & 0xffff0000); 130 ast_write32(ast, 0xf000, 0x1); 131 do { 132 data = ast_read32(ast, 0xf004) & 0xffff0000; 133 } while (data != (r & 0xffff0000)); 134 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); 135 } 136 137 /* 138 * AST2100/2150 DLL CBR Setting 139 */ 140 #define CBR_SIZE_AST2150 ((16 << 10) - 1) 141 #define CBR_PASSNUM_AST2150 5 142 #define CBR_THRESHOLD_AST2150 10 143 #define CBR_THRESHOLD2_AST2150 10 144 #define TIMEOUT_AST2150 5000000 145 146 #define CBR_PATNUM_AST2150 8 147 148 static const u32 pattern_AST2150[14] = { 149 0xFF00FF00, 150 0xCC33CC33, 151 0xAA55AA55, 152 0xFFFE0001, 153 0x683501FE, 154 0x0F1929B0, 155 0x2D0B4346, 156 0x60767F02, 157 0x6FBE36A6, 158 0x3A253035, 159 0x3019686D, 160 0x41C6167E, 161 0x620152BF, 162 0x20F050E0 163 }; 164 165 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen) 166 { 167 u32 data, timeout; 168 169 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 170 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); 171 timeout = 0; 172 do { 173 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; 174 if (++timeout > TIMEOUT_AST2150) { 175 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 176 return 0xffffffff; 177 } 178 } while (!data); 179 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 180 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); 181 timeout = 0; 182 do { 183 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; 184 if (++timeout > TIMEOUT_AST2150) { 185 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 186 return 0xffffffff; 187 } 188 } while (!data); 189 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 190 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 191 return data; 192 } 193 194 #if 0 /* unused in DDX driver - here for completeness */ 195 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen) 196 { 197 u32 data, timeout; 198 199 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 200 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); 201 timeout = 0; 202 do { 203 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; 204 if (++timeout > TIMEOUT_AST2150) { 205 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 206 return 0xffffffff; 207 } 208 } while (!data); 209 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 210 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 211 return data; 212 } 213 #endif 214 215 static int cbrtest_ast2150(struct ast_device *ast) 216 { 217 int i; 218 219 for (i = 0; i < 8; i++) 220 if (mmctestburst2_ast2150(ast, i)) 221 return 0; 222 return 1; 223 } 224 225 static int cbrscan_ast2150(struct ast_device *ast, int busw) 226 { 227 u32 patcnt, loop; 228 229 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) { 230 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); 231 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) { 232 if (cbrtest_ast2150(ast)) 233 break; 234 } 235 if (loop == CBR_PASSNUM_AST2150) 236 return 0; 237 } 238 return 1; 239 } 240 241 242 static void cbrdlli_ast2150(struct ast_device *ast, int busw) 243 { 244 u32 dll_min[4], dll_max[4], dlli, data, passcnt; 245 246 cbr_start: 247 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff; 248 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0; 249 passcnt = 0; 250 251 for (dlli = 0; dlli < 100; dlli++) { 252 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 253 data = cbrscan_ast2150(ast, busw); 254 if (data != 0) { 255 if (data & 0x1) { 256 if (dll_min[0] > dlli) 257 dll_min[0] = dlli; 258 if (dll_max[0] < dlli) 259 dll_max[0] = dlli; 260 } 261 passcnt++; 262 } else if (passcnt >= CBR_THRESHOLD_AST2150) 263 goto cbr_start; 264 } 265 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150) 266 goto cbr_start; 267 268 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); 269 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 270 } 271 272 273 274 static void ast_init_dram_reg(struct drm_device *dev) 275 { 276 struct ast_device *ast = to_ast_device(dev); 277 u8 j; 278 u32 data, temp, i; 279 const struct ast_dramstruct *dram_reg_info; 280 281 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 282 283 if ((j & 0x80) == 0) { /* VGA only */ 284 if (ast->chip == AST2000) { 285 dram_reg_info = ast2000_dram_table_data; 286 ast_write32(ast, 0xf004, 0x1e6e0000); 287 ast_write32(ast, 0xf000, 0x1); 288 ast_write32(ast, 0x10100, 0xa8); 289 290 do { 291 ; 292 } while (ast_read32(ast, 0x10100) != 0xa8); 293 } else {/* AST2100/1100 */ 294 if (ast->chip == AST2100 || ast->chip == 2200) 295 dram_reg_info = ast2100_dram_table_data; 296 else 297 dram_reg_info = ast1100_dram_table_data; 298 299 ast_write32(ast, 0xf004, 0x1e6e0000); 300 ast_write32(ast, 0xf000, 0x1); 301 ast_write32(ast, 0x12000, 0x1688A8A8); 302 do { 303 ; 304 } while (ast_read32(ast, 0x12000) != 0x01); 305 306 ast_write32(ast, 0x10000, 0xfc600309); 307 do { 308 ; 309 } while (ast_read32(ast, 0x10000) != 0x01); 310 } 311 312 while (dram_reg_info->index != 0xffff) { 313 if (dram_reg_info->index == 0xff00) {/* delay fn */ 314 for (i = 0; i < 15; i++) 315 udelay(dram_reg_info->data); 316 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) { 317 data = dram_reg_info->data; 318 if (ast->dram_type == AST_DRAM_1Gx16) 319 data = 0x00000d89; 320 else if (ast->dram_type == AST_DRAM_1Gx32) 321 data = 0x00000c8d; 322 323 temp = ast_read32(ast, 0x12070); 324 temp &= 0xc; 325 temp <<= 2; 326 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); 327 } else 328 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); 329 dram_reg_info++; 330 } 331 332 /* AST 2100/2150 DRAM calibration */ 333 data = ast_read32(ast, 0x10120); 334 if (data == 0x5061) { /* 266Mhz */ 335 data = ast_read32(ast, 0x10004); 336 if (data & 0x40) 337 cbrdlli_ast2150(ast, 16); /* 16 bits */ 338 else 339 cbrdlli_ast2150(ast, 32); /* 32 bits */ 340 } 341 342 switch (ast->chip) { 343 case AST2000: 344 temp = ast_read32(ast, 0x10140); 345 ast_write32(ast, 0x10140, temp | 0x40); 346 break; 347 case AST1100: 348 case AST2100: 349 case AST2200: 350 case AST2150: 351 temp = ast_read32(ast, 0x1200c); 352 ast_write32(ast, 0x1200c, temp & 0xfffffffd); 353 temp = ast_read32(ast, 0x12040); 354 ast_write32(ast, 0x12040, temp | 0x40); 355 break; 356 default: 357 break; 358 } 359 } 360 361 /* wait ready */ 362 do { 363 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 364 } while ((j & 0x40) == 0); 365 } 366 367 void ast_post_gpu(struct drm_device *dev) 368 { 369 struct ast_device *ast = to_ast_device(dev); 370 struct pci_dev *pdev = to_pci_dev(dev->dev); 371 u32 reg; 372 373 pci_read_config_dword(pdev, 0x04, ®); 374 reg |= 0x3; 375 pci_write_config_dword(pdev, 0x04, reg); 376 377 ast_enable_vga(dev); 378 ast_open_key(ast); 379 ast_enable_mmio(dev); 380 ast_set_def_ext_reg(dev); 381 382 if (ast->chip == AST2600) { 383 if (ast->tx_chip_types & AST_TX_ASTDP_BIT) 384 ast_dp_launch(dev); 385 } else if (ast->config_mode == ast_use_p2a) { 386 if (ast->chip == AST2500) 387 ast_post_chip_2500(dev); 388 else if (ast->chip == AST2300 || ast->chip == AST2400) 389 ast_post_chip_2300(dev); 390 else 391 ast_init_dram_reg(dev); 392 393 ast_init_3rdtx(dev); 394 } else { 395 if (ast->tx_chip_types & AST_TX_SIL164_BIT) 396 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ 397 } 398 } 399 400 /* AST 2300 DRAM settings */ 401 #define AST_DDR3 0 402 #define AST_DDR2 1 403 404 struct ast2300_dram_param { 405 u32 dram_type; 406 u32 dram_chipid; 407 u32 dram_freq; 408 u32 vram_size; 409 u32 odt; 410 u32 wodt; 411 u32 rodt; 412 u32 dram_config; 413 u32 reg_PERIOD; 414 u32 reg_MADJ; 415 u32 reg_SADJ; 416 u32 reg_MRS; 417 u32 reg_EMRS; 418 u32 reg_AC1; 419 u32 reg_AC2; 420 u32 reg_DQSIC; 421 u32 reg_DRV; 422 u32 reg_IOZ; 423 u32 reg_DQIDLY; 424 u32 reg_FREQ; 425 u32 madj_max; 426 u32 dll2_finetune_step; 427 }; 428 429 /* 430 * DQSI DLL CBR Setting 431 */ 432 #define CBR_SIZE0 ((1 << 10) - 1) 433 #define CBR_SIZE1 ((4 << 10) - 1) 434 #define CBR_SIZE2 ((64 << 10) - 1) 435 #define CBR_PASSNUM 5 436 #define CBR_PASSNUM2 5 437 #define CBR_THRESHOLD 10 438 #define CBR_THRESHOLD2 10 439 #define TIMEOUT 5000000 440 #define CBR_PATNUM 8 441 442 static const u32 pattern[8] = { 443 0xFF00FF00, 444 0xCC33CC33, 445 0xAA55AA55, 446 0x88778877, 447 0x92CC4D6E, 448 0x543D3CDE, 449 0xF1E843C7, 450 0x7C61D253 451 }; 452 453 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl) 454 { 455 u32 data, timeout; 456 457 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 458 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); 459 timeout = 0; 460 do { 461 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; 462 if (data & 0x2000) 463 return false; 464 if (++timeout > TIMEOUT) { 465 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 466 return false; 467 } 468 } while (!data); 469 ast_moutdwm(ast, 0x1e6e0070, 0x0); 470 return true; 471 } 472 473 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl) 474 { 475 u32 data, timeout; 476 477 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 478 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); 479 timeout = 0; 480 do { 481 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; 482 if (++timeout > TIMEOUT) { 483 ast_moutdwm(ast, 0x1e6e0070, 0x0); 484 return 0xffffffff; 485 } 486 } while (!data); 487 data = ast_mindwm(ast, 0x1e6e0078); 488 data = (data | (data >> 16)) & 0xffff; 489 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 490 return data; 491 } 492 493 494 static bool mmc_test_burst(struct ast_device *ast, u32 datagen) 495 { 496 return mmc_test(ast, datagen, 0xc1); 497 } 498 499 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen) 500 { 501 return mmc_test2(ast, datagen, 0x41); 502 } 503 504 static bool mmc_test_single(struct ast_device *ast, u32 datagen) 505 { 506 return mmc_test(ast, datagen, 0xc5); 507 } 508 509 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen) 510 { 511 return mmc_test2(ast, datagen, 0x05); 512 } 513 514 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen) 515 { 516 return mmc_test(ast, datagen, 0x85); 517 } 518 519 static int cbr_test(struct ast_device *ast) 520 { 521 u32 data; 522 int i; 523 data = mmc_test_single2(ast, 0); 524 if ((data & 0xff) && (data & 0xff00)) 525 return 0; 526 for (i = 0; i < 8; i++) { 527 data = mmc_test_burst2(ast, i); 528 if ((data & 0xff) && (data & 0xff00)) 529 return 0; 530 } 531 if (!data) 532 return 3; 533 else if (data & 0xff) 534 return 2; 535 return 1; 536 } 537 538 static int cbr_scan(struct ast_device *ast) 539 { 540 u32 data, data2, patcnt, loop; 541 542 data2 = 3; 543 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 544 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 545 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 546 if ((data = cbr_test(ast)) != 0) { 547 data2 &= data; 548 if (!data2) 549 return 0; 550 break; 551 } 552 } 553 if (loop == CBR_PASSNUM2) 554 return 0; 555 } 556 return data2; 557 } 558 559 static u32 cbr_test2(struct ast_device *ast) 560 { 561 u32 data; 562 563 data = mmc_test_burst2(ast, 0); 564 if (data == 0xffff) 565 return 0; 566 data |= mmc_test_single2(ast, 0); 567 if (data == 0xffff) 568 return 0; 569 570 return ~data & 0xffff; 571 } 572 573 static u32 cbr_scan2(struct ast_device *ast) 574 { 575 u32 data, data2, patcnt, loop; 576 577 data2 = 0xffff; 578 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 579 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 580 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 581 if ((data = cbr_test2(ast)) != 0) { 582 data2 &= data; 583 if (!data2) 584 return 0; 585 break; 586 } 587 } 588 if (loop == CBR_PASSNUM2) 589 return 0; 590 } 591 return data2; 592 } 593 594 static bool cbr_test3(struct ast_device *ast) 595 { 596 if (!mmc_test_burst(ast, 0)) 597 return false; 598 if (!mmc_test_single(ast, 0)) 599 return false; 600 return true; 601 } 602 603 static bool cbr_scan3(struct ast_device *ast) 604 { 605 u32 patcnt, loop; 606 607 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 608 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 609 for (loop = 0; loop < 2; loop++) { 610 if (cbr_test3(ast)) 611 break; 612 } 613 if (loop == 2) 614 return false; 615 } 616 return true; 617 } 618 619 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param) 620 { 621 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0; 622 bool status = false; 623 FINETUNE_START: 624 for (cnt = 0; cnt < 16; cnt++) { 625 dllmin[cnt] = 0xff; 626 dllmax[cnt] = 0x0; 627 } 628 passcnt = 0; 629 for (dlli = 0; dlli < 76; dlli++) { 630 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); 631 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); 632 data = cbr_scan2(ast); 633 if (data != 0) { 634 mask = 0x00010001; 635 for (cnt = 0; cnt < 16; cnt++) { 636 if (data & mask) { 637 if (dllmin[cnt] > dlli) { 638 dllmin[cnt] = dlli; 639 } 640 if (dllmax[cnt] < dlli) { 641 dllmax[cnt] = dlli; 642 } 643 } 644 mask <<= 1; 645 } 646 passcnt++; 647 } else if (passcnt >= CBR_THRESHOLD2) { 648 break; 649 } 650 } 651 gold_sadj[0] = 0x0; 652 passcnt = 0; 653 for (cnt = 0; cnt < 16; cnt++) { 654 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 655 gold_sadj[0] += dllmin[cnt]; 656 passcnt++; 657 } 658 } 659 if (retry++ > 10) 660 goto FINETUNE_DONE; 661 if (passcnt != 16) { 662 goto FINETUNE_START; 663 } 664 status = true; 665 FINETUNE_DONE: 666 gold_sadj[0] = gold_sadj[0] >> 4; 667 gold_sadj[1] = gold_sadj[0]; 668 669 data = 0; 670 for (cnt = 0; cnt < 8; cnt++) { 671 data >>= 3; 672 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 673 dlli = dllmin[cnt]; 674 if (gold_sadj[0] >= dlli) { 675 dlli = ((gold_sadj[0] - dlli) * 19) >> 5; 676 if (dlli > 3) { 677 dlli = 3; 678 } 679 } else { 680 dlli = ((dlli - gold_sadj[0]) * 19) >> 5; 681 if (dlli > 4) { 682 dlli = 4; 683 } 684 dlli = (8 - dlli) & 0x7; 685 } 686 data |= dlli << 21; 687 } 688 } 689 ast_moutdwm(ast, 0x1E6E0080, data); 690 691 data = 0; 692 for (cnt = 8; cnt < 16; cnt++) { 693 data >>= 3; 694 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 695 dlli = dllmin[cnt]; 696 if (gold_sadj[1] >= dlli) { 697 dlli = ((gold_sadj[1] - dlli) * 19) >> 5; 698 if (dlli > 3) { 699 dlli = 3; 700 } else { 701 dlli = (dlli - 1) & 0x7; 702 } 703 } else { 704 dlli = ((dlli - gold_sadj[1]) * 19) >> 5; 705 dlli += 1; 706 if (dlli > 4) { 707 dlli = 4; 708 } 709 dlli = (8 - dlli) & 0x7; 710 } 711 data |= dlli << 21; 712 } 713 } 714 ast_moutdwm(ast, 0x1E6E0084, data); 715 return status; 716 } /* finetuneDQI_L */ 717 718 static void finetuneDQSI(struct ast_device *ast) 719 { 720 u32 dlli, dqsip, dqidly; 721 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff; 722 u32 g_dqidly, g_dqsip, g_margin, g_side; 723 u16 pass[32][2][2]; 724 char tag[2][76]; 725 726 /* Disable DQI CBR */ 727 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); 728 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); 729 reg_mcr18 &= 0x0000ffff; 730 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); 731 732 for (dlli = 0; dlli < 76; dlli++) { 733 tag[0][dlli] = 0x0; 734 tag[1][dlli] = 0x0; 735 } 736 for (dqidly = 0; dqidly < 32; dqidly++) { 737 pass[dqidly][0][0] = 0xff; 738 pass[dqidly][0][1] = 0x0; 739 pass[dqidly][1][0] = 0xff; 740 pass[dqidly][1][1] = 0x0; 741 } 742 for (dqidly = 0; dqidly < 32; dqidly++) { 743 passcnt[0] = passcnt[1] = 0; 744 for (dqsip = 0; dqsip < 2; dqsip++) { 745 ast_moutdwm(ast, 0x1E6E000C, 0); 746 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); 747 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); 748 for (dlli = 0; dlli < 76; dlli++) { 749 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 750 ast_moutdwm(ast, 0x1E6E0070, 0); 751 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); 752 if (cbr_scan3(ast)) { 753 if (dlli == 0) 754 break; 755 passcnt[dqsip]++; 756 tag[dqsip][dlli] = 'P'; 757 if (dlli < pass[dqidly][dqsip][0]) 758 pass[dqidly][dqsip][0] = (u16) dlli; 759 if (dlli > pass[dqidly][dqsip][1]) 760 pass[dqidly][dqsip][1] = (u16) dlli; 761 } else if (passcnt[dqsip] >= 5) 762 break; 763 else { 764 pass[dqidly][dqsip][0] = 0xff; 765 pass[dqidly][dqsip][1] = 0x0; 766 } 767 } 768 } 769 if (passcnt[0] == 0 && passcnt[1] == 0) 770 dqidly++; 771 } 772 /* Search margin */ 773 g_dqidly = g_dqsip = g_margin = g_side = 0; 774 775 for (dqidly = 0; dqidly < 32; dqidly++) { 776 for (dqsip = 0; dqsip < 2; dqsip++) { 777 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1]) 778 continue; 779 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0]; 780 if ((diff+2) < g_margin) 781 continue; 782 passcnt[0] = passcnt[1] = 0; 783 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++); 784 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++); 785 if (passcnt[0] > passcnt[1]) 786 passcnt[0] = passcnt[1]; 787 passcnt[1] = 0; 788 if (passcnt[0] > g_side) 789 passcnt[1] = passcnt[0] - g_side; 790 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) { 791 g_margin = diff; 792 g_dqidly = dqidly; 793 g_dqsip = dqsip; 794 g_side = passcnt[0]; 795 } else if (passcnt[1] > 1 && g_side < 8) { 796 if (diff > g_margin) 797 g_margin = diff; 798 g_dqidly = dqidly; 799 g_dqsip = dqsip; 800 g_side = passcnt[0]; 801 } 802 } 803 } 804 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23); 805 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); 806 807 } 808 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param) 809 { 810 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0; 811 bool status = false; 812 813 finetuneDQSI(ast); 814 if (finetuneDQI_L(ast, param) == false) 815 return status; 816 817 CBR_START2: 818 dllmin[0] = dllmin[1] = 0xff; 819 dllmax[0] = dllmax[1] = 0x0; 820 passcnt = 0; 821 for (dlli = 0; dlli < 76; dlli++) { 822 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 823 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); 824 data = cbr_scan(ast); 825 if (data != 0) { 826 if (data & 0x1) { 827 if (dllmin[0] > dlli) { 828 dllmin[0] = dlli; 829 } 830 if (dllmax[0] < dlli) { 831 dllmax[0] = dlli; 832 } 833 } 834 if (data & 0x2) { 835 if (dllmin[1] > dlli) { 836 dllmin[1] = dlli; 837 } 838 if (dllmax[1] < dlli) { 839 dllmax[1] = dlli; 840 } 841 } 842 passcnt++; 843 } else if (passcnt >= CBR_THRESHOLD) { 844 break; 845 } 846 } 847 if (retry++ > 10) 848 goto CBR_DONE2; 849 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) { 850 goto CBR_START2; 851 } 852 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) { 853 goto CBR_START2; 854 } 855 status = true; 856 CBR_DONE2: 857 dlli = (dllmin[1] + dllmax[1]) >> 1; 858 dlli <<= 8; 859 dlli += (dllmin[0] + dllmax[0]) >> 1; 860 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); 861 return status; 862 } /* CBRDLL2 */ 863 864 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param) 865 { 866 u32 trap, trap_AC2, trap_MRS; 867 868 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 869 870 /* Ger trap info */ 871 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 872 trap_AC2 = 0x00020000 + (trap << 16); 873 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19); 874 trap_MRS = 0x00000010 + (trap << 4); 875 trap_MRS |= ((trap & 0x2) << 18); 876 877 param->reg_MADJ = 0x00034C4C; 878 param->reg_SADJ = 0x00001800; 879 param->reg_DRV = 0x000000F0; 880 param->reg_PERIOD = param->dram_freq; 881 param->rodt = 0; 882 883 switch (param->dram_freq) { 884 case 336: 885 ast_moutdwm(ast, 0x1E6E2020, 0x0190); 886 param->wodt = 0; 887 param->reg_AC1 = 0x22202725; 888 param->reg_AC2 = 0xAA007613 | trap_AC2; 889 param->reg_DQSIC = 0x000000BA; 890 param->reg_MRS = 0x04001400 | trap_MRS; 891 param->reg_EMRS = 0x00000000; 892 param->reg_IOZ = 0x00000023; 893 param->reg_DQIDLY = 0x00000074; 894 param->reg_FREQ = 0x00004DC0; 895 param->madj_max = 96; 896 param->dll2_finetune_step = 3; 897 switch (param->dram_chipid) { 898 default: 899 case AST_DRAM_512Mx16: 900 case AST_DRAM_1Gx16: 901 param->reg_AC2 = 0xAA007613 | trap_AC2; 902 break; 903 case AST_DRAM_2Gx16: 904 param->reg_AC2 = 0xAA00761C | trap_AC2; 905 break; 906 case AST_DRAM_4Gx16: 907 param->reg_AC2 = 0xAA007636 | trap_AC2; 908 break; 909 } 910 break; 911 default: 912 case 396: 913 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); 914 param->wodt = 1; 915 param->reg_AC1 = 0x33302825; 916 param->reg_AC2 = 0xCC009617 | trap_AC2; 917 param->reg_DQSIC = 0x000000E2; 918 param->reg_MRS = 0x04001600 | trap_MRS; 919 param->reg_EMRS = 0x00000000; 920 param->reg_IOZ = 0x00000034; 921 param->reg_DRV = 0x000000FA; 922 param->reg_DQIDLY = 0x00000089; 923 param->reg_FREQ = 0x00005040; 924 param->madj_max = 96; 925 param->dll2_finetune_step = 4; 926 927 switch (param->dram_chipid) { 928 default: 929 case AST_DRAM_512Mx16: 930 case AST_DRAM_1Gx16: 931 param->reg_AC2 = 0xCC009617 | trap_AC2; 932 break; 933 case AST_DRAM_2Gx16: 934 param->reg_AC2 = 0xCC009622 | trap_AC2; 935 break; 936 case AST_DRAM_4Gx16: 937 param->reg_AC2 = 0xCC00963F | trap_AC2; 938 break; 939 } 940 break; 941 942 case 408: 943 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); 944 param->wodt = 1; 945 param->reg_AC1 = 0x33302825; 946 param->reg_AC2 = 0xCC009617 | trap_AC2; 947 param->reg_DQSIC = 0x000000E2; 948 param->reg_MRS = 0x04001600 | trap_MRS; 949 param->reg_EMRS = 0x00000000; 950 param->reg_IOZ = 0x00000023; 951 param->reg_DRV = 0x000000FA; 952 param->reg_DQIDLY = 0x00000089; 953 param->reg_FREQ = 0x000050C0; 954 param->madj_max = 96; 955 param->dll2_finetune_step = 4; 956 957 switch (param->dram_chipid) { 958 default: 959 case AST_DRAM_512Mx16: 960 case AST_DRAM_1Gx16: 961 param->reg_AC2 = 0xCC009617 | trap_AC2; 962 break; 963 case AST_DRAM_2Gx16: 964 param->reg_AC2 = 0xCC009622 | trap_AC2; 965 break; 966 case AST_DRAM_4Gx16: 967 param->reg_AC2 = 0xCC00963F | trap_AC2; 968 break; 969 } 970 971 break; 972 case 456: 973 ast_moutdwm(ast, 0x1E6E2020, 0x0230); 974 param->wodt = 0; 975 param->reg_AC1 = 0x33302926; 976 param->reg_AC2 = 0xCD44961A; 977 param->reg_DQSIC = 0x000000FC; 978 param->reg_MRS = 0x00081830; 979 param->reg_EMRS = 0x00000000; 980 param->reg_IOZ = 0x00000045; 981 param->reg_DQIDLY = 0x00000097; 982 param->reg_FREQ = 0x000052C0; 983 param->madj_max = 88; 984 param->dll2_finetune_step = 4; 985 break; 986 case 504: 987 ast_moutdwm(ast, 0x1E6E2020, 0x0270); 988 param->wodt = 1; 989 param->reg_AC1 = 0x33302926; 990 param->reg_AC2 = 0xDE44A61D; 991 param->reg_DQSIC = 0x00000117; 992 param->reg_MRS = 0x00081A30; 993 param->reg_EMRS = 0x00000000; 994 param->reg_IOZ = 0x070000BB; 995 param->reg_DQIDLY = 0x000000A0; 996 param->reg_FREQ = 0x000054C0; 997 param->madj_max = 79; 998 param->dll2_finetune_step = 4; 999 break; 1000 case 528: 1001 ast_moutdwm(ast, 0x1E6E2020, 0x0290); 1002 param->wodt = 1; 1003 param->rodt = 1; 1004 param->reg_AC1 = 0x33302926; 1005 param->reg_AC2 = 0xEF44B61E; 1006 param->reg_DQSIC = 0x00000125; 1007 param->reg_MRS = 0x00081A30; 1008 param->reg_EMRS = 0x00000040; 1009 param->reg_DRV = 0x000000F5; 1010 param->reg_IOZ = 0x00000023; 1011 param->reg_DQIDLY = 0x00000088; 1012 param->reg_FREQ = 0x000055C0; 1013 param->madj_max = 76; 1014 param->dll2_finetune_step = 3; 1015 break; 1016 case 576: 1017 ast_moutdwm(ast, 0x1E6E2020, 0x0140); 1018 param->reg_MADJ = 0x00136868; 1019 param->reg_SADJ = 0x00004534; 1020 param->wodt = 1; 1021 param->rodt = 1; 1022 param->reg_AC1 = 0x33302A37; 1023 param->reg_AC2 = 0xEF56B61E; 1024 param->reg_DQSIC = 0x0000013F; 1025 param->reg_MRS = 0x00101A50; 1026 param->reg_EMRS = 0x00000040; 1027 param->reg_DRV = 0x000000FA; 1028 param->reg_IOZ = 0x00000023; 1029 param->reg_DQIDLY = 0x00000078; 1030 param->reg_FREQ = 0x000057C0; 1031 param->madj_max = 136; 1032 param->dll2_finetune_step = 3; 1033 break; 1034 case 600: 1035 ast_moutdwm(ast, 0x1E6E2020, 0x02E1); 1036 param->reg_MADJ = 0x00136868; 1037 param->reg_SADJ = 0x00004534; 1038 param->wodt = 1; 1039 param->rodt = 1; 1040 param->reg_AC1 = 0x32302A37; 1041 param->reg_AC2 = 0xDF56B61F; 1042 param->reg_DQSIC = 0x0000014D; 1043 param->reg_MRS = 0x00101A50; 1044 param->reg_EMRS = 0x00000004; 1045 param->reg_DRV = 0x000000F5; 1046 param->reg_IOZ = 0x00000023; 1047 param->reg_DQIDLY = 0x00000078; 1048 param->reg_FREQ = 0x000058C0; 1049 param->madj_max = 132; 1050 param->dll2_finetune_step = 3; 1051 break; 1052 case 624: 1053 ast_moutdwm(ast, 0x1E6E2020, 0x0160); 1054 param->reg_MADJ = 0x00136868; 1055 param->reg_SADJ = 0x00004534; 1056 param->wodt = 1; 1057 param->rodt = 1; 1058 param->reg_AC1 = 0x32302A37; 1059 param->reg_AC2 = 0xEF56B621; 1060 param->reg_DQSIC = 0x0000015A; 1061 param->reg_MRS = 0x02101A50; 1062 param->reg_EMRS = 0x00000004; 1063 param->reg_DRV = 0x000000F5; 1064 param->reg_IOZ = 0x00000034; 1065 param->reg_DQIDLY = 0x00000078; 1066 param->reg_FREQ = 0x000059C0; 1067 param->madj_max = 128; 1068 param->dll2_finetune_step = 3; 1069 break; 1070 } /* switch freq */ 1071 1072 switch (param->dram_chipid) { 1073 case AST_DRAM_512Mx16: 1074 param->dram_config = 0x130; 1075 break; 1076 default: 1077 case AST_DRAM_1Gx16: 1078 param->dram_config = 0x131; 1079 break; 1080 case AST_DRAM_2Gx16: 1081 param->dram_config = 0x132; 1082 break; 1083 case AST_DRAM_4Gx16: 1084 param->dram_config = 0x133; 1085 break; 1086 } /* switch size */ 1087 1088 switch (param->vram_size) { 1089 default: 1090 case AST_VIDMEM_SIZE_8M: 1091 param->dram_config |= 0x00; 1092 break; 1093 case AST_VIDMEM_SIZE_16M: 1094 param->dram_config |= 0x04; 1095 break; 1096 case AST_VIDMEM_SIZE_32M: 1097 param->dram_config |= 0x08; 1098 break; 1099 case AST_VIDMEM_SIZE_64M: 1100 param->dram_config |= 0x0c; 1101 break; 1102 } 1103 1104 } 1105 1106 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param) 1107 { 1108 u32 data, data2, retry = 0; 1109 1110 ddr3_init_start: 1111 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1112 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); 1113 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); 1114 ast_moutdwm(ast, 0x1E6E0034, 0x00000000); 1115 udelay(10); 1116 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1117 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1118 udelay(10); 1119 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1120 udelay(10); 1121 1122 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); 1123 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); 1124 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1125 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1126 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1127 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); 1128 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); 1129 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1130 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); 1131 ast_moutdwm(ast, 0x1E6E0018, 0x00002370); 1132 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); 1133 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); 1134 ast_moutdwm(ast, 0x1E6E0044, 0x22222222); 1135 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); 1136 ast_moutdwm(ast, 0x1E6E004C, 0x00000002); 1137 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1138 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1139 ast_moutdwm(ast, 0x1E6E0054, 0); 1140 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1141 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1142 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1143 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); 1144 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); 1145 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1146 /* Wait MCLK2X lock to MCLK */ 1147 do { 1148 data = ast_mindwm(ast, 0x1E6E001C); 1149 } while (!(data & 0x08000000)); 1150 data = ast_mindwm(ast, 0x1E6E001C); 1151 data = (data >> 8) & 0xff; 1152 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1153 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1154 if ((data2 & 0xff) > param->madj_max) { 1155 break; 1156 } 1157 ast_moutdwm(ast, 0x1E6E0064, data2); 1158 if (data2 & 0x00100000) { 1159 data2 = ((data2 & 0xff) >> 3) + 3; 1160 } else { 1161 data2 = ((data2 & 0xff) >> 2) + 5; 1162 } 1163 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1164 data2 += data & 0xff; 1165 data = data | (data2 << 8); 1166 ast_moutdwm(ast, 0x1E6E0068, data); 1167 udelay(10); 1168 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); 1169 udelay(10); 1170 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1171 ast_moutdwm(ast, 0x1E6E0018, data); 1172 data = data | 0x200; 1173 ast_moutdwm(ast, 0x1E6E0018, data); 1174 do { 1175 data = ast_mindwm(ast, 0x1E6E001C); 1176 } while (!(data & 0x08000000)); 1177 1178 data = ast_mindwm(ast, 0x1E6E001C); 1179 data = (data >> 8) & 0xff; 1180 } 1181 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); 1182 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; 1183 ast_moutdwm(ast, 0x1E6E0018, data); 1184 1185 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); 1186 ast_moutdwm(ast, 0x1E6E000C, 0x00000040); 1187 udelay(50); 1188 /* Mode Register Setting */ 1189 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1190 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1191 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); 1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); 1193 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1194 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1195 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1196 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); 1197 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1198 1199 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); 1200 data = 0; 1201 if (param->wodt) { 1202 data = 0x300; 1203 } 1204 if (param->rodt) { 1205 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1206 } 1207 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); 1208 1209 /* Calibrate the DQSI delay */ 1210 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) 1211 goto ddr3_init_start; 1212 1213 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1214 /* ECC Memory Initialization */ 1215 #ifdef ECC 1216 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1217 ast_moutdwm(ast, 0x1E6E0070, 0x221); 1218 do { 1219 data = ast_mindwm(ast, 0x1E6E0070); 1220 } while (!(data & 0x00001000)); 1221 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1222 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1223 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1224 #endif 1225 1226 1227 } 1228 1229 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param) 1230 { 1231 u32 trap, trap_AC2, trap_MRS; 1232 1233 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 1234 1235 /* Ger trap info */ 1236 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 1237 trap_AC2 = (trap << 20) | (trap << 16); 1238 trap_AC2 += 0x00110000; 1239 trap_MRS = 0x00000040 | (trap << 4); 1240 1241 1242 param->reg_MADJ = 0x00034C4C; 1243 param->reg_SADJ = 0x00001800; 1244 param->reg_DRV = 0x000000F0; 1245 param->reg_PERIOD = param->dram_freq; 1246 param->rodt = 0; 1247 1248 switch (param->dram_freq) { 1249 case 264: 1250 ast_moutdwm(ast, 0x1E6E2020, 0x0130); 1251 param->wodt = 0; 1252 param->reg_AC1 = 0x11101513; 1253 param->reg_AC2 = 0x78117011; 1254 param->reg_DQSIC = 0x00000092; 1255 param->reg_MRS = 0x00000842; 1256 param->reg_EMRS = 0x00000000; 1257 param->reg_DRV = 0x000000F0; 1258 param->reg_IOZ = 0x00000034; 1259 param->reg_DQIDLY = 0x0000005A; 1260 param->reg_FREQ = 0x00004AC0; 1261 param->madj_max = 138; 1262 param->dll2_finetune_step = 3; 1263 break; 1264 case 336: 1265 ast_moutdwm(ast, 0x1E6E2020, 0x0190); 1266 param->wodt = 1; 1267 param->reg_AC1 = 0x22202613; 1268 param->reg_AC2 = 0xAA009016 | trap_AC2; 1269 param->reg_DQSIC = 0x000000BA; 1270 param->reg_MRS = 0x00000A02 | trap_MRS; 1271 param->reg_EMRS = 0x00000040; 1272 param->reg_DRV = 0x000000FA; 1273 param->reg_IOZ = 0x00000034; 1274 param->reg_DQIDLY = 0x00000074; 1275 param->reg_FREQ = 0x00004DC0; 1276 param->madj_max = 96; 1277 param->dll2_finetune_step = 3; 1278 switch (param->dram_chipid) { 1279 default: 1280 case AST_DRAM_512Mx16: 1281 param->reg_AC2 = 0xAA009012 | trap_AC2; 1282 break; 1283 case AST_DRAM_1Gx16: 1284 param->reg_AC2 = 0xAA009016 | trap_AC2; 1285 break; 1286 case AST_DRAM_2Gx16: 1287 param->reg_AC2 = 0xAA009023 | trap_AC2; 1288 break; 1289 case AST_DRAM_4Gx16: 1290 param->reg_AC2 = 0xAA00903B | trap_AC2; 1291 break; 1292 } 1293 break; 1294 default: 1295 case 396: 1296 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); 1297 param->wodt = 1; 1298 param->rodt = 0; 1299 param->reg_AC1 = 0x33302714; 1300 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1301 param->reg_DQSIC = 0x000000E2; 1302 param->reg_MRS = 0x00000C02 | trap_MRS; 1303 param->reg_EMRS = 0x00000040; 1304 param->reg_DRV = 0x000000FA; 1305 param->reg_IOZ = 0x00000034; 1306 param->reg_DQIDLY = 0x00000089; 1307 param->reg_FREQ = 0x00005040; 1308 param->madj_max = 96; 1309 param->dll2_finetune_step = 4; 1310 1311 switch (param->dram_chipid) { 1312 case AST_DRAM_512Mx16: 1313 param->reg_AC2 = 0xCC00B016 | trap_AC2; 1314 break; 1315 default: 1316 case AST_DRAM_1Gx16: 1317 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1318 break; 1319 case AST_DRAM_2Gx16: 1320 param->reg_AC2 = 0xCC00B02B | trap_AC2; 1321 break; 1322 case AST_DRAM_4Gx16: 1323 param->reg_AC2 = 0xCC00B03F | trap_AC2; 1324 break; 1325 } 1326 1327 break; 1328 1329 case 408: 1330 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); 1331 param->wodt = 1; 1332 param->rodt = 0; 1333 param->reg_AC1 = 0x33302714; 1334 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1335 param->reg_DQSIC = 0x000000E2; 1336 param->reg_MRS = 0x00000C02 | trap_MRS; 1337 param->reg_EMRS = 0x00000040; 1338 param->reg_DRV = 0x000000FA; 1339 param->reg_IOZ = 0x00000034; 1340 param->reg_DQIDLY = 0x00000089; 1341 param->reg_FREQ = 0x000050C0; 1342 param->madj_max = 96; 1343 param->dll2_finetune_step = 4; 1344 1345 switch (param->dram_chipid) { 1346 case AST_DRAM_512Mx16: 1347 param->reg_AC2 = 0xCC00B016 | trap_AC2; 1348 break; 1349 default: 1350 case AST_DRAM_1Gx16: 1351 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1352 break; 1353 case AST_DRAM_2Gx16: 1354 param->reg_AC2 = 0xCC00B02B | trap_AC2; 1355 break; 1356 case AST_DRAM_4Gx16: 1357 param->reg_AC2 = 0xCC00B03F | trap_AC2; 1358 break; 1359 } 1360 1361 break; 1362 case 456: 1363 ast_moutdwm(ast, 0x1E6E2020, 0x0230); 1364 param->wodt = 0; 1365 param->reg_AC1 = 0x33302815; 1366 param->reg_AC2 = 0xCD44B01E; 1367 param->reg_DQSIC = 0x000000FC; 1368 param->reg_MRS = 0x00000E72; 1369 param->reg_EMRS = 0x00000000; 1370 param->reg_DRV = 0x00000000; 1371 param->reg_IOZ = 0x00000034; 1372 param->reg_DQIDLY = 0x00000097; 1373 param->reg_FREQ = 0x000052C0; 1374 param->madj_max = 88; 1375 param->dll2_finetune_step = 3; 1376 break; 1377 case 504: 1378 ast_moutdwm(ast, 0x1E6E2020, 0x0261); 1379 param->wodt = 1; 1380 param->rodt = 1; 1381 param->reg_AC1 = 0x33302815; 1382 param->reg_AC2 = 0xDE44C022; 1383 param->reg_DQSIC = 0x00000117; 1384 param->reg_MRS = 0x00000E72; 1385 param->reg_EMRS = 0x00000040; 1386 param->reg_DRV = 0x0000000A; 1387 param->reg_IOZ = 0x00000045; 1388 param->reg_DQIDLY = 0x000000A0; 1389 param->reg_FREQ = 0x000054C0; 1390 param->madj_max = 79; 1391 param->dll2_finetune_step = 3; 1392 break; 1393 case 528: 1394 ast_moutdwm(ast, 0x1E6E2020, 0x0120); 1395 param->wodt = 1; 1396 param->rodt = 1; 1397 param->reg_AC1 = 0x33302815; 1398 param->reg_AC2 = 0xEF44D024; 1399 param->reg_DQSIC = 0x00000125; 1400 param->reg_MRS = 0x00000E72; 1401 param->reg_EMRS = 0x00000004; 1402 param->reg_DRV = 0x000000F9; 1403 param->reg_IOZ = 0x00000045; 1404 param->reg_DQIDLY = 0x000000A7; 1405 param->reg_FREQ = 0x000055C0; 1406 param->madj_max = 76; 1407 param->dll2_finetune_step = 3; 1408 break; 1409 case 552: 1410 ast_moutdwm(ast, 0x1E6E2020, 0x02A1); 1411 param->wodt = 1; 1412 param->rodt = 1; 1413 param->reg_AC1 = 0x43402915; 1414 param->reg_AC2 = 0xFF44E025; 1415 param->reg_DQSIC = 0x00000132; 1416 param->reg_MRS = 0x00000E72; 1417 param->reg_EMRS = 0x00000040; 1418 param->reg_DRV = 0x0000000A; 1419 param->reg_IOZ = 0x00000045; 1420 param->reg_DQIDLY = 0x000000AD; 1421 param->reg_FREQ = 0x000056C0; 1422 param->madj_max = 76; 1423 param->dll2_finetune_step = 3; 1424 break; 1425 case 576: 1426 ast_moutdwm(ast, 0x1E6E2020, 0x0140); 1427 param->wodt = 1; 1428 param->rodt = 1; 1429 param->reg_AC1 = 0x43402915; 1430 param->reg_AC2 = 0xFF44E027; 1431 param->reg_DQSIC = 0x0000013F; 1432 param->reg_MRS = 0x00000E72; 1433 param->reg_EMRS = 0x00000004; 1434 param->reg_DRV = 0x000000F5; 1435 param->reg_IOZ = 0x00000045; 1436 param->reg_DQIDLY = 0x000000B3; 1437 param->reg_FREQ = 0x000057C0; 1438 param->madj_max = 76; 1439 param->dll2_finetune_step = 3; 1440 break; 1441 } 1442 1443 switch (param->dram_chipid) { 1444 case AST_DRAM_512Mx16: 1445 param->dram_config = 0x100; 1446 break; 1447 default: 1448 case AST_DRAM_1Gx16: 1449 param->dram_config = 0x121; 1450 break; 1451 case AST_DRAM_2Gx16: 1452 param->dram_config = 0x122; 1453 break; 1454 case AST_DRAM_4Gx16: 1455 param->dram_config = 0x123; 1456 break; 1457 } /* switch size */ 1458 1459 switch (param->vram_size) { 1460 default: 1461 case AST_VIDMEM_SIZE_8M: 1462 param->dram_config |= 0x00; 1463 break; 1464 case AST_VIDMEM_SIZE_16M: 1465 param->dram_config |= 0x04; 1466 break; 1467 case AST_VIDMEM_SIZE_32M: 1468 param->dram_config |= 0x08; 1469 break; 1470 case AST_VIDMEM_SIZE_64M: 1471 param->dram_config |= 0x0c; 1472 break; 1473 } 1474 } 1475 1476 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param) 1477 { 1478 u32 data, data2, retry = 0; 1479 1480 ddr2_init_start: 1481 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1482 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); 1483 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); 1484 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1485 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1486 udelay(10); 1487 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1488 udelay(10); 1489 1490 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); 1491 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); 1492 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1493 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1494 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1495 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); 1496 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); 1497 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1498 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); 1499 ast_moutdwm(ast, 0x1E6E0018, 0x00002330); 1500 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); 1501 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); 1502 ast_moutdwm(ast, 0x1E6E0044, 0x88848466); 1503 ast_moutdwm(ast, 0x1E6E0048, 0x44440008); 1504 ast_moutdwm(ast, 0x1E6E004C, 0x00000000); 1505 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1506 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1507 ast_moutdwm(ast, 0x1E6E0054, 0); 1508 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1509 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1510 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1511 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); 1512 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); 1513 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1514 1515 /* Wait MCLK2X lock to MCLK */ 1516 do { 1517 data = ast_mindwm(ast, 0x1E6E001C); 1518 } while (!(data & 0x08000000)); 1519 data = ast_mindwm(ast, 0x1E6E001C); 1520 data = (data >> 8) & 0xff; 1521 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1522 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1523 if ((data2 & 0xff) > param->madj_max) { 1524 break; 1525 } 1526 ast_moutdwm(ast, 0x1E6E0064, data2); 1527 if (data2 & 0x00100000) { 1528 data2 = ((data2 & 0xff) >> 3) + 3; 1529 } else { 1530 data2 = ((data2 & 0xff) >> 2) + 5; 1531 } 1532 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1533 data2 += data & 0xff; 1534 data = data | (data2 << 8); 1535 ast_moutdwm(ast, 0x1E6E0068, data); 1536 udelay(10); 1537 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); 1538 udelay(10); 1539 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1540 ast_moutdwm(ast, 0x1E6E0018, data); 1541 data = data | 0x200; 1542 ast_moutdwm(ast, 0x1E6E0018, data); 1543 do { 1544 data = ast_mindwm(ast, 0x1E6E001C); 1545 } while (!(data & 0x08000000)); 1546 1547 data = ast_mindwm(ast, 0x1E6E001C); 1548 data = (data >> 8) & 0xff; 1549 } 1550 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); 1551 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; 1552 ast_moutdwm(ast, 0x1E6E0018, data); 1553 1554 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); 1555 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1556 udelay(50); 1557 /* Mode Register Setting */ 1558 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1559 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1560 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); 1561 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); 1562 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1563 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1564 1565 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); 1566 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1567 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1568 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); 1569 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1570 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1571 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1572 1573 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); 1574 data = 0; 1575 if (param->wodt) { 1576 data = 0x500; 1577 } 1578 if (param->rodt) { 1579 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1580 } 1581 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); 1582 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1583 1584 /* Calibrate the DQSI delay */ 1585 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) 1586 goto ddr2_init_start; 1587 1588 /* ECC Memory Initialization */ 1589 #ifdef ECC 1590 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1591 ast_moutdwm(ast, 0x1E6E0070, 0x221); 1592 do { 1593 data = ast_mindwm(ast, 0x1E6E0070); 1594 } while (!(data & 0x00001000)); 1595 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1596 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1597 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1598 #endif 1599 1600 } 1601 1602 static void ast_post_chip_2300(struct drm_device *dev) 1603 { 1604 struct ast_device *ast = to_ast_device(dev); 1605 struct ast2300_dram_param param; 1606 u32 temp; 1607 u8 reg; 1608 1609 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 1610 if ((reg & 0x80) == 0) {/* vga only */ 1611 ast_write32(ast, 0xf004, 0x1e6e0000); 1612 ast_write32(ast, 0xf000, 0x1); 1613 ast_write32(ast, 0x12000, 0x1688a8a8); 1614 do { 1615 ; 1616 } while (ast_read32(ast, 0x12000) != 0x1); 1617 1618 ast_write32(ast, 0x10000, 0xfc600309); 1619 do { 1620 ; 1621 } while (ast_read32(ast, 0x10000) != 0x1); 1622 1623 /* Slow down CPU/AHB CLK in VGA only mode */ 1624 temp = ast_read32(ast, 0x12008); 1625 temp |= 0x73; 1626 ast_write32(ast, 0x12008, temp); 1627 1628 param.dram_freq = 396; 1629 param.dram_type = AST_DDR3; 1630 temp = ast_mindwm(ast, 0x1e6e2070); 1631 if (temp & 0x01000000) 1632 param.dram_type = AST_DDR2; 1633 switch (temp & 0x18000000) { 1634 case 0: 1635 param.dram_chipid = AST_DRAM_512Mx16; 1636 break; 1637 default: 1638 case 0x08000000: 1639 param.dram_chipid = AST_DRAM_1Gx16; 1640 break; 1641 case 0x10000000: 1642 param.dram_chipid = AST_DRAM_2Gx16; 1643 break; 1644 case 0x18000000: 1645 param.dram_chipid = AST_DRAM_4Gx16; 1646 break; 1647 } 1648 switch (temp & 0x0c) { 1649 default: 1650 case 0x00: 1651 param.vram_size = AST_VIDMEM_SIZE_8M; 1652 break; 1653 1654 case 0x04: 1655 param.vram_size = AST_VIDMEM_SIZE_16M; 1656 break; 1657 1658 case 0x08: 1659 param.vram_size = AST_VIDMEM_SIZE_32M; 1660 break; 1661 1662 case 0x0c: 1663 param.vram_size = AST_VIDMEM_SIZE_64M; 1664 break; 1665 } 1666 1667 if (param.dram_type == AST_DDR3) { 1668 get_ddr3_info(ast, ¶m); 1669 ddr3_init(ast, ¶m); 1670 } else { 1671 get_ddr2_info(ast, ¶m); 1672 ddr2_init(ast, ¶m); 1673 } 1674 1675 temp = ast_mindwm(ast, 0x1e6e2040); 1676 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); 1677 } 1678 1679 /* wait ready */ 1680 do { 1681 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 1682 } while ((reg & 0x40) == 0); 1683 } 1684 1685 static bool cbr_test_2500(struct ast_device *ast) 1686 { 1687 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); 1688 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); 1689 if (!mmc_test_burst(ast, 0)) 1690 return false; 1691 if (!mmc_test_single_2500(ast, 0)) 1692 return false; 1693 return true; 1694 } 1695 1696 static bool ddr_test_2500(struct ast_device *ast) 1697 { 1698 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); 1699 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); 1700 if (!mmc_test_burst(ast, 0)) 1701 return false; 1702 if (!mmc_test_burst(ast, 1)) 1703 return false; 1704 if (!mmc_test_burst(ast, 2)) 1705 return false; 1706 if (!mmc_test_burst(ast, 3)) 1707 return false; 1708 if (!mmc_test_single_2500(ast, 0)) 1709 return false; 1710 return true; 1711 } 1712 1713 static void ddr_init_common_2500(struct ast_device *ast) 1714 { 1715 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); 1716 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); 1717 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); 1718 ast_moutdwm(ast, 0x1E6E0040, 0x88448844); 1719 ast_moutdwm(ast, 0x1E6E0044, 0x24422288); 1720 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); 1721 ast_moutdwm(ast, 0x1E6E004C, 0x22222222); 1722 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1723 ast_moutdwm(ast, 0x1E6E0208, 0x00000000); 1724 ast_moutdwm(ast, 0x1E6E0218, 0x00000000); 1725 ast_moutdwm(ast, 0x1E6E0220, 0x00000000); 1726 ast_moutdwm(ast, 0x1E6E0228, 0x00000000); 1727 ast_moutdwm(ast, 0x1E6E0230, 0x00000000); 1728 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); 1729 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); 1730 ast_moutdwm(ast, 0x1E6E0240, 0x86000000); 1731 ast_moutdwm(ast, 0x1E6E0244, 0x00008600); 1732 ast_moutdwm(ast, 0x1E6E0248, 0x80000000); 1733 ast_moutdwm(ast, 0x1E6E024C, 0x80808080); 1734 } 1735 1736 static void ddr_phy_init_2500(struct ast_device *ast) 1737 { 1738 u32 data, pass, timecnt; 1739 1740 pass = 0; 1741 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); 1742 while (!pass) { 1743 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) { 1744 data = ast_mindwm(ast, 0x1E6E0060) & 0x1; 1745 if (!data) 1746 break; 1747 } 1748 if (timecnt != TIMEOUT) { 1749 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; 1750 if (!data) 1751 pass = 1; 1752 } 1753 if (!pass) { 1754 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1755 udelay(10); /* delay 10 us */ 1756 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); 1757 } 1758 } 1759 1760 ast_moutdwm(ast, 0x1E6E0060, 0x00000006); 1761 } 1762 1763 /* 1764 * Check DRAM Size 1765 * 1Gb : 0x80000000 ~ 0x87FFFFFF 1766 * 2Gb : 0x80000000 ~ 0x8FFFFFFF 1767 * 4Gb : 0x80000000 ~ 0x9FFFFFFF 1768 * 8Gb : 0x80000000 ~ 0xBFFFFFFF 1769 */ 1770 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC) 1771 { 1772 u32 reg_04, reg_14; 1773 1774 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; 1775 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; 1776 1777 ast_moutdwm(ast, 0xA0100000, 0x41424344); 1778 ast_moutdwm(ast, 0x90100000, 0x35363738); 1779 ast_moutdwm(ast, 0x88100000, 0x292A2B2C); 1780 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); 1781 1782 /* Check 8Gbit */ 1783 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { 1784 reg_04 |= 0x03; 1785 reg_14 |= (tRFC >> 24) & 0xFF; 1786 /* Check 4Gbit */ 1787 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { 1788 reg_04 |= 0x02; 1789 reg_14 |= (tRFC >> 16) & 0xFF; 1790 /* Check 2Gbit */ 1791 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { 1792 reg_04 |= 0x01; 1793 reg_14 |= (tRFC >> 8) & 0xFF; 1794 } else { 1795 reg_14 |= tRFC & 0xFF; 1796 } 1797 ast_moutdwm(ast, 0x1E6E0004, reg_04); 1798 ast_moutdwm(ast, 0x1E6E0014, reg_14); 1799 } 1800 1801 static void enable_cache_2500(struct ast_device *ast) 1802 { 1803 u32 reg_04, data; 1804 1805 reg_04 = ast_mindwm(ast, 0x1E6E0004); 1806 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); 1807 1808 do 1809 data = ast_mindwm(ast, 0x1E6E0004); 1810 while (!(data & 0x80000)); 1811 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); 1812 } 1813 1814 static void set_mpll_2500(struct ast_device *ast) 1815 { 1816 u32 addr, data, param; 1817 1818 /* Reset MMC */ 1819 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1820 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); 1821 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) { 1822 ast_moutdwm(ast, addr, 0x0); 1823 addr += 4; 1824 } 1825 ast_moutdwm(ast, 0x1E6E0034, 0x00020000); 1826 1827 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 1828 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; 1829 if (data) { 1830 /* CLKIN = 25MHz */ 1831 param = 0x930023E0; 1832 ast_moutdwm(ast, 0x1E6E2160, 0x00011320); 1833 } else { 1834 /* CLKIN = 24MHz */ 1835 param = 0x93002400; 1836 } 1837 ast_moutdwm(ast, 0x1E6E2020, param); 1838 udelay(100); 1839 } 1840 1841 static void reset_mmc_2500(struct ast_device *ast) 1842 { 1843 ast_moutdwm(ast, 0x1E78505C, 0x00000004); 1844 ast_moutdwm(ast, 0x1E785044, 0x00000001); 1845 ast_moutdwm(ast, 0x1E785048, 0x00004755); 1846 ast_moutdwm(ast, 0x1E78504C, 0x00000013); 1847 mdelay(100); 1848 ast_moutdwm(ast, 0x1E785054, 0x00000077); 1849 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1850 } 1851 1852 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table) 1853 { 1854 1855 ast_moutdwm(ast, 0x1E6E0004, 0x00000303); 1856 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); 1857 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); 1858 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); 1859 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ 1860 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ 1861 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ 1862 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ 1863 1864 /* DDR PHY Setting */ 1865 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); 1866 ast_moutdwm(ast, 0x1E6E0204, 0x00001001); 1867 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); 1868 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); 1869 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); 1870 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); 1871 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); 1872 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); 1873 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); 1874 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); 1875 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); 1876 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); 1877 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); 1878 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); 1879 1880 /* Controller Setting */ 1881 ast_moutdwm(ast, 0x1E6E0034, 0x00020091); 1882 1883 /* Wait DDR PHY init done */ 1884 ddr_phy_init_2500(ast); 1885 1886 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); 1887 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); 1888 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); 1889 1890 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); 1891 enable_cache_2500(ast); 1892 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); 1893 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); 1894 } 1895 1896 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) 1897 { 1898 u32 data, data2, pass, retrycnt; 1899 u32 ddr_vref, phy_vref; 1900 u32 min_ddr_vref = 0, min_phy_vref = 0; 1901 u32 max_ddr_vref = 0, max_phy_vref = 0; 1902 1903 ast_moutdwm(ast, 0x1E6E0004, 0x00000313); 1904 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); 1905 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); 1906 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); 1907 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ 1908 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ 1909 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ 1910 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ 1911 1912 /* DDR PHY Setting */ 1913 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); 1914 ast_moutdwm(ast, 0x1E6E0204, 0x09002000); 1915 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); 1916 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); 1917 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); 1918 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); 1919 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); 1920 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); 1921 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); 1922 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); 1923 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); 1924 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); 1925 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); 1926 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); 1927 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); 1928 1929 /* Controller Setting */ 1930 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); 1931 1932 /* Train PHY Vref first */ 1933 pass = 0; 1934 1935 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { 1936 max_phy_vref = 0x0; 1937 pass = 0; 1938 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); 1939 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) { 1940 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1941 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1942 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); 1943 /* Fire DFI Init */ 1944 ddr_phy_init_2500(ast); 1945 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); 1946 if (cbr_test_2500(ast)) { 1947 pass++; 1948 data = ast_mindwm(ast, 0x1E6E03D0); 1949 data2 = data >> 8; 1950 data = data & 0xff; 1951 if (data > data2) 1952 data = data2; 1953 if (max_phy_vref < data) { 1954 max_phy_vref = data; 1955 min_phy_vref = phy_vref; 1956 } 1957 } else if (pass > 0) 1958 break; 1959 } 1960 } 1961 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); 1962 1963 /* Train DDR Vref next */ 1964 pass = 0; 1965 1966 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { 1967 min_ddr_vref = 0xFF; 1968 max_ddr_vref = 0x0; 1969 pass = 0; 1970 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) { 1971 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1972 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1973 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); 1974 /* Fire DFI Init */ 1975 ddr_phy_init_2500(ast); 1976 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); 1977 if (cbr_test_2500(ast)) { 1978 pass++; 1979 if (min_ddr_vref > ddr_vref) 1980 min_ddr_vref = ddr_vref; 1981 if (max_ddr_vref < ddr_vref) 1982 max_ddr_vref = ddr_vref; 1983 } else if (pass != 0) 1984 break; 1985 } 1986 } 1987 1988 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1989 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1990 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1; 1991 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); 1992 1993 /* Wait DDR PHY init done */ 1994 ddr_phy_init_2500(ast); 1995 1996 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); 1997 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); 1998 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); 1999 2000 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); 2001 enable_cache_2500(ast); 2002 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); 2003 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); 2004 } 2005 2006 static bool ast_dram_init_2500(struct ast_device *ast) 2007 { 2008 u32 data; 2009 u32 max_tries = 5; 2010 2011 do { 2012 if (max_tries-- == 0) 2013 return false; 2014 set_mpll_2500(ast); 2015 reset_mmc_2500(ast); 2016 ddr_init_common_2500(ast); 2017 2018 data = ast_mindwm(ast, 0x1E6E2070); 2019 if (data & 0x01000000) 2020 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); 2021 else 2022 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); 2023 } while (!ddr_test_2500(ast)); 2024 2025 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); 2026 2027 /* Patch code */ 2028 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; 2029 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); 2030 2031 return true; 2032 } 2033 2034 void ast_patch_ahb_2500(struct ast_device *ast) 2035 { 2036 u32 data; 2037 2038 /* Clear bus lock condition */ 2039 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); 2040 ast_moutdwm(ast, 0x1e600084, 0x00010000); 2041 ast_moutdwm(ast, 0x1e600088, 0x00000000); 2042 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); 2043 data = ast_mindwm(ast, 0x1e6e2070); 2044 if (data & 0x08000000) { /* check fast reset */ 2045 /* 2046 * If "Fast restet" is enabled for ARM-ICE debugger, 2047 * then WDT needs to enable, that 2048 * WDT04 is WDT#1 Reload reg. 2049 * WDT08 is WDT#1 counter restart reg to avoid system deadlock 2050 * WDT0C is WDT#1 control reg 2051 * [6:5]:= 01:Full chip 2052 * [4]:= 1:1MHz clock source 2053 * [1]:= 1:WDT will be cleeared and disabled after timeout occurs 2054 * [0]:= 1:WDT enable 2055 */ 2056 ast_moutdwm(ast, 0x1E785004, 0x00000010); 2057 ast_moutdwm(ast, 0x1E785008, 0x00004755); 2058 ast_moutdwm(ast, 0x1E78500c, 0x00000033); 2059 udelay(1000); 2060 } 2061 do { 2062 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); 2063 data = ast_mindwm(ast, 0x1e6e2000); 2064 } while (data != 1); 2065 ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ 2066 } 2067 2068 void ast_post_chip_2500(struct drm_device *dev) 2069 { 2070 struct ast_device *ast = to_ast_device(dev); 2071 u32 temp; 2072 u8 reg; 2073 2074 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 2075 if ((reg & AST_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */ 2076 /* Clear bus lock condition */ 2077 ast_patch_ahb_2500(ast); 2078 2079 /* Disable watchdog */ 2080 ast_moutdwm(ast, 0x1E78502C, 0x00000000); 2081 ast_moutdwm(ast, 0x1E78504C, 0x00000000); 2082 2083 /* 2084 * Reset USB port to patch USB unknown device issue 2085 * SCU90 is Multi-function Pin Control #5 2086 * [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub 2087 * port). 2088 * SCU94 is Multi-function Pin Control #6 2089 * [14:13]:= 1x:USB2.0 Host2 controller 2090 * SCU70 is Hardware Strap reg 2091 * [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by 2092 * [18]: 0(24)/1(48) MHz) 2093 * SCU7C is Write clear reg to SCU70 2094 * [23]:= write 1 and then SCU70[23] will be clear as 0b. 2095 */ 2096 ast_moutdwm(ast, 0x1E6E2090, 0x20000000); 2097 ast_moutdwm(ast, 0x1E6E2094, 0x00004000); 2098 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { 2099 ast_moutdwm(ast, 0x1E6E207C, 0x00800000); 2100 mdelay(100); 2101 ast_moutdwm(ast, 0x1E6E2070, 0x00800000); 2102 } 2103 /* Modify eSPI reset pin */ 2104 temp = ast_mindwm(ast, 0x1E6E2070); 2105 if (temp & 0x02000000) 2106 ast_moutdwm(ast, 0x1E6E207C, 0x00004000); 2107 2108 /* Slow down CPU/AHB CLK in VGA only mode */ 2109 temp = ast_read32(ast, 0x12008); 2110 temp |= 0x73; 2111 ast_write32(ast, 0x12008, temp); 2112 2113 if (!ast_dram_init_2500(ast)) 2114 drm_err(dev, "DRAM init failed !\n"); 2115 2116 temp = ast_mindwm(ast, 0x1e6e2040); 2117 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); 2118 } 2119 2120 /* wait ready */ 2121 do { 2122 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 2123 } while ((reg & 0x40) == 0); 2124 } 2125