1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include "ast_drv.h" 36 37 #include "ast_tables.h" 38 39 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 40 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 41 static int ast_cursor_set(struct drm_crtc *crtc, 42 struct drm_file *file_priv, 43 uint32_t handle, 44 uint32_t width, 45 uint32_t height); 46 static int ast_cursor_move(struct drm_crtc *crtc, 47 int x, int y); 48 49 static inline void ast_load_palette_index(struct ast_private *ast, 50 u8 index, u8 red, u8 green, 51 u8 blue) 52 { 53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 54 ast_io_read8(ast, AST_IO_SEQ_PORT); 55 ast_io_write8(ast, AST_IO_DAC_DATA, red); 56 ast_io_read8(ast, AST_IO_SEQ_PORT); 57 ast_io_write8(ast, AST_IO_DAC_DATA, green); 58 ast_io_read8(ast, AST_IO_SEQ_PORT); 59 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 60 ast_io_read8(ast, AST_IO_SEQ_PORT); 61 } 62 63 static void ast_crtc_load_lut(struct drm_crtc *crtc) 64 { 65 struct ast_private *ast = crtc->dev->dev_private; 66 u16 *r, *g, *b; 67 int i; 68 69 if (!crtc->enabled) 70 return; 71 72 r = crtc->gamma_store; 73 g = r + crtc->gamma_size; 74 b = g + crtc->gamma_size; 75 76 for (i = 0; i < 256; i++) 77 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8); 78 } 79 80 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, 81 struct drm_display_mode *adjusted_mode, 82 struct ast_vbios_mode_info *vbios_mode) 83 { 84 struct ast_private *ast = crtc->dev->dev_private; 85 const struct drm_framebuffer *fb = crtc->primary->fb; 86 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; 87 const struct ast_vbios_enhtable *best = NULL; 88 u32 hborder, vborder; 89 bool check_sync; 90 91 switch (fb->format->cpp[0] * 8) { 92 case 8: 93 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 94 color_index = VGAModeIndex - 1; 95 break; 96 case 16: 97 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 98 color_index = HiCModeIndex; 99 break; 100 case 24: 101 case 32: 102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 103 color_index = TrueCModeIndex; 104 break; 105 default: 106 return false; 107 } 108 109 switch (crtc->mode.crtc_hdisplay) { 110 case 640: 111 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 112 break; 113 case 800: 114 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 115 break; 116 case 1024: 117 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 118 break; 119 case 1280: 120 if (crtc->mode.crtc_vdisplay == 800) 121 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 122 else 123 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 124 break; 125 case 1360: 126 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 127 break; 128 case 1440: 129 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 130 break; 131 case 1600: 132 if (crtc->mode.crtc_vdisplay == 900) 133 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 134 else 135 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 136 break; 137 case 1680: 138 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 139 break; 140 case 1920: 141 if (crtc->mode.crtc_vdisplay == 1080) 142 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 143 else 144 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 145 break; 146 default: 147 return false; 148 } 149 150 refresh_rate = drm_mode_vrefresh(mode); 151 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 152 do { 153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 154 155 while (loop->refresh_rate != 0xff) { 156 if ((check_sync) && 157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 158 (loop->flags & PVSync)) || 159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 160 (loop->flags & NVSync)) || 161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 162 (loop->flags & PHSync)) || 163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 164 (loop->flags & NHSync)))) { 165 loop++; 166 continue; 167 } 168 if (loop->refresh_rate <= refresh_rate 169 && (!best || loop->refresh_rate > best->refresh_rate)) 170 best = loop; 171 loop++; 172 } 173 if (best || !check_sync) 174 break; 175 check_sync = 0; 176 } while (1); 177 if (best) 178 vbios_mode->enh_table = best; 179 180 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 181 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 182 183 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 184 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 185 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 186 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 187 vbios_mode->enh_table->hfp; 188 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 189 vbios_mode->enh_table->hfp + 190 vbios_mode->enh_table->hsync); 191 192 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 193 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 194 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 195 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 196 vbios_mode->enh_table->vfp; 197 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 198 vbios_mode->enh_table->vfp + 199 vbios_mode->enh_table->vsync); 200 201 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 202 mode_id = vbios_mode->enh_table->mode_id; 203 204 if (ast->chip == AST1180) { 205 /* TODO 1180 */ 206 } else { 207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); 208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 210 211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 212 if (vbios_mode->enh_table->flags & NewModeInfo) { 213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, 215 fb->format->cpp[0] * 8); 216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 219 220 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 221 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 222 } 223 } 224 225 return true; 226 227 228 } 229 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 230 struct ast_vbios_mode_info *vbios_mode) 231 { 232 struct ast_private *ast = crtc->dev->dev_private; 233 const struct ast_vbios_stdtable *stdtable; 234 u32 i; 235 u8 jreg; 236 237 stdtable = vbios_mode->std_table; 238 239 jreg = stdtable->misc; 240 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 241 242 /* Set SEQ */ 243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 244 for (i = 0; i < 4; i++) { 245 jreg = stdtable->seq[i]; 246 if (!i) 247 jreg |= 0x20; 248 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 249 } 250 251 /* Set CRTC */ 252 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 253 for (i = 0; i < 25; i++) 254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 255 256 /* set AR */ 257 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 258 for (i = 0; i < 20; i++) { 259 jreg = stdtable->ar[i]; 260 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 262 } 263 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 265 266 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 267 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 268 269 /* Set GR */ 270 for (i = 0; i < 9; i++) 271 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 272 } 273 274 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 275 struct ast_vbios_mode_info *vbios_mode) 276 { 277 struct ast_private *ast = crtc->dev->dev_private; 278 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 279 u16 temp, precache = 0; 280 281 if ((ast->chip == AST2500) && 282 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 283 precache = 40; 284 285 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 286 287 temp = (mode->crtc_htotal >> 3) - 5; 288 if (temp & 0x100) 289 jregAC |= 0x01; /* HT D[8] */ 290 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 291 292 temp = (mode->crtc_hdisplay >> 3) - 1; 293 if (temp & 0x100) 294 jregAC |= 0x04; /* HDE D[8] */ 295 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 296 297 temp = (mode->crtc_hblank_start >> 3) - 1; 298 if (temp & 0x100) 299 jregAC |= 0x10; /* HBS D[8] */ 300 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 301 302 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 303 if (temp & 0x20) 304 jreg05 |= 0x80; /* HBE D[5] */ 305 if (temp & 0x40) 306 jregAD |= 0x01; /* HBE D[5] */ 307 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 308 309 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 310 if (temp & 0x100) 311 jregAC |= 0x40; /* HRS D[5] */ 312 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 313 314 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 315 if (temp & 0x20) 316 jregAD |= 0x04; /* HRE D[5] */ 317 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 318 319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 320 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 321 322 /* vert timings */ 323 temp = (mode->crtc_vtotal) - 2; 324 if (temp & 0x100) 325 jreg07 |= 0x01; 326 if (temp & 0x200) 327 jreg07 |= 0x20; 328 if (temp & 0x400) 329 jregAE |= 0x01; 330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 331 332 temp = (mode->crtc_vsync_start) - 1; 333 if (temp & 0x100) 334 jreg07 |= 0x04; 335 if (temp & 0x200) 336 jreg07 |= 0x80; 337 if (temp & 0x400) 338 jregAE |= 0x08; 339 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 340 341 temp = (mode->crtc_vsync_end - 1) & 0x3f; 342 if (temp & 0x10) 343 jregAE |= 0x20; 344 if (temp & 0x20) 345 jregAE |= 0x40; 346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 347 348 temp = mode->crtc_vdisplay - 1; 349 if (temp & 0x100) 350 jreg07 |= 0x02; 351 if (temp & 0x200) 352 jreg07 |= 0x40; 353 if (temp & 0x400) 354 jregAE |= 0x02; 355 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 356 357 temp = mode->crtc_vblank_start - 1; 358 if (temp & 0x100) 359 jreg07 |= 0x08; 360 if (temp & 0x200) 361 jreg09 |= 0x20; 362 if (temp & 0x400) 363 jregAE |= 0x04; 364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 365 366 temp = mode->crtc_vblank_end - 1; 367 if (temp & 0x100) 368 jregAE |= 0x10; 369 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 370 371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 372 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 374 375 if (precache) 376 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 377 else 378 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 379 380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 381 } 382 383 static void ast_set_offset_reg(struct drm_crtc *crtc) 384 { 385 struct ast_private *ast = crtc->dev->dev_private; 386 const struct drm_framebuffer *fb = crtc->primary->fb; 387 388 u16 offset; 389 390 offset = fb->pitches[0] >> 3; 391 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 392 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 393 } 394 395 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, 396 struct ast_vbios_mode_info *vbios_mode) 397 { 398 struct ast_private *ast = dev->dev_private; 399 const struct ast_vbios_dclk_info *clk_info; 400 401 if (ast->chip == AST2500) 402 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 403 else 404 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 405 406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 408 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 409 (clk_info->param3 & 0xc0) | 410 ((clk_info->param3 & 0x3) << 4)); 411 } 412 413 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 414 struct ast_vbios_mode_info *vbios_mode) 415 { 416 struct ast_private *ast = crtc->dev->dev_private; 417 const struct drm_framebuffer *fb = crtc->primary->fb; 418 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 419 420 switch (fb->format->cpp[0] * 8) { 421 case 8: 422 jregA0 = 0x70; 423 jregA3 = 0x01; 424 jregA8 = 0x00; 425 break; 426 case 15: 427 case 16: 428 jregA0 = 0x70; 429 jregA3 = 0x04; 430 jregA8 = 0x02; 431 break; 432 case 32: 433 jregA0 = 0x70; 434 jregA3 = 0x08; 435 jregA8 = 0x02; 436 break; 437 } 438 439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 441 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 442 443 /* Set Threshold */ 444 if (ast->chip == AST2300 || ast->chip == AST2400 || 445 ast->chip == AST2500) { 446 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 447 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 448 } else if (ast->chip == AST2100 || 449 ast->chip == AST1100 || 450 ast->chip == AST2200 || 451 ast->chip == AST2150) { 452 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 453 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 454 } else { 455 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 456 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 457 } 458 } 459 460 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, 461 struct ast_vbios_mode_info *vbios_mode) 462 { 463 struct ast_private *ast = dev->dev_private; 464 u8 jreg; 465 466 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 467 jreg &= ~0xC0; 468 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 469 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 470 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 471 } 472 473 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 474 struct ast_vbios_mode_info *vbios_mode) 475 { 476 const struct drm_framebuffer *fb = crtc->primary->fb; 477 478 switch (fb->format->cpp[0] * 8) { 479 case 8: 480 break; 481 default: 482 return false; 483 } 484 return true; 485 } 486 487 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset) 488 { 489 struct ast_private *ast = crtc->dev->dev_private; 490 u32 addr; 491 492 addr = offset >> 2; 493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 494 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 496 497 } 498 499 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 500 { 501 struct ast_private *ast = crtc->dev->dev_private; 502 503 if (ast->chip == AST1180) 504 return; 505 506 switch (mode) { 507 case DRM_MODE_DPMS_ON: 508 case DRM_MODE_DPMS_STANDBY: 509 case DRM_MODE_DPMS_SUSPEND: 510 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 511 if (ast->tx_chip_type == AST_TX_DP501) 512 ast_set_dp501_video_output(crtc->dev, 1); 513 ast_crtc_load_lut(crtc); 514 break; 515 case DRM_MODE_DPMS_OFF: 516 if (ast->tx_chip_type == AST_TX_DP501) 517 ast_set_dp501_video_output(crtc->dev, 0); 518 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 519 break; 520 } 521 } 522 523 /* ast is different - we will force move buffers out of VRAM */ 524 static int ast_crtc_do_set_base(struct drm_crtc *crtc, 525 struct drm_framebuffer *fb, 526 int x, int y, int atomic) 527 { 528 struct ast_private *ast = crtc->dev->dev_private; 529 struct drm_gem_object *obj; 530 struct ast_framebuffer *ast_fb; 531 struct ast_bo *bo; 532 int ret; 533 u64 gpu_addr; 534 535 /* push the previous fb to system ram */ 536 if (!atomic && fb) { 537 ast_fb = to_ast_framebuffer(fb); 538 obj = ast_fb->obj; 539 bo = gem_to_ast_bo(obj); 540 ret = ast_bo_reserve(bo, false); 541 if (ret) 542 return ret; 543 ast_bo_push_sysram(bo); 544 ast_bo_unreserve(bo); 545 } 546 547 ast_fb = to_ast_framebuffer(crtc->primary->fb); 548 obj = ast_fb->obj; 549 bo = gem_to_ast_bo(obj); 550 551 ret = ast_bo_reserve(bo, false); 552 if (ret) 553 return ret; 554 555 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 556 if (ret) { 557 ast_bo_unreserve(bo); 558 return ret; 559 } 560 561 if (&ast->fbdev->afb == ast_fb) { 562 /* if pushing console in kmap it */ 563 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 564 if (ret) 565 DRM_ERROR("failed to kmap fbcon\n"); 566 else 567 ast_fbdev_set_base(ast, gpu_addr); 568 } 569 ast_bo_unreserve(bo); 570 571 ast_set_start_address_crt1(crtc, (u32)gpu_addr); 572 573 return 0; 574 } 575 576 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 577 struct drm_framebuffer *old_fb) 578 { 579 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0); 580 } 581 582 static int ast_crtc_mode_set(struct drm_crtc *crtc, 583 struct drm_display_mode *mode, 584 struct drm_display_mode *adjusted_mode, 585 int x, int y, 586 struct drm_framebuffer *old_fb) 587 { 588 struct drm_device *dev = crtc->dev; 589 struct ast_private *ast = crtc->dev->dev_private; 590 struct ast_vbios_mode_info vbios_mode; 591 bool ret; 592 if (ast->chip == AST1180) { 593 DRM_ERROR("AST 1180 modesetting not supported\n"); 594 return -EINVAL; 595 } 596 597 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); 598 if (ret == false) 599 return -EINVAL; 600 ast_open_key(ast); 601 602 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); 603 604 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); 605 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); 606 ast_set_offset_reg(crtc); 607 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); 608 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); 609 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); 610 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode); 611 612 ast_crtc_mode_set_base(crtc, x, y, old_fb); 613 614 return 0; 615 } 616 617 static void ast_crtc_disable(struct drm_crtc *crtc) 618 { 619 int ret; 620 621 DRM_DEBUG_KMS("\n"); 622 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 623 if (crtc->primary->fb) { 624 struct ast_framebuffer *ast_fb = to_ast_framebuffer(crtc->primary->fb); 625 struct drm_gem_object *obj = ast_fb->obj; 626 struct ast_bo *bo = gem_to_ast_bo(obj); 627 628 ret = ast_bo_reserve(bo, false); 629 if (ret) 630 return; 631 632 ast_bo_push_sysram(bo); 633 ast_bo_unreserve(bo); 634 } 635 crtc->primary->fb = NULL; 636 } 637 638 static void ast_crtc_prepare(struct drm_crtc *crtc) 639 { 640 641 } 642 643 static void ast_crtc_commit(struct drm_crtc *crtc) 644 { 645 struct ast_private *ast = crtc->dev->dev_private; 646 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 647 ast_crtc_load_lut(crtc); 648 } 649 650 651 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 652 .dpms = ast_crtc_dpms, 653 .mode_set = ast_crtc_mode_set, 654 .mode_set_base = ast_crtc_mode_set_base, 655 .disable = ast_crtc_disable, 656 .prepare = ast_crtc_prepare, 657 .commit = ast_crtc_commit, 658 659 }; 660 661 static void ast_crtc_reset(struct drm_crtc *crtc) 662 { 663 664 } 665 666 static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 667 u16 *blue, uint32_t size, 668 struct drm_modeset_acquire_ctx *ctx) 669 { 670 ast_crtc_load_lut(crtc); 671 672 return 0; 673 } 674 675 676 static void ast_crtc_destroy(struct drm_crtc *crtc) 677 { 678 drm_crtc_cleanup(crtc); 679 kfree(crtc); 680 } 681 682 static const struct drm_crtc_funcs ast_crtc_funcs = { 683 .cursor_set = ast_cursor_set, 684 .cursor_move = ast_cursor_move, 685 .reset = ast_crtc_reset, 686 .set_config = drm_crtc_helper_set_config, 687 .gamma_set = ast_crtc_gamma_set, 688 .destroy = ast_crtc_destroy, 689 }; 690 691 static int ast_crtc_init(struct drm_device *dev) 692 { 693 struct ast_crtc *crtc; 694 695 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 696 if (!crtc) 697 return -ENOMEM; 698 699 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); 700 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 701 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 702 return 0; 703 } 704 705 static void ast_encoder_destroy(struct drm_encoder *encoder) 706 { 707 drm_encoder_cleanup(encoder); 708 kfree(encoder); 709 } 710 711 712 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector) 713 { 714 int enc_id = connector->encoder_ids[0]; 715 /* pick the encoder ids */ 716 if (enc_id) 717 return drm_encoder_find(connector->dev, NULL, enc_id); 718 return NULL; 719 } 720 721 722 static const struct drm_encoder_funcs ast_enc_funcs = { 723 .destroy = ast_encoder_destroy, 724 }; 725 726 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode) 727 { 728 729 } 730 731 static void ast_encoder_mode_set(struct drm_encoder *encoder, 732 struct drm_display_mode *mode, 733 struct drm_display_mode *adjusted_mode) 734 { 735 } 736 737 static void ast_encoder_prepare(struct drm_encoder *encoder) 738 { 739 740 } 741 742 static void ast_encoder_commit(struct drm_encoder *encoder) 743 { 744 745 } 746 747 748 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = { 749 .dpms = ast_encoder_dpms, 750 .prepare = ast_encoder_prepare, 751 .commit = ast_encoder_commit, 752 .mode_set = ast_encoder_mode_set, 753 }; 754 755 static int ast_encoder_init(struct drm_device *dev) 756 { 757 struct ast_encoder *ast_encoder; 758 759 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL); 760 if (!ast_encoder) 761 return -ENOMEM; 762 763 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs, 764 DRM_MODE_ENCODER_DAC, NULL); 765 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); 766 767 ast_encoder->base.possible_crtcs = 1; 768 return 0; 769 } 770 771 static int ast_get_modes(struct drm_connector *connector) 772 { 773 struct ast_connector *ast_connector = to_ast_connector(connector); 774 struct ast_private *ast = connector->dev->dev_private; 775 struct edid *edid; 776 int ret; 777 bool flags = false; 778 if (ast->tx_chip_type == AST_TX_DP501) { 779 ast->dp501_maxclk = 0xff; 780 edid = kmalloc(128, GFP_KERNEL); 781 if (!edid) 782 return -ENOMEM; 783 784 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 785 if (flags) 786 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 787 else 788 kfree(edid); 789 } 790 if (!flags) 791 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 792 if (edid) { 793 drm_mode_connector_update_edid_property(&ast_connector->base, edid); 794 ret = drm_add_edid_modes(connector, edid); 795 kfree(edid); 796 return ret; 797 } else 798 drm_mode_connector_update_edid_property(&ast_connector->base, NULL); 799 return 0; 800 } 801 802 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, 803 struct drm_display_mode *mode) 804 { 805 struct ast_private *ast = connector->dev->dev_private; 806 int flags = MODE_NOMODE; 807 uint32_t jtemp; 808 809 if (ast->support_wide_screen) { 810 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 811 return MODE_OK; 812 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 813 return MODE_OK; 814 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 815 return MODE_OK; 816 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 817 return MODE_OK; 818 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 819 return MODE_OK; 820 821 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 822 (ast->chip == AST2300) || (ast->chip == AST2400) || 823 (ast->chip == AST2500) || (ast->chip == AST1180)) { 824 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 825 return MODE_OK; 826 827 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 828 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 829 if (jtemp & 0x01) 830 return MODE_NOMODE; 831 else 832 return MODE_OK; 833 } 834 } 835 } 836 switch (mode->hdisplay) { 837 case 640: 838 if (mode->vdisplay == 480) flags = MODE_OK; 839 break; 840 case 800: 841 if (mode->vdisplay == 600) flags = MODE_OK; 842 break; 843 case 1024: 844 if (mode->vdisplay == 768) flags = MODE_OK; 845 break; 846 case 1280: 847 if (mode->vdisplay == 1024) flags = MODE_OK; 848 break; 849 case 1600: 850 if (mode->vdisplay == 1200) flags = MODE_OK; 851 break; 852 default: 853 return flags; 854 } 855 856 return flags; 857 } 858 859 static void ast_connector_destroy(struct drm_connector *connector) 860 { 861 struct ast_connector *ast_connector = to_ast_connector(connector); 862 ast_i2c_destroy(ast_connector->i2c); 863 drm_connector_unregister(connector); 864 drm_connector_cleanup(connector); 865 kfree(connector); 866 } 867 868 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 869 .mode_valid = ast_mode_valid, 870 .get_modes = ast_get_modes, 871 .best_encoder = ast_best_single_encoder, 872 }; 873 874 static const struct drm_connector_funcs ast_connector_funcs = { 875 .dpms = drm_helper_connector_dpms, 876 .fill_modes = drm_helper_probe_single_connector_modes, 877 .destroy = ast_connector_destroy, 878 }; 879 880 static int ast_connector_init(struct drm_device *dev) 881 { 882 struct ast_connector *ast_connector; 883 struct drm_connector *connector; 884 struct drm_encoder *encoder; 885 886 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 887 if (!ast_connector) 888 return -ENOMEM; 889 890 connector = &ast_connector->base; 891 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA); 892 893 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 894 895 connector->interlace_allowed = 0; 896 connector->doublescan_allowed = 0; 897 898 drm_connector_register(connector); 899 900 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 901 902 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 903 drm_mode_connector_attach_encoder(connector, encoder); 904 905 ast_connector->i2c = ast_i2c_create(dev); 906 if (!ast_connector->i2c) 907 DRM_ERROR("failed to add ddc bus for connector\n"); 908 909 return 0; 910 } 911 912 /* allocate cursor cache and pin at start of VRAM */ 913 static int ast_cursor_init(struct drm_device *dev) 914 { 915 struct ast_private *ast = dev->dev_private; 916 int size; 917 int ret; 918 struct drm_gem_object *obj; 919 struct ast_bo *bo; 920 uint64_t gpu_addr; 921 922 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM; 923 924 ret = ast_gem_create(dev, size, true, &obj); 925 if (ret) 926 return ret; 927 bo = gem_to_ast_bo(obj); 928 ret = ast_bo_reserve(bo, false); 929 if (unlikely(ret != 0)) 930 goto fail; 931 932 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 933 ast_bo_unreserve(bo); 934 if (ret) 935 goto fail; 936 937 /* kmap the object */ 938 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap); 939 if (ret) 940 goto fail; 941 942 ast->cursor_cache = obj; 943 ast->cursor_cache_gpu_addr = gpu_addr; 944 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr); 945 return 0; 946 fail: 947 return ret; 948 } 949 950 static void ast_cursor_fini(struct drm_device *dev) 951 { 952 struct ast_private *ast = dev->dev_private; 953 ttm_bo_kunmap(&ast->cache_kmap); 954 drm_gem_object_put_unlocked(ast->cursor_cache); 955 } 956 957 int ast_mode_init(struct drm_device *dev) 958 { 959 ast_cursor_init(dev); 960 ast_crtc_init(dev); 961 ast_encoder_init(dev); 962 ast_connector_init(dev); 963 return 0; 964 } 965 966 void ast_mode_fini(struct drm_device *dev) 967 { 968 ast_cursor_fini(dev); 969 } 970 971 static int get_clock(void *i2c_priv) 972 { 973 struct ast_i2c_chan *i2c = i2c_priv; 974 struct ast_private *ast = i2c->dev->dev_private; 975 uint32_t val; 976 977 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4; 978 return val & 1 ? 1 : 0; 979 } 980 981 static int get_data(void *i2c_priv) 982 { 983 struct ast_i2c_chan *i2c = i2c_priv; 984 struct ast_private *ast = i2c->dev->dev_private; 985 uint32_t val; 986 987 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5; 988 return val & 1 ? 1 : 0; 989 } 990 991 static void set_clock(void *i2c_priv, int clock) 992 { 993 struct ast_i2c_chan *i2c = i2c_priv; 994 struct ast_private *ast = i2c->dev->dev_private; 995 int i; 996 u8 ujcrb7, jtemp; 997 998 for (i = 0; i < 0x10000; i++) { 999 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1000 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7); 1001 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1002 if (ujcrb7 == jtemp) 1003 break; 1004 } 1005 } 1006 1007 static void set_data(void *i2c_priv, int data) 1008 { 1009 struct ast_i2c_chan *i2c = i2c_priv; 1010 struct ast_private *ast = i2c->dev->dev_private; 1011 int i; 1012 u8 ujcrb7, jtemp; 1013 1014 for (i = 0; i < 0x10000; i++) { 1015 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1016 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7); 1017 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1018 if (ujcrb7 == jtemp) 1019 break; 1020 } 1021 } 1022 1023 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1024 { 1025 struct ast_i2c_chan *i2c; 1026 int ret; 1027 1028 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1029 if (!i2c) 1030 return NULL; 1031 1032 i2c->adapter.owner = THIS_MODULE; 1033 i2c->adapter.class = I2C_CLASS_DDC; 1034 i2c->adapter.dev.parent = &dev->pdev->dev; 1035 i2c->dev = dev; 1036 i2c_set_adapdata(&i2c->adapter, i2c); 1037 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1038 "AST i2c bit bus"); 1039 i2c->adapter.algo_data = &i2c->bit; 1040 1041 i2c->bit.udelay = 20; 1042 i2c->bit.timeout = 2; 1043 i2c->bit.data = i2c; 1044 i2c->bit.setsda = set_data; 1045 i2c->bit.setscl = set_clock; 1046 i2c->bit.getsda = get_data; 1047 i2c->bit.getscl = get_clock; 1048 ret = i2c_bit_add_bus(&i2c->adapter); 1049 if (ret) { 1050 DRM_ERROR("Failed to register bit i2c\n"); 1051 goto out_free; 1052 } 1053 1054 return i2c; 1055 out_free: 1056 kfree(i2c); 1057 return NULL; 1058 } 1059 1060 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1061 { 1062 if (!i2c) 1063 return; 1064 i2c_del_adapter(&i2c->adapter); 1065 kfree(i2c); 1066 } 1067 1068 static void ast_show_cursor(struct drm_crtc *crtc) 1069 { 1070 struct ast_private *ast = crtc->dev->dev_private; 1071 u8 jreg; 1072 1073 jreg = 0x2; 1074 /* enable ARGB cursor */ 1075 jreg |= 1; 1076 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1077 } 1078 1079 static void ast_hide_cursor(struct drm_crtc *crtc) 1080 { 1081 struct ast_private *ast = crtc->dev->dev_private; 1082 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 1083 } 1084 1085 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1086 { 1087 union { 1088 u32 ul; 1089 u8 b[4]; 1090 } srcdata32[2], data32; 1091 union { 1092 u16 us; 1093 u8 b[2]; 1094 } data16; 1095 u32 csum = 0; 1096 s32 alpha_dst_delta, last_alpha_dst_delta; 1097 u8 *srcxor, *dstxor; 1098 int i, j; 1099 u32 per_pixel_copy, two_pixel_copy; 1100 1101 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1102 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1103 1104 srcxor = src; 1105 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1106 per_pixel_copy = width & 1; 1107 two_pixel_copy = width >> 1; 1108 1109 for (j = 0; j < height; j++) { 1110 for (i = 0; i < two_pixel_copy; i++) { 1111 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1112 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1113 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1114 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1115 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1116 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1117 1118 writel(data32.ul, dstxor); 1119 csum += data32.ul; 1120 1121 dstxor += 4; 1122 srcxor += 8; 1123 1124 } 1125 1126 for (i = 0; i < per_pixel_copy; i++) { 1127 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1128 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1129 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1130 writew(data16.us, dstxor); 1131 csum += (u32)data16.us; 1132 1133 dstxor += 2; 1134 srcxor += 4; 1135 } 1136 dstxor += last_alpha_dst_delta; 1137 } 1138 return csum; 1139 } 1140 1141 static int ast_cursor_set(struct drm_crtc *crtc, 1142 struct drm_file *file_priv, 1143 uint32_t handle, 1144 uint32_t width, 1145 uint32_t height) 1146 { 1147 struct ast_private *ast = crtc->dev->dev_private; 1148 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1149 struct drm_gem_object *obj; 1150 struct ast_bo *bo; 1151 uint64_t gpu_addr; 1152 u32 csum; 1153 int ret; 1154 struct ttm_bo_kmap_obj uobj_map; 1155 u8 *src, *dst; 1156 bool src_isiomem, dst_isiomem; 1157 if (!handle) { 1158 ast_hide_cursor(crtc); 1159 return 0; 1160 } 1161 1162 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT) 1163 return -EINVAL; 1164 1165 obj = drm_gem_object_lookup(file_priv, handle); 1166 if (!obj) { 1167 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle); 1168 return -ENOENT; 1169 } 1170 bo = gem_to_ast_bo(obj); 1171 1172 ret = ast_bo_reserve(bo, false); 1173 if (ret) 1174 goto fail; 1175 1176 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map); 1177 1178 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem); 1179 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem); 1180 1181 if (src_isiomem == true) 1182 DRM_ERROR("src cursor bo should be in main memory\n"); 1183 if (dst_isiomem == false) 1184 DRM_ERROR("dst bo should be in VRAM\n"); 1185 1186 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1187 1188 /* do data transfer to cursor cache */ 1189 csum = copy_cursor_image(src, dst, width, height); 1190 1191 /* write checksum + signature */ 1192 ttm_bo_kunmap(&uobj_map); 1193 ast_bo_unreserve(bo); 1194 { 1195 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1196 writel(csum, dst); 1197 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1198 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1199 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1200 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1201 1202 /* set pattern offset */ 1203 gpu_addr = ast->cursor_cache_gpu_addr; 1204 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1205 gpu_addr >>= 3; 1206 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff); 1207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff); 1208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff); 1209 } 1210 ast_crtc->cursor_width = width; 1211 ast_crtc->cursor_height = height; 1212 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width; 1213 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height; 1214 1215 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM; 1216 1217 ast_show_cursor(crtc); 1218 1219 drm_gem_object_put_unlocked(obj); 1220 return 0; 1221 fail: 1222 drm_gem_object_put_unlocked(obj); 1223 return ret; 1224 } 1225 1226 static int ast_cursor_move(struct drm_crtc *crtc, 1227 int x, int y) 1228 { 1229 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1230 struct ast_private *ast = crtc->dev->dev_private; 1231 int x_offset, y_offset; 1232 u8 *sig; 1233 1234 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1235 writel(x, sig + AST_HWC_SIGNATURE_X); 1236 writel(y, sig + AST_HWC_SIGNATURE_Y); 1237 1238 x_offset = ast_crtc->offset_x; 1239 y_offset = ast_crtc->offset_y; 1240 if (x < 0) { 1241 x_offset = (-x) + ast_crtc->offset_x; 1242 x = 0; 1243 } 1244 1245 if (y < 0) { 1246 y_offset = (-y) + ast_crtc->offset_y; 1247 y = 0; 1248 } 1249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1250 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1255 1256 /* dummy write to fire HWC */ 1257 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00); 1258 1259 return 0; 1260 } 1261