1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 31 #include <linux/export.h> 32 #include <linux/pci.h> 33 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_atomic_state_helper.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fourcc.h> 40 #include <drm/drm_gem_atomic_helper.h> 41 #include <drm/drm_gem_framebuffer_helper.h> 42 #include <drm/drm_gem_vram_helper.h> 43 #include <drm/drm_plane_helper.h> 44 #include <drm/drm_probe_helper.h> 45 #include <drm/drm_simple_kms_helper.h> 46 47 #include "ast_drv.h" 48 #include "ast_tables.h" 49 50 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 51 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 52 53 static inline void ast_load_palette_index(struct ast_private *ast, 54 u8 index, u8 red, u8 green, 55 u8 blue) 56 { 57 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 58 ast_io_read8(ast, AST_IO_SEQ_PORT); 59 ast_io_write8(ast, AST_IO_DAC_DATA, red); 60 ast_io_read8(ast, AST_IO_SEQ_PORT); 61 ast_io_write8(ast, AST_IO_DAC_DATA, green); 62 ast_io_read8(ast, AST_IO_SEQ_PORT); 63 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 64 ast_io_read8(ast, AST_IO_SEQ_PORT); 65 } 66 67 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc) 68 { 69 u16 *r, *g, *b; 70 int i; 71 72 if (!crtc->enabled) 73 return; 74 75 r = crtc->gamma_store; 76 g = r + crtc->gamma_size; 77 b = g + crtc->gamma_size; 78 79 for (i = 0; i < 256; i++) 80 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8); 81 } 82 83 static bool ast_get_vbios_mode_info(const struct drm_format_info *format, 84 const struct drm_display_mode *mode, 85 struct drm_display_mode *adjusted_mode, 86 struct ast_vbios_mode_info *vbios_mode) 87 { 88 u32 refresh_rate_index = 0, refresh_rate; 89 const struct ast_vbios_enhtable *best = NULL; 90 u32 hborder, vborder; 91 bool check_sync; 92 93 switch (format->cpp[0] * 8) { 94 case 8: 95 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 96 break; 97 case 16: 98 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 99 break; 100 case 24: 101 case 32: 102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 103 break; 104 default: 105 return false; 106 } 107 108 switch (mode->crtc_hdisplay) { 109 case 640: 110 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 111 break; 112 case 800: 113 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 114 break; 115 case 1024: 116 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 117 break; 118 case 1280: 119 if (mode->crtc_vdisplay == 800) 120 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 121 else 122 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 123 break; 124 case 1360: 125 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 126 break; 127 case 1440: 128 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 129 break; 130 case 1600: 131 if (mode->crtc_vdisplay == 900) 132 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 133 else 134 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 135 break; 136 case 1680: 137 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 138 break; 139 case 1920: 140 if (mode->crtc_vdisplay == 1080) 141 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 142 else 143 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 144 break; 145 default: 146 return false; 147 } 148 149 refresh_rate = drm_mode_vrefresh(mode); 150 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 151 152 while (1) { 153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 154 155 while (loop->refresh_rate != 0xff) { 156 if ((check_sync) && 157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 158 (loop->flags & PVSync)) || 159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 160 (loop->flags & NVSync)) || 161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 162 (loop->flags & PHSync)) || 163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 164 (loop->flags & NHSync)))) { 165 loop++; 166 continue; 167 } 168 if (loop->refresh_rate <= refresh_rate 169 && (!best || loop->refresh_rate > best->refresh_rate)) 170 best = loop; 171 loop++; 172 } 173 if (best || !check_sync) 174 break; 175 check_sync = 0; 176 } 177 178 if (best) 179 vbios_mode->enh_table = best; 180 181 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 182 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 183 184 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 185 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 186 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 187 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 188 vbios_mode->enh_table->hfp; 189 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 190 vbios_mode->enh_table->hfp + 191 vbios_mode->enh_table->hsync); 192 193 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 194 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 195 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 196 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 197 vbios_mode->enh_table->vfp; 198 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 199 vbios_mode->enh_table->vfp + 200 vbios_mode->enh_table->vsync); 201 202 return true; 203 } 204 205 static void ast_set_vbios_color_reg(struct ast_private *ast, 206 const struct drm_format_info *format, 207 const struct ast_vbios_mode_info *vbios_mode) 208 { 209 u32 color_index; 210 211 switch (format->cpp[0]) { 212 case 1: 213 color_index = VGAModeIndex - 1; 214 break; 215 case 2: 216 color_index = HiCModeIndex; 217 break; 218 case 3: 219 case 4: 220 color_index = TrueCModeIndex; 221 break; 222 default: 223 return; 224 } 225 226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4)); 227 228 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 229 230 if (vbios_mode->enh_table->flags & NewModeInfo) { 231 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 232 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8); 233 } 234 } 235 236 static void ast_set_vbios_mode_reg(struct ast_private *ast, 237 const struct drm_display_mode *adjusted_mode, 238 const struct ast_vbios_mode_info *vbios_mode) 239 { 240 u32 refresh_rate_index, mode_id; 241 242 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 243 mode_id = vbios_mode->enh_table->mode_id; 244 245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 247 248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 249 250 if (vbios_mode->enh_table->flags & NewModeInfo) { 251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 257 } 258 } 259 260 static void ast_set_std_reg(struct ast_private *ast, 261 struct drm_display_mode *mode, 262 struct ast_vbios_mode_info *vbios_mode) 263 { 264 const struct ast_vbios_stdtable *stdtable; 265 u32 i; 266 u8 jreg; 267 268 stdtable = vbios_mode->std_table; 269 270 jreg = stdtable->misc; 271 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 272 273 /* Set SEQ; except Screen Disable field */ 274 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 275 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]); 276 for (i = 1; i < 4; i++) { 277 jreg = stdtable->seq[i]; 278 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 279 } 280 281 /* Set CRTC; except base address and offset */ 282 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 283 for (i = 0; i < 12; i++) 284 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 285 for (i = 14; i < 19; i++) 286 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 287 for (i = 20; i < 25; i++) 288 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 289 290 /* set AR */ 291 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 292 for (i = 0; i < 20; i++) { 293 jreg = stdtable->ar[i]; 294 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 295 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 296 } 297 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 298 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 299 300 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 301 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 302 303 /* Set GR */ 304 for (i = 0; i < 9; i++) 305 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 306 } 307 308 static void ast_set_crtc_reg(struct ast_private *ast, 309 struct drm_display_mode *mode, 310 struct ast_vbios_mode_info *vbios_mode) 311 { 312 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 313 u16 temp, precache = 0; 314 315 if ((ast->chip == AST2500) && 316 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 317 precache = 40; 318 319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 320 321 temp = (mode->crtc_htotal >> 3) - 5; 322 if (temp & 0x100) 323 jregAC |= 0x01; /* HT D[8] */ 324 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 325 326 temp = (mode->crtc_hdisplay >> 3) - 1; 327 if (temp & 0x100) 328 jregAC |= 0x04; /* HDE D[8] */ 329 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 330 331 temp = (mode->crtc_hblank_start >> 3) - 1; 332 if (temp & 0x100) 333 jregAC |= 0x10; /* HBS D[8] */ 334 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 335 336 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 337 if (temp & 0x20) 338 jreg05 |= 0x80; /* HBE D[5] */ 339 if (temp & 0x40) 340 jregAD |= 0x01; /* HBE D[5] */ 341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 342 343 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 344 if (temp & 0x100) 345 jregAC |= 0x40; /* HRS D[5] */ 346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 347 348 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 349 if (temp & 0x20) 350 jregAD |= 0x04; /* HRE D[5] */ 351 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 352 353 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 355 356 /* vert timings */ 357 temp = (mode->crtc_vtotal) - 2; 358 if (temp & 0x100) 359 jreg07 |= 0x01; 360 if (temp & 0x200) 361 jreg07 |= 0x20; 362 if (temp & 0x400) 363 jregAE |= 0x01; 364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 365 366 temp = (mode->crtc_vsync_start) - 1; 367 if (temp & 0x100) 368 jreg07 |= 0x04; 369 if (temp & 0x200) 370 jreg07 |= 0x80; 371 if (temp & 0x400) 372 jregAE |= 0x08; 373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 374 375 temp = (mode->crtc_vsync_end - 1) & 0x3f; 376 if (temp & 0x10) 377 jregAE |= 0x20; 378 if (temp & 0x20) 379 jregAE |= 0x40; 380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 381 382 temp = mode->crtc_vdisplay - 1; 383 if (temp & 0x100) 384 jreg07 |= 0x02; 385 if (temp & 0x200) 386 jreg07 |= 0x40; 387 if (temp & 0x400) 388 jregAE |= 0x02; 389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 390 391 temp = mode->crtc_vblank_start - 1; 392 if (temp & 0x100) 393 jreg07 |= 0x08; 394 if (temp & 0x200) 395 jreg09 |= 0x20; 396 if (temp & 0x400) 397 jregAE |= 0x04; 398 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 399 400 temp = mode->crtc_vblank_end - 1; 401 if (temp & 0x100) 402 jregAE |= 0x10; 403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 404 405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 408 409 if (precache) 410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 411 else 412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 413 414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 415 } 416 417 static void ast_set_offset_reg(struct ast_private *ast, 418 struct drm_framebuffer *fb) 419 { 420 u16 offset; 421 422 offset = fb->pitches[0] >> 3; 423 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 424 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 425 } 426 427 static void ast_set_dclk_reg(struct ast_private *ast, 428 struct drm_display_mode *mode, 429 struct ast_vbios_mode_info *vbios_mode) 430 { 431 const struct ast_vbios_dclk_info *clk_info; 432 433 if (ast->chip == AST2500) 434 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 435 else 436 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 437 438 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 441 (clk_info->param3 & 0xc0) | 442 ((clk_info->param3 & 0x3) << 4)); 443 } 444 445 static void ast_set_color_reg(struct ast_private *ast, 446 const struct drm_format_info *format) 447 { 448 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 449 450 switch (format->cpp[0] * 8) { 451 case 8: 452 jregA0 = 0x70; 453 jregA3 = 0x01; 454 jregA8 = 0x00; 455 break; 456 case 15: 457 case 16: 458 jregA0 = 0x70; 459 jregA3 = 0x04; 460 jregA8 = 0x02; 461 break; 462 case 32: 463 jregA0 = 0x70; 464 jregA3 = 0x08; 465 jregA8 = 0x02; 466 break; 467 } 468 469 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 470 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 471 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 472 } 473 474 static void ast_set_crtthd_reg(struct ast_private *ast) 475 { 476 /* Set Threshold */ 477 if (ast->chip == AST2300 || ast->chip == AST2400 || 478 ast->chip == AST2500) { 479 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 480 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 481 } else if (ast->chip == AST2100 || 482 ast->chip == AST1100 || 483 ast->chip == AST2200 || 484 ast->chip == AST2150) { 485 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 487 } else { 488 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 489 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 490 } 491 } 492 493 static void ast_set_sync_reg(struct ast_private *ast, 494 struct drm_display_mode *mode, 495 struct ast_vbios_mode_info *vbios_mode) 496 { 497 u8 jreg; 498 499 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 500 jreg &= ~0xC0; 501 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 502 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 503 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 504 } 505 506 static void ast_set_start_address_crt1(struct ast_private *ast, 507 unsigned offset) 508 { 509 u32 addr; 510 511 addr = offset >> 2; 512 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 513 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 514 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 515 516 } 517 518 static void ast_wait_for_vretrace(struct ast_private *ast) 519 { 520 unsigned long timeout = jiffies + HZ; 521 u8 vgair1; 522 523 do { 524 vgair1 = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 525 } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout)); 526 } 527 528 /* 529 * Primary plane 530 */ 531 532 static const uint32_t ast_primary_plane_formats[] = { 533 DRM_FORMAT_XRGB8888, 534 DRM_FORMAT_RGB565, 535 DRM_FORMAT_C8, 536 }; 537 538 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, 539 struct drm_plane_state *state) 540 { 541 struct drm_crtc_state *crtc_state; 542 struct ast_crtc_state *ast_crtc_state; 543 int ret; 544 545 if (!state->crtc) 546 return 0; 547 548 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 549 550 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 551 DRM_PLANE_HELPER_NO_SCALING, 552 DRM_PLANE_HELPER_NO_SCALING, 553 false, true); 554 if (ret) 555 return ret; 556 557 if (!state->visible) 558 return 0; 559 560 ast_crtc_state = to_ast_crtc_state(crtc_state); 561 562 ast_crtc_state->format = state->fb->format; 563 564 return 0; 565 } 566 567 static void 568 ast_primary_plane_helper_atomic_update(struct drm_plane *plane, 569 struct drm_plane_state *old_state) 570 { 571 struct drm_device *dev = plane->dev; 572 struct ast_private *ast = to_ast_private(dev); 573 struct drm_plane_state *state = plane->state; 574 struct drm_gem_vram_object *gbo; 575 s64 gpu_addr; 576 struct drm_framebuffer *fb = state->fb; 577 struct drm_framebuffer *old_fb = old_state->fb; 578 579 if (!old_fb || (fb->format != old_fb->format)) { 580 struct drm_crtc_state *crtc_state = state->crtc->state; 581 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state); 582 struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info; 583 584 ast_set_color_reg(ast, fb->format); 585 ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info); 586 } 587 588 gbo = drm_gem_vram_of_gem(fb->obj[0]); 589 gpu_addr = drm_gem_vram_offset(gbo); 590 if (drm_WARN_ON_ONCE(dev, gpu_addr < 0)) 591 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */ 592 593 ast_set_offset_reg(ast, fb); 594 ast_set_start_address_crt1(ast, (u32)gpu_addr); 595 596 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00); 597 } 598 599 static void 600 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, 601 struct drm_plane_state *old_state) 602 { 603 struct ast_private *ast = to_ast_private(plane->dev); 604 605 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 606 } 607 608 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = { 609 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, 610 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, 611 .atomic_check = ast_primary_plane_helper_atomic_check, 612 .atomic_update = ast_primary_plane_helper_atomic_update, 613 .atomic_disable = ast_primary_plane_helper_atomic_disable, 614 }; 615 616 static const struct drm_plane_funcs ast_primary_plane_funcs = { 617 .update_plane = drm_atomic_helper_update_plane, 618 .disable_plane = drm_atomic_helper_disable_plane, 619 .destroy = drm_plane_cleanup, 620 .reset = drm_atomic_helper_plane_reset, 621 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 622 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 623 }; 624 625 static int ast_primary_plane_init(struct ast_private *ast) 626 { 627 struct drm_device *dev = &ast->base; 628 struct drm_plane *primary_plane = &ast->primary_plane; 629 int ret; 630 631 ret = drm_universal_plane_init(dev, primary_plane, 0x01, 632 &ast_primary_plane_funcs, 633 ast_primary_plane_formats, 634 ARRAY_SIZE(ast_primary_plane_formats), 635 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 636 if (ret) { 637 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret); 638 return ret; 639 } 640 drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs); 641 642 return 0; 643 } 644 645 /* 646 * Cursor plane 647 */ 648 649 static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height) 650 { 651 union { 652 u32 ul; 653 u8 b[4]; 654 } srcdata32[2], data32; 655 union { 656 u16 us; 657 u8 b[2]; 658 } data16; 659 u32 csum = 0; 660 s32 alpha_dst_delta, last_alpha_dst_delta; 661 u8 __iomem *dstxor; 662 const u8 *srcxor; 663 int i, j; 664 u32 per_pixel_copy, two_pixel_copy; 665 666 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 667 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 668 669 srcxor = src; 670 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 671 per_pixel_copy = width & 1; 672 two_pixel_copy = width >> 1; 673 674 for (j = 0; j < height; j++) { 675 for (i = 0; i < two_pixel_copy; i++) { 676 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 677 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 678 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 679 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 680 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 681 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 682 683 writel(data32.ul, dstxor); 684 csum += data32.ul; 685 686 dstxor += 4; 687 srcxor += 8; 688 689 } 690 691 for (i = 0; i < per_pixel_copy; i++) { 692 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 693 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 694 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 695 writew(data16.us, dstxor); 696 csum += (u32)data16.us; 697 698 dstxor += 2; 699 srcxor += 4; 700 } 701 dstxor += last_alpha_dst_delta; 702 } 703 704 /* write checksum + signature */ 705 dst += AST_HWC_SIZE; 706 writel(csum, dst); 707 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 708 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 709 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 710 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 711 } 712 713 static void ast_set_cursor_base(struct ast_private *ast, u64 address) 714 { 715 u8 addr0 = (address >> 3) & 0xff; 716 u8 addr1 = (address >> 11) & 0xff; 717 u8 addr2 = (address >> 19) & 0xff; 718 719 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); 720 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); 721 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); 722 } 723 724 static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y, 725 u8 x_offset, u8 y_offset) 726 { 727 u8 x0 = (x & 0x00ff); 728 u8 x1 = (x & 0x0f00) >> 8; 729 u8 y0 = (y & 0x00ff); 730 u8 y1 = (y & 0x0700) >> 8; 731 732 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 733 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 734 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0); 735 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1); 736 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0); 737 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1); 738 } 739 740 static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled) 741 { 742 static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP | 743 AST_IO_VGACRCB_HWC_ENABLED); 744 745 u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP; 746 747 if (enabled) 748 vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED; 749 750 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb); 751 } 752 753 static const uint32_t ast_cursor_plane_formats[] = { 754 DRM_FORMAT_ARGB8888, 755 }; 756 757 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, 758 struct drm_plane_state *state) 759 { 760 struct drm_framebuffer *fb = state->fb; 761 struct drm_crtc_state *crtc_state; 762 int ret; 763 764 if (!state->crtc) 765 return 0; 766 767 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 768 769 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 770 DRM_PLANE_HELPER_NO_SCALING, 771 DRM_PLANE_HELPER_NO_SCALING, 772 true, true); 773 if (ret) 774 return ret; 775 776 if (!state->visible) 777 return 0; 778 779 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) 780 return -EINVAL; 781 782 return 0; 783 } 784 785 static void 786 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, 787 struct drm_plane_state *old_state) 788 { 789 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane); 790 struct drm_plane_state *state = plane->state; 791 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 792 struct drm_framebuffer *fb = state->fb; 793 struct ast_private *ast = to_ast_private(plane->dev); 794 struct dma_buf_map dst_map = 795 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map; 796 u64 dst_off = 797 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off; 798 struct dma_buf_map src_map = shadow_plane_state->map[0]; 799 unsigned int offset_x, offset_y; 800 u16 x, y; 801 u8 x_offset, y_offset; 802 u8 __iomem *dst; 803 u8 __iomem *sig; 804 const u8 *src; 805 806 src = src_map.vaddr; /* TODO: Use mapping abstraction properly */ 807 dst = dst_map.vaddr_iomem; /* TODO: Use mapping abstraction properly */ 808 sig = dst + AST_HWC_SIZE; /* TODO: Use mapping abstraction properly */ 809 810 /* 811 * Do data transfer to HW cursor BO. If a new cursor image was installed, 812 * point the scanout engine to dst_gbo's offset and page-flip the HWC buffers. 813 */ 814 815 ast_update_cursor_image(dst, src, fb->width, fb->height); 816 817 if (state->fb != old_state->fb) { 818 ast_set_cursor_base(ast, dst_off); 819 820 ++ast_cursor_plane->next_hwc_index; 821 ast_cursor_plane->next_hwc_index %= ARRAY_SIZE(ast_cursor_plane->hwc); 822 } 823 824 /* 825 * Update location in HWC signature and registers. 826 */ 827 828 writel(state->crtc_x, sig + AST_HWC_SIGNATURE_X); 829 writel(state->crtc_y, sig + AST_HWC_SIGNATURE_Y); 830 831 offset_x = AST_MAX_HWC_WIDTH - fb->width; 832 offset_y = AST_MAX_HWC_HEIGHT - fb->height; 833 834 if (state->crtc_x < 0) { 835 x_offset = (-state->crtc_x) + offset_x; 836 x = 0; 837 } else { 838 x_offset = offset_x; 839 x = state->crtc_x; 840 } 841 if (state->crtc_y < 0) { 842 y_offset = (-state->crtc_y) + offset_y; 843 y = 0; 844 } else { 845 y_offset = offset_y; 846 y = state->crtc_y; 847 } 848 849 ast_set_cursor_location(ast, x, y, x_offset, y_offset); 850 851 /* Dummy write to enable HWC and make the HW pick-up the changes. */ 852 ast_set_cursor_enabled(ast, true); 853 } 854 855 static void 856 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, 857 struct drm_plane_state *old_state) 858 { 859 struct ast_private *ast = to_ast_private(plane->dev); 860 861 ast_set_cursor_enabled(ast, false); 862 } 863 864 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = { 865 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 866 .atomic_check = ast_cursor_plane_helper_atomic_check, 867 .atomic_update = ast_cursor_plane_helper_atomic_update, 868 .atomic_disable = ast_cursor_plane_helper_atomic_disable, 869 }; 870 871 static void ast_cursor_plane_destroy(struct drm_plane *plane) 872 { 873 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane); 874 size_t i; 875 struct drm_gem_vram_object *gbo; 876 struct dma_buf_map map; 877 878 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) { 879 gbo = ast_cursor_plane->hwc[i].gbo; 880 map = ast_cursor_plane->hwc[i].map; 881 drm_gem_vram_vunmap(gbo, &map); 882 drm_gem_vram_unpin(gbo); 883 drm_gem_vram_put(gbo); 884 } 885 886 drm_plane_cleanup(plane); 887 } 888 889 static const struct drm_plane_funcs ast_cursor_plane_funcs = { 890 .update_plane = drm_atomic_helper_update_plane, 891 .disable_plane = drm_atomic_helper_disable_plane, 892 .destroy = ast_cursor_plane_destroy, 893 DRM_GEM_SHADOW_PLANE_FUNCS, 894 }; 895 896 static int ast_cursor_plane_init(struct ast_private *ast) 897 { 898 struct drm_device *dev = &ast->base; 899 struct ast_cursor_plane *ast_cursor_plane = &ast->cursor_plane; 900 struct drm_plane *cursor_plane = &ast_cursor_plane->base; 901 size_t size, i; 902 struct drm_gem_vram_object *gbo; 903 struct dma_buf_map map; 904 int ret; 905 s64 off; 906 907 /* 908 * Allocate backing storage for cursors. The BOs are permanently 909 * pinned to the top end of the VRAM. 910 */ 911 912 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE); 913 914 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) { 915 gbo = drm_gem_vram_create(dev, size, 0); 916 if (IS_ERR(gbo)) { 917 ret = PTR_ERR(gbo); 918 goto err_hwc; 919 } 920 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM | 921 DRM_GEM_VRAM_PL_FLAG_TOPDOWN); 922 if (ret) 923 goto err_drm_gem_vram_put; 924 ret = drm_gem_vram_vmap(gbo, &map); 925 if (ret) 926 goto err_drm_gem_vram_unpin; 927 off = drm_gem_vram_offset(gbo); 928 if (off < 0) { 929 ret = off; 930 goto err_drm_gem_vram_vunmap; 931 } 932 ast_cursor_plane->hwc[i].gbo = gbo; 933 ast_cursor_plane->hwc[i].map = map; 934 ast_cursor_plane->hwc[i].off = off; 935 } 936 937 /* 938 * Create the cursor plane. The plane's destroy callback will release 939 * the backing storages' BO memory. 940 */ 941 942 ret = drm_universal_plane_init(dev, cursor_plane, 0x01, 943 &ast_cursor_plane_funcs, 944 ast_cursor_plane_formats, 945 ARRAY_SIZE(ast_cursor_plane_formats), 946 NULL, DRM_PLANE_TYPE_CURSOR, NULL); 947 if (ret) { 948 drm_err(dev, "drm_universal_plane failed(): %d\n", ret); 949 goto err_hwc; 950 } 951 drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs); 952 953 return 0; 954 955 err_hwc: 956 while (i) { 957 --i; 958 gbo = ast_cursor_plane->hwc[i].gbo; 959 map = ast_cursor_plane->hwc[i].map; 960 err_drm_gem_vram_vunmap: 961 drm_gem_vram_vunmap(gbo, &map); 962 err_drm_gem_vram_unpin: 963 drm_gem_vram_unpin(gbo); 964 err_drm_gem_vram_put: 965 drm_gem_vram_put(gbo); 966 } 967 return ret; 968 } 969 970 /* 971 * CRTC 972 */ 973 974 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 975 { 976 struct ast_private *ast = to_ast_private(crtc->dev); 977 978 /* TODO: Maybe control display signal generation with 979 * Sync Enable (bit CR17.7). 980 */ 981 switch (mode) { 982 case DRM_MODE_DPMS_ON: 983 case DRM_MODE_DPMS_STANDBY: 984 case DRM_MODE_DPMS_SUSPEND: 985 if (ast->tx_chip_type == AST_TX_DP501) 986 ast_set_dp501_video_output(crtc->dev, 1); 987 break; 988 case DRM_MODE_DPMS_OFF: 989 if (ast->tx_chip_type == AST_TX_DP501) 990 ast_set_dp501_video_output(crtc->dev, 0); 991 break; 992 } 993 } 994 995 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, 996 struct drm_atomic_state *state) 997 { 998 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 999 crtc); 1000 struct drm_device *dev = crtc->dev; 1001 struct ast_crtc_state *ast_state; 1002 const struct drm_format_info *format; 1003 bool succ; 1004 1005 if (!crtc_state->enable) 1006 return 0; /* no mode checks if CRTC is being disabled */ 1007 1008 ast_state = to_ast_crtc_state(crtc_state); 1009 1010 format = ast_state->format; 1011 if (drm_WARN_ON_ONCE(dev, !format)) 1012 return -EINVAL; /* BUG: We didn't set format in primary check(). */ 1013 1014 succ = ast_get_vbios_mode_info(format, &crtc_state->mode, 1015 &crtc_state->adjusted_mode, 1016 &ast_state->vbios_mode_info); 1017 if (!succ) 1018 return -EINVAL; 1019 1020 return 0; 1021 } 1022 1023 static void 1024 ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, 1025 struct drm_atomic_state *state) 1026 { 1027 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1028 crtc); 1029 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1030 crtc); 1031 struct ast_private *ast = to_ast_private(crtc->dev); 1032 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state); 1033 struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state); 1034 1035 /* 1036 * The gamma LUT has to be reloaded after changing the primary 1037 * plane's color format. 1038 */ 1039 if (old_ast_crtc_state->format != ast_crtc_state->format) 1040 ast_crtc_load_lut(ast, crtc); 1041 } 1042 1043 static void 1044 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, 1045 struct drm_atomic_state *state) 1046 { 1047 struct drm_device *dev = crtc->dev; 1048 struct ast_private *ast = to_ast_private(dev); 1049 struct drm_crtc_state *crtc_state = crtc->state; 1050 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state); 1051 struct ast_vbios_mode_info *vbios_mode_info = 1052 &ast_crtc_state->vbios_mode_info; 1053 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1054 1055 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info); 1056 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); 1057 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info); 1058 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info); 1059 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info); 1060 ast_set_crtthd_reg(ast); 1061 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info); 1062 1063 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1064 } 1065 1066 static void 1067 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, 1068 struct drm_atomic_state *state) 1069 { 1070 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1071 crtc); 1072 struct drm_device *dev = crtc->dev; 1073 struct ast_private *ast = to_ast_private(dev); 1074 1075 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1076 1077 /* 1078 * HW cursors require the underlying primary plane and CRTC to 1079 * display a valid mode and image. This is not the case during 1080 * full modeset operations. So we temporarily disable any active 1081 * plane, including the HW cursor. Each plane's atomic_update() 1082 * helper will re-enable it if necessary. 1083 * 1084 * We only do this during *full* modesets. It does not affect 1085 * simple pageflips on the planes. 1086 */ 1087 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); 1088 1089 /* 1090 * Ensure that no scanout takes place before reprogramming mode 1091 * and format registers. 1092 */ 1093 ast_wait_for_vretrace(ast); 1094 } 1095 1096 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 1097 .atomic_check = ast_crtc_helper_atomic_check, 1098 .atomic_flush = ast_crtc_helper_atomic_flush, 1099 .atomic_enable = ast_crtc_helper_atomic_enable, 1100 .atomic_disable = ast_crtc_helper_atomic_disable, 1101 }; 1102 1103 static void ast_crtc_reset(struct drm_crtc *crtc) 1104 { 1105 struct ast_crtc_state *ast_state = 1106 kzalloc(sizeof(*ast_state), GFP_KERNEL); 1107 1108 if (crtc->state) 1109 crtc->funcs->atomic_destroy_state(crtc, crtc->state); 1110 1111 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base); 1112 } 1113 1114 static struct drm_crtc_state * 1115 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1116 { 1117 struct ast_crtc_state *new_ast_state, *ast_state; 1118 struct drm_device *dev = crtc->dev; 1119 1120 if (drm_WARN_ON(dev, !crtc->state)) 1121 return NULL; 1122 1123 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL); 1124 if (!new_ast_state) 1125 return NULL; 1126 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base); 1127 1128 ast_state = to_ast_crtc_state(crtc->state); 1129 1130 new_ast_state->format = ast_state->format; 1131 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info, 1132 sizeof(new_ast_state->vbios_mode_info)); 1133 1134 return &new_ast_state->base; 1135 } 1136 1137 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1138 struct drm_crtc_state *state) 1139 { 1140 struct ast_crtc_state *ast_state = to_ast_crtc_state(state); 1141 1142 __drm_atomic_helper_crtc_destroy_state(&ast_state->base); 1143 kfree(ast_state); 1144 } 1145 1146 static const struct drm_crtc_funcs ast_crtc_funcs = { 1147 .reset = ast_crtc_reset, 1148 .destroy = drm_crtc_cleanup, 1149 .set_config = drm_atomic_helper_set_config, 1150 .page_flip = drm_atomic_helper_page_flip, 1151 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state, 1152 .atomic_destroy_state = ast_crtc_atomic_destroy_state, 1153 }; 1154 1155 static int ast_crtc_init(struct drm_device *dev) 1156 { 1157 struct ast_private *ast = to_ast_private(dev); 1158 struct drm_crtc *crtc = &ast->crtc; 1159 int ret; 1160 1161 ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane, 1162 &ast->cursor_plane.base, &ast_crtc_funcs, 1163 NULL); 1164 if (ret) 1165 return ret; 1166 1167 drm_mode_crtc_set_gamma_size(crtc, 256); 1168 drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs); 1169 1170 return 0; 1171 } 1172 1173 /* 1174 * Encoder 1175 */ 1176 1177 static int ast_encoder_init(struct drm_device *dev) 1178 { 1179 struct ast_private *ast = to_ast_private(dev); 1180 struct drm_encoder *encoder = &ast->encoder; 1181 int ret; 1182 1183 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC); 1184 if (ret) 1185 return ret; 1186 1187 encoder->possible_crtcs = 1; 1188 1189 return 0; 1190 } 1191 1192 /* 1193 * Connector 1194 */ 1195 1196 static int ast_get_modes(struct drm_connector *connector) 1197 { 1198 struct ast_connector *ast_connector = to_ast_connector(connector); 1199 struct ast_private *ast = to_ast_private(connector->dev); 1200 struct edid *edid; 1201 int ret; 1202 bool flags = false; 1203 if (ast->tx_chip_type == AST_TX_DP501) { 1204 ast->dp501_maxclk = 0xff; 1205 edid = kmalloc(128, GFP_KERNEL); 1206 if (!edid) 1207 return -ENOMEM; 1208 1209 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 1210 if (flags) 1211 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 1212 else 1213 kfree(edid); 1214 } 1215 if (!flags) 1216 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 1217 if (edid) { 1218 drm_connector_update_edid_property(&ast_connector->base, edid); 1219 ret = drm_add_edid_modes(connector, edid); 1220 kfree(edid); 1221 return ret; 1222 } else 1223 drm_connector_update_edid_property(&ast_connector->base, NULL); 1224 return 0; 1225 } 1226 1227 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, 1228 struct drm_display_mode *mode) 1229 { 1230 struct ast_private *ast = to_ast_private(connector->dev); 1231 int flags = MODE_NOMODE; 1232 uint32_t jtemp; 1233 1234 if (ast->support_wide_screen) { 1235 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 1236 return MODE_OK; 1237 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 1238 return MODE_OK; 1239 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 1240 return MODE_OK; 1241 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 1242 return MODE_OK; 1243 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 1244 return MODE_OK; 1245 1246 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 1247 (ast->chip == AST2300) || (ast->chip == AST2400) || 1248 (ast->chip == AST2500)) { 1249 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 1250 return MODE_OK; 1251 1252 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 1253 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 1254 if (jtemp & 0x01) 1255 return MODE_NOMODE; 1256 else 1257 return MODE_OK; 1258 } 1259 } 1260 } 1261 switch (mode->hdisplay) { 1262 case 640: 1263 if (mode->vdisplay == 480) flags = MODE_OK; 1264 break; 1265 case 800: 1266 if (mode->vdisplay == 600) flags = MODE_OK; 1267 break; 1268 case 1024: 1269 if (mode->vdisplay == 768) flags = MODE_OK; 1270 break; 1271 case 1280: 1272 if (mode->vdisplay == 1024) flags = MODE_OK; 1273 break; 1274 case 1600: 1275 if (mode->vdisplay == 1200) flags = MODE_OK; 1276 break; 1277 default: 1278 return flags; 1279 } 1280 1281 return flags; 1282 } 1283 1284 static void ast_connector_destroy(struct drm_connector *connector) 1285 { 1286 struct ast_connector *ast_connector = to_ast_connector(connector); 1287 ast_i2c_destroy(ast_connector->i2c); 1288 drm_connector_cleanup(connector); 1289 } 1290 1291 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 1292 .get_modes = ast_get_modes, 1293 .mode_valid = ast_mode_valid, 1294 }; 1295 1296 static const struct drm_connector_funcs ast_connector_funcs = { 1297 .reset = drm_atomic_helper_connector_reset, 1298 .fill_modes = drm_helper_probe_single_connector_modes, 1299 .destroy = ast_connector_destroy, 1300 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1301 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1302 }; 1303 1304 static int ast_connector_init(struct drm_device *dev) 1305 { 1306 struct ast_private *ast = to_ast_private(dev); 1307 struct ast_connector *ast_connector = &ast->connector; 1308 struct drm_connector *connector = &ast_connector->base; 1309 struct drm_encoder *encoder = &ast->encoder; 1310 1311 ast_connector->i2c = ast_i2c_create(dev); 1312 if (!ast_connector->i2c) 1313 drm_err(dev, "failed to add ddc bus for connector\n"); 1314 1315 drm_connector_init_with_ddc(dev, connector, 1316 &ast_connector_funcs, 1317 DRM_MODE_CONNECTOR_VGA, 1318 &ast_connector->i2c->adapter); 1319 1320 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 1321 1322 connector->interlace_allowed = 0; 1323 connector->doublescan_allowed = 0; 1324 1325 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1326 1327 drm_connector_attach_encoder(connector, encoder); 1328 1329 return 0; 1330 } 1331 1332 /* 1333 * Mode config 1334 */ 1335 1336 static const struct drm_mode_config_helper_funcs 1337 ast_mode_config_helper_funcs = { 1338 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 1339 }; 1340 1341 static const struct drm_mode_config_funcs ast_mode_config_funcs = { 1342 .fb_create = drm_gem_fb_create, 1343 .mode_valid = drm_vram_helper_mode_valid, 1344 .atomic_check = drm_atomic_helper_check, 1345 .atomic_commit = drm_atomic_helper_commit, 1346 }; 1347 1348 int ast_mode_config_init(struct ast_private *ast) 1349 { 1350 struct drm_device *dev = &ast->base; 1351 struct pci_dev *pdev = to_pci_dev(dev->dev); 1352 int ret; 1353 1354 ret = drmm_mode_config_init(dev); 1355 if (ret) 1356 return ret; 1357 1358 dev->mode_config.funcs = &ast_mode_config_funcs; 1359 dev->mode_config.min_width = 0; 1360 dev->mode_config.min_height = 0; 1361 dev->mode_config.preferred_depth = 24; 1362 dev->mode_config.prefer_shadow = 1; 1363 dev->mode_config.fb_base = pci_resource_start(pdev, 0); 1364 1365 if (ast->chip == AST2100 || 1366 ast->chip == AST2200 || 1367 ast->chip == AST2300 || 1368 ast->chip == AST2400 || 1369 ast->chip == AST2500) { 1370 dev->mode_config.max_width = 1920; 1371 dev->mode_config.max_height = 2048; 1372 } else { 1373 dev->mode_config.max_width = 1600; 1374 dev->mode_config.max_height = 1200; 1375 } 1376 1377 dev->mode_config.helper_private = &ast_mode_config_helper_funcs; 1378 1379 1380 ret = ast_primary_plane_init(ast); 1381 if (ret) 1382 return ret; 1383 1384 ret = ast_cursor_plane_init(ast); 1385 if (ret) 1386 return ret; 1387 1388 ast_crtc_init(dev); 1389 ast_encoder_init(dev); 1390 ast_connector_init(dev); 1391 1392 drm_mode_config_reset(dev); 1393 1394 return 0; 1395 } 1396 1397 static int get_clock(void *i2c_priv) 1398 { 1399 struct ast_i2c_chan *i2c = i2c_priv; 1400 struct ast_private *ast = to_ast_private(i2c->dev); 1401 uint32_t val, val2, count, pass; 1402 1403 count = 0; 1404 pass = 0; 1405 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1406 do { 1407 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1408 if (val == val2) { 1409 pass++; 1410 } else { 1411 pass = 0; 1412 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1413 } 1414 } while ((pass < 5) && (count++ < 0x10000)); 1415 1416 return val & 1 ? 1 : 0; 1417 } 1418 1419 static int get_data(void *i2c_priv) 1420 { 1421 struct ast_i2c_chan *i2c = i2c_priv; 1422 struct ast_private *ast = to_ast_private(i2c->dev); 1423 uint32_t val, val2, count, pass; 1424 1425 count = 0; 1426 pass = 0; 1427 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1428 do { 1429 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1430 if (val == val2) { 1431 pass++; 1432 } else { 1433 pass = 0; 1434 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1435 } 1436 } while ((pass < 5) && (count++ < 0x10000)); 1437 1438 return val & 1 ? 1 : 0; 1439 } 1440 1441 static void set_clock(void *i2c_priv, int clock) 1442 { 1443 struct ast_i2c_chan *i2c = i2c_priv; 1444 struct ast_private *ast = to_ast_private(i2c->dev); 1445 int i; 1446 u8 ujcrb7, jtemp; 1447 1448 for (i = 0; i < 0x10000; i++) { 1449 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1450 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); 1451 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1452 if (ujcrb7 == jtemp) 1453 break; 1454 } 1455 } 1456 1457 static void set_data(void *i2c_priv, int data) 1458 { 1459 struct ast_i2c_chan *i2c = i2c_priv; 1460 struct ast_private *ast = to_ast_private(i2c->dev); 1461 int i; 1462 u8 ujcrb7, jtemp; 1463 1464 for (i = 0; i < 0x10000; i++) { 1465 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1466 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); 1467 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1468 if (ujcrb7 == jtemp) 1469 break; 1470 } 1471 } 1472 1473 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1474 { 1475 struct ast_i2c_chan *i2c; 1476 int ret; 1477 1478 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1479 if (!i2c) 1480 return NULL; 1481 1482 i2c->adapter.owner = THIS_MODULE; 1483 i2c->adapter.class = I2C_CLASS_DDC; 1484 i2c->adapter.dev.parent = dev->dev; 1485 i2c->dev = dev; 1486 i2c_set_adapdata(&i2c->adapter, i2c); 1487 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1488 "AST i2c bit bus"); 1489 i2c->adapter.algo_data = &i2c->bit; 1490 1491 i2c->bit.udelay = 20; 1492 i2c->bit.timeout = 2; 1493 i2c->bit.data = i2c; 1494 i2c->bit.setsda = set_data; 1495 i2c->bit.setscl = set_clock; 1496 i2c->bit.getsda = get_data; 1497 i2c->bit.getscl = get_clock; 1498 ret = i2c_bit_add_bus(&i2c->adapter); 1499 if (ret) { 1500 drm_err(dev, "Failed to register bit i2c\n"); 1501 goto out_free; 1502 } 1503 1504 return i2c; 1505 out_free: 1506 kfree(i2c); 1507 return NULL; 1508 } 1509 1510 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1511 { 1512 if (!i2c) 1513 return; 1514 i2c_del_adapter(&i2c->adapter); 1515 kfree(i2c); 1516 } 1517