1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include "ast_drv.h" 36 37 #include "ast_tables.h" 38 39 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 40 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 41 static int ast_cursor_set(struct drm_crtc *crtc, 42 struct drm_file *file_priv, 43 uint32_t handle, 44 uint32_t width, 45 uint32_t height); 46 static int ast_cursor_move(struct drm_crtc *crtc, 47 int x, int y); 48 49 static inline void ast_load_palette_index(struct ast_private *ast, 50 u8 index, u8 red, u8 green, 51 u8 blue) 52 { 53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 54 ast_io_read8(ast, AST_IO_SEQ_PORT); 55 ast_io_write8(ast, AST_IO_DAC_DATA, red); 56 ast_io_read8(ast, AST_IO_SEQ_PORT); 57 ast_io_write8(ast, AST_IO_DAC_DATA, green); 58 ast_io_read8(ast, AST_IO_SEQ_PORT); 59 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 60 ast_io_read8(ast, AST_IO_SEQ_PORT); 61 } 62 63 static void ast_crtc_load_lut(struct drm_crtc *crtc) 64 { 65 struct ast_private *ast = crtc->dev->dev_private; 66 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 67 int i; 68 69 if (!crtc->enabled) 70 return; 71 72 for (i = 0; i < 256; i++) 73 ast_load_palette_index(ast, i, ast_crtc->lut_r[i], 74 ast_crtc->lut_g[i], ast_crtc->lut_b[i]); 75 } 76 77 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, 78 struct drm_display_mode *adjusted_mode, 79 struct ast_vbios_mode_info *vbios_mode) 80 { 81 struct ast_private *ast = crtc->dev->dev_private; 82 const struct drm_framebuffer *fb = crtc->primary->fb; 83 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; 84 u32 hborder, vborder; 85 bool check_sync; 86 struct ast_vbios_enhtable *best = NULL; 87 88 switch (fb->format->cpp[0] * 8) { 89 case 8: 90 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 91 color_index = VGAModeIndex - 1; 92 break; 93 case 16: 94 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 95 color_index = HiCModeIndex; 96 break; 97 case 24: 98 case 32: 99 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 100 color_index = TrueCModeIndex; 101 break; 102 default: 103 return false; 104 } 105 106 switch (crtc->mode.crtc_hdisplay) { 107 case 640: 108 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 109 break; 110 case 800: 111 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 112 break; 113 case 1024: 114 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 115 break; 116 case 1280: 117 if (crtc->mode.crtc_vdisplay == 800) 118 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 119 else 120 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 121 break; 122 case 1360: 123 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 124 break; 125 case 1440: 126 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 127 break; 128 case 1600: 129 if (crtc->mode.crtc_vdisplay == 900) 130 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 131 else 132 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 133 break; 134 case 1680: 135 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 136 break; 137 case 1920: 138 if (crtc->mode.crtc_vdisplay == 1080) 139 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 140 else 141 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 142 break; 143 default: 144 return false; 145 } 146 147 refresh_rate = drm_mode_vrefresh(mode); 148 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 149 do { 150 struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 151 152 while (loop->refresh_rate != 0xff) { 153 if ((check_sync) && 154 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 155 (loop->flags & PVSync)) || 156 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 157 (loop->flags & NVSync)) || 158 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 159 (loop->flags & PHSync)) || 160 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 161 (loop->flags & NHSync)))) { 162 loop++; 163 continue; 164 } 165 if (loop->refresh_rate <= refresh_rate 166 && (!best || loop->refresh_rate > best->refresh_rate)) 167 best = loop; 168 loop++; 169 } 170 if (best || !check_sync) 171 break; 172 check_sync = 0; 173 } while (1); 174 if (best) 175 vbios_mode->enh_table = best; 176 177 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 178 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 179 180 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 181 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 182 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 183 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 184 vbios_mode->enh_table->hfp; 185 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 186 vbios_mode->enh_table->hfp + 187 vbios_mode->enh_table->hsync); 188 189 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 190 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 191 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 192 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 193 vbios_mode->enh_table->vfp; 194 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 195 vbios_mode->enh_table->vfp + 196 vbios_mode->enh_table->vsync); 197 198 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 199 mode_id = vbios_mode->enh_table->mode_id; 200 201 if (ast->chip == AST1180) { 202 /* TODO 1180 */ 203 } else { 204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); 205 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 206 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 207 208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 209 if (vbios_mode->enh_table->flags & NewModeInfo) { 210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, 212 fb->format->cpp[0] * 8); 213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 216 217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 219 } 220 } 221 222 return true; 223 224 225 } 226 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 227 struct ast_vbios_mode_info *vbios_mode) 228 { 229 struct ast_private *ast = crtc->dev->dev_private; 230 struct ast_vbios_stdtable *stdtable; 231 u32 i; 232 u8 jreg; 233 234 stdtable = vbios_mode->std_table; 235 236 jreg = stdtable->misc; 237 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 238 239 /* Set SEQ */ 240 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 241 for (i = 0; i < 4; i++) { 242 jreg = stdtable->seq[i]; 243 if (!i) 244 jreg |= 0x20; 245 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 246 } 247 248 /* Set CRTC */ 249 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 250 for (i = 0; i < 25; i++) 251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 252 253 /* set AR */ 254 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 255 for (i = 0; i < 20; i++) { 256 jreg = stdtable->ar[i]; 257 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 258 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 259 } 260 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 262 263 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 265 266 /* Set GR */ 267 for (i = 0; i < 9; i++) 268 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 269 } 270 271 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 272 struct ast_vbios_mode_info *vbios_mode) 273 { 274 struct ast_private *ast = crtc->dev->dev_private; 275 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 276 u16 temp; 277 278 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 279 280 temp = (mode->crtc_htotal >> 3) - 5; 281 if (temp & 0x100) 282 jregAC |= 0x01; /* HT D[8] */ 283 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 284 285 temp = (mode->crtc_hdisplay >> 3) - 1; 286 if (temp & 0x100) 287 jregAC |= 0x04; /* HDE D[8] */ 288 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 289 290 temp = (mode->crtc_hblank_start >> 3) - 1; 291 if (temp & 0x100) 292 jregAC |= 0x10; /* HBS D[8] */ 293 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 294 295 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 296 if (temp & 0x20) 297 jreg05 |= 0x80; /* HBE D[5] */ 298 if (temp & 0x40) 299 jregAD |= 0x01; /* HBE D[5] */ 300 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 301 302 temp = (mode->crtc_hsync_start >> 3) - 1; 303 if (temp & 0x100) 304 jregAC |= 0x40; /* HRS D[5] */ 305 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 306 307 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f; 308 if (temp & 0x20) 309 jregAD |= 0x04; /* HRE D[5] */ 310 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 311 312 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 313 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 314 315 /* vert timings */ 316 temp = (mode->crtc_vtotal) - 2; 317 if (temp & 0x100) 318 jreg07 |= 0x01; 319 if (temp & 0x200) 320 jreg07 |= 0x20; 321 if (temp & 0x400) 322 jregAE |= 0x01; 323 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 324 325 temp = (mode->crtc_vsync_start) - 1; 326 if (temp & 0x100) 327 jreg07 |= 0x04; 328 if (temp & 0x200) 329 jreg07 |= 0x80; 330 if (temp & 0x400) 331 jregAE |= 0x08; 332 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 333 334 temp = (mode->crtc_vsync_end - 1) & 0x3f; 335 if (temp & 0x10) 336 jregAE |= 0x20; 337 if (temp & 0x20) 338 jregAE |= 0x40; 339 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 340 341 temp = mode->crtc_vdisplay - 1; 342 if (temp & 0x100) 343 jreg07 |= 0x02; 344 if (temp & 0x200) 345 jreg07 |= 0x40; 346 if (temp & 0x400) 347 jregAE |= 0x02; 348 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 349 350 temp = mode->crtc_vblank_start - 1; 351 if (temp & 0x100) 352 jreg07 |= 0x08; 353 if (temp & 0x200) 354 jreg09 |= 0x20; 355 if (temp & 0x400) 356 jregAE |= 0x04; 357 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 358 359 temp = mode->crtc_vblank_end - 1; 360 if (temp & 0x100) 361 jregAE |= 0x10; 362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 363 364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 365 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 366 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 367 368 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 369 } 370 371 static void ast_set_offset_reg(struct drm_crtc *crtc) 372 { 373 struct ast_private *ast = crtc->dev->dev_private; 374 const struct drm_framebuffer *fb = crtc->primary->fb; 375 376 u16 offset; 377 378 offset = fb->pitches[0] >> 3; 379 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 380 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 381 } 382 383 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, 384 struct ast_vbios_mode_info *vbios_mode) 385 { 386 struct ast_private *ast = dev->dev_private; 387 struct ast_vbios_dclk_info *clk_info; 388 389 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 390 391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 392 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 393 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 394 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4)); 395 } 396 397 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 398 struct ast_vbios_mode_info *vbios_mode) 399 { 400 struct ast_private *ast = crtc->dev->dev_private; 401 const struct drm_framebuffer *fb = crtc->primary->fb; 402 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 403 404 switch (fb->format->cpp[0] * 8) { 405 case 8: 406 jregA0 = 0x70; 407 jregA3 = 0x01; 408 jregA8 = 0x00; 409 break; 410 case 15: 411 case 16: 412 jregA0 = 0x70; 413 jregA3 = 0x04; 414 jregA8 = 0x02; 415 break; 416 case 32: 417 jregA0 = 0x70; 418 jregA3 = 0x08; 419 jregA8 = 0x02; 420 break; 421 } 422 423 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 424 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 425 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 426 427 /* Set Threshold */ 428 if (ast->chip == AST2300 || ast->chip == AST2400) { 429 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 431 } else if (ast->chip == AST2100 || 432 ast->chip == AST1100 || 433 ast->chip == AST2200 || 434 ast->chip == AST2150) { 435 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 436 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 437 } else { 438 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 439 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 440 } 441 } 442 443 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, 444 struct ast_vbios_mode_info *vbios_mode) 445 { 446 struct ast_private *ast = dev->dev_private; 447 u8 jreg; 448 449 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 450 jreg &= ~0xC0; 451 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 452 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 453 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 454 } 455 456 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 457 struct ast_vbios_mode_info *vbios_mode) 458 { 459 const struct drm_framebuffer *fb = crtc->primary->fb; 460 461 switch (fb->format->cpp[0] * 8) { 462 case 8: 463 break; 464 default: 465 return false; 466 } 467 return true; 468 } 469 470 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset) 471 { 472 struct ast_private *ast = crtc->dev->dev_private; 473 u32 addr; 474 475 addr = offset >> 2; 476 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 477 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 478 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 479 480 } 481 482 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 483 { 484 struct ast_private *ast = crtc->dev->dev_private; 485 486 if (ast->chip == AST1180) 487 return; 488 489 switch (mode) { 490 case DRM_MODE_DPMS_ON: 491 case DRM_MODE_DPMS_STANDBY: 492 case DRM_MODE_DPMS_SUSPEND: 493 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 494 if (ast->tx_chip_type == AST_TX_DP501) 495 ast_set_dp501_video_output(crtc->dev, 1); 496 ast_crtc_load_lut(crtc); 497 break; 498 case DRM_MODE_DPMS_OFF: 499 if (ast->tx_chip_type == AST_TX_DP501) 500 ast_set_dp501_video_output(crtc->dev, 0); 501 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 502 break; 503 } 504 } 505 506 /* ast is different - we will force move buffers out of VRAM */ 507 static int ast_crtc_do_set_base(struct drm_crtc *crtc, 508 struct drm_framebuffer *fb, 509 int x, int y, int atomic) 510 { 511 struct ast_private *ast = crtc->dev->dev_private; 512 struct drm_gem_object *obj; 513 struct ast_framebuffer *ast_fb; 514 struct ast_bo *bo; 515 int ret; 516 u64 gpu_addr; 517 518 /* push the previous fb to system ram */ 519 if (!atomic && fb) { 520 ast_fb = to_ast_framebuffer(fb); 521 obj = ast_fb->obj; 522 bo = gem_to_ast_bo(obj); 523 ret = ast_bo_reserve(bo, false); 524 if (ret) 525 return ret; 526 ast_bo_push_sysram(bo); 527 ast_bo_unreserve(bo); 528 } 529 530 ast_fb = to_ast_framebuffer(crtc->primary->fb); 531 obj = ast_fb->obj; 532 bo = gem_to_ast_bo(obj); 533 534 ret = ast_bo_reserve(bo, false); 535 if (ret) 536 return ret; 537 538 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 539 if (ret) { 540 ast_bo_unreserve(bo); 541 return ret; 542 } 543 544 if (&ast->fbdev->afb == ast_fb) { 545 /* if pushing console in kmap it */ 546 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 547 if (ret) 548 DRM_ERROR("failed to kmap fbcon\n"); 549 else 550 ast_fbdev_set_base(ast, gpu_addr); 551 } 552 ast_bo_unreserve(bo); 553 554 ast_set_start_address_crt1(crtc, (u32)gpu_addr); 555 556 return 0; 557 } 558 559 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 560 struct drm_framebuffer *old_fb) 561 { 562 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0); 563 } 564 565 static int ast_crtc_mode_set(struct drm_crtc *crtc, 566 struct drm_display_mode *mode, 567 struct drm_display_mode *adjusted_mode, 568 int x, int y, 569 struct drm_framebuffer *old_fb) 570 { 571 struct drm_device *dev = crtc->dev; 572 struct ast_private *ast = crtc->dev->dev_private; 573 struct ast_vbios_mode_info vbios_mode; 574 bool ret; 575 if (ast->chip == AST1180) { 576 DRM_ERROR("AST 1180 modesetting not supported\n"); 577 return -EINVAL; 578 } 579 580 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); 581 if (ret == false) 582 return -EINVAL; 583 ast_open_key(ast); 584 585 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); 586 587 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); 588 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); 589 ast_set_offset_reg(crtc); 590 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); 591 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); 592 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); 593 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode); 594 595 ast_crtc_mode_set_base(crtc, x, y, old_fb); 596 597 return 0; 598 } 599 600 static void ast_crtc_disable(struct drm_crtc *crtc) 601 { 602 603 } 604 605 static void ast_crtc_prepare(struct drm_crtc *crtc) 606 { 607 608 } 609 610 static void ast_crtc_commit(struct drm_crtc *crtc) 611 { 612 struct ast_private *ast = crtc->dev->dev_private; 613 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 614 } 615 616 617 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 618 .dpms = ast_crtc_dpms, 619 .mode_set = ast_crtc_mode_set, 620 .mode_set_base = ast_crtc_mode_set_base, 621 .disable = ast_crtc_disable, 622 .load_lut = ast_crtc_load_lut, 623 .prepare = ast_crtc_prepare, 624 .commit = ast_crtc_commit, 625 626 }; 627 628 static void ast_crtc_reset(struct drm_crtc *crtc) 629 { 630 631 } 632 633 static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 634 u16 *blue, uint32_t size) 635 { 636 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 637 int i; 638 639 /* userspace palettes are always correct as is */ 640 for (i = 0; i < size; i++) { 641 ast_crtc->lut_r[i] = red[i] >> 8; 642 ast_crtc->lut_g[i] = green[i] >> 8; 643 ast_crtc->lut_b[i] = blue[i] >> 8; 644 } 645 ast_crtc_load_lut(crtc); 646 647 return 0; 648 } 649 650 651 static void ast_crtc_destroy(struct drm_crtc *crtc) 652 { 653 drm_crtc_cleanup(crtc); 654 kfree(crtc); 655 } 656 657 static const struct drm_crtc_funcs ast_crtc_funcs = { 658 .cursor_set = ast_cursor_set, 659 .cursor_move = ast_cursor_move, 660 .reset = ast_crtc_reset, 661 .set_config = drm_crtc_helper_set_config, 662 .gamma_set = ast_crtc_gamma_set, 663 .destroy = ast_crtc_destroy, 664 }; 665 666 static int ast_crtc_init(struct drm_device *dev) 667 { 668 struct ast_crtc *crtc; 669 int i; 670 671 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 672 if (!crtc) 673 return -ENOMEM; 674 675 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); 676 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 677 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 678 679 for (i = 0; i < 256; i++) { 680 crtc->lut_r[i] = i; 681 crtc->lut_g[i] = i; 682 crtc->lut_b[i] = i; 683 } 684 return 0; 685 } 686 687 static void ast_encoder_destroy(struct drm_encoder *encoder) 688 { 689 drm_encoder_cleanup(encoder); 690 kfree(encoder); 691 } 692 693 694 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector) 695 { 696 int enc_id = connector->encoder_ids[0]; 697 /* pick the encoder ids */ 698 if (enc_id) 699 return drm_encoder_find(connector->dev, enc_id); 700 return NULL; 701 } 702 703 704 static const struct drm_encoder_funcs ast_enc_funcs = { 705 .destroy = ast_encoder_destroy, 706 }; 707 708 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode) 709 { 710 711 } 712 713 static void ast_encoder_mode_set(struct drm_encoder *encoder, 714 struct drm_display_mode *mode, 715 struct drm_display_mode *adjusted_mode) 716 { 717 } 718 719 static void ast_encoder_prepare(struct drm_encoder *encoder) 720 { 721 722 } 723 724 static void ast_encoder_commit(struct drm_encoder *encoder) 725 { 726 727 } 728 729 730 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = { 731 .dpms = ast_encoder_dpms, 732 .prepare = ast_encoder_prepare, 733 .commit = ast_encoder_commit, 734 .mode_set = ast_encoder_mode_set, 735 }; 736 737 static int ast_encoder_init(struct drm_device *dev) 738 { 739 struct ast_encoder *ast_encoder; 740 741 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL); 742 if (!ast_encoder) 743 return -ENOMEM; 744 745 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs, 746 DRM_MODE_ENCODER_DAC, NULL); 747 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); 748 749 ast_encoder->base.possible_crtcs = 1; 750 return 0; 751 } 752 753 static int ast_get_modes(struct drm_connector *connector) 754 { 755 struct ast_connector *ast_connector = to_ast_connector(connector); 756 struct ast_private *ast = connector->dev->dev_private; 757 struct edid *edid; 758 int ret; 759 bool flags = false; 760 if (ast->tx_chip_type == AST_TX_DP501) { 761 ast->dp501_maxclk = 0xff; 762 edid = kmalloc(128, GFP_KERNEL); 763 if (!edid) 764 return -ENOMEM; 765 766 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 767 if (flags) 768 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 769 else 770 kfree(edid); 771 } 772 if (!flags) 773 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 774 if (edid) { 775 drm_mode_connector_update_edid_property(&ast_connector->base, edid); 776 ret = drm_add_edid_modes(connector, edid); 777 kfree(edid); 778 return ret; 779 } else 780 drm_mode_connector_update_edid_property(&ast_connector->base, NULL); 781 return 0; 782 } 783 784 static int ast_mode_valid(struct drm_connector *connector, 785 struct drm_display_mode *mode) 786 { 787 struct ast_private *ast = connector->dev->dev_private; 788 int flags = MODE_NOMODE; 789 uint32_t jtemp; 790 791 if (ast->support_wide_screen) { 792 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 793 return MODE_OK; 794 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 795 return MODE_OK; 796 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 797 return MODE_OK; 798 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 799 return MODE_OK; 800 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 801 return MODE_OK; 802 803 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) { 804 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 805 return MODE_OK; 806 807 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 808 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 809 if (jtemp & 0x01) 810 return MODE_NOMODE; 811 else 812 return MODE_OK; 813 } 814 } 815 } 816 switch (mode->hdisplay) { 817 case 640: 818 if (mode->vdisplay == 480) flags = MODE_OK; 819 break; 820 case 800: 821 if (mode->vdisplay == 600) flags = MODE_OK; 822 break; 823 case 1024: 824 if (mode->vdisplay == 768) flags = MODE_OK; 825 break; 826 case 1280: 827 if (mode->vdisplay == 1024) flags = MODE_OK; 828 break; 829 case 1600: 830 if (mode->vdisplay == 1200) flags = MODE_OK; 831 break; 832 default: 833 return flags; 834 } 835 836 return flags; 837 } 838 839 static void ast_connector_destroy(struct drm_connector *connector) 840 { 841 struct ast_connector *ast_connector = to_ast_connector(connector); 842 ast_i2c_destroy(ast_connector->i2c); 843 drm_connector_unregister(connector); 844 drm_connector_cleanup(connector); 845 kfree(connector); 846 } 847 848 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 849 .mode_valid = ast_mode_valid, 850 .get_modes = ast_get_modes, 851 .best_encoder = ast_best_single_encoder, 852 }; 853 854 static const struct drm_connector_funcs ast_connector_funcs = { 855 .dpms = drm_helper_connector_dpms, 856 .fill_modes = drm_helper_probe_single_connector_modes, 857 .destroy = ast_connector_destroy, 858 }; 859 860 static int ast_connector_init(struct drm_device *dev) 861 { 862 struct ast_connector *ast_connector; 863 struct drm_connector *connector; 864 struct drm_encoder *encoder; 865 866 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 867 if (!ast_connector) 868 return -ENOMEM; 869 870 connector = &ast_connector->base; 871 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA); 872 873 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 874 875 connector->interlace_allowed = 0; 876 connector->doublescan_allowed = 0; 877 878 drm_connector_register(connector); 879 880 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 881 882 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 883 drm_mode_connector_attach_encoder(connector, encoder); 884 885 ast_connector->i2c = ast_i2c_create(dev); 886 if (!ast_connector->i2c) 887 DRM_ERROR("failed to add ddc bus for connector\n"); 888 889 return 0; 890 } 891 892 /* allocate cursor cache and pin at start of VRAM */ 893 static int ast_cursor_init(struct drm_device *dev) 894 { 895 struct ast_private *ast = dev->dev_private; 896 int size; 897 int ret; 898 struct drm_gem_object *obj; 899 struct ast_bo *bo; 900 uint64_t gpu_addr; 901 902 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM; 903 904 ret = ast_gem_create(dev, size, true, &obj); 905 if (ret) 906 return ret; 907 bo = gem_to_ast_bo(obj); 908 ret = ast_bo_reserve(bo, false); 909 if (unlikely(ret != 0)) 910 goto fail; 911 912 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 913 ast_bo_unreserve(bo); 914 if (ret) 915 goto fail; 916 917 /* kmap the object */ 918 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap); 919 if (ret) 920 goto fail; 921 922 ast->cursor_cache = obj; 923 ast->cursor_cache_gpu_addr = gpu_addr; 924 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr); 925 return 0; 926 fail: 927 return ret; 928 } 929 930 static void ast_cursor_fini(struct drm_device *dev) 931 { 932 struct ast_private *ast = dev->dev_private; 933 ttm_bo_kunmap(&ast->cache_kmap); 934 drm_gem_object_unreference_unlocked(ast->cursor_cache); 935 } 936 937 int ast_mode_init(struct drm_device *dev) 938 { 939 ast_cursor_init(dev); 940 ast_crtc_init(dev); 941 ast_encoder_init(dev); 942 ast_connector_init(dev); 943 return 0; 944 } 945 946 void ast_mode_fini(struct drm_device *dev) 947 { 948 ast_cursor_fini(dev); 949 } 950 951 static int get_clock(void *i2c_priv) 952 { 953 struct ast_i2c_chan *i2c = i2c_priv; 954 struct ast_private *ast = i2c->dev->dev_private; 955 uint32_t val; 956 957 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4; 958 return val & 1 ? 1 : 0; 959 } 960 961 static int get_data(void *i2c_priv) 962 { 963 struct ast_i2c_chan *i2c = i2c_priv; 964 struct ast_private *ast = i2c->dev->dev_private; 965 uint32_t val; 966 967 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5; 968 return val & 1 ? 1 : 0; 969 } 970 971 static void set_clock(void *i2c_priv, int clock) 972 { 973 struct ast_i2c_chan *i2c = i2c_priv; 974 struct ast_private *ast = i2c->dev->dev_private; 975 int i; 976 u8 ujcrb7, jtemp; 977 978 for (i = 0; i < 0x10000; i++) { 979 ujcrb7 = ((clock & 0x01) ? 0 : 1); 980 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7); 981 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 982 if (ujcrb7 == jtemp) 983 break; 984 } 985 } 986 987 static void set_data(void *i2c_priv, int data) 988 { 989 struct ast_i2c_chan *i2c = i2c_priv; 990 struct ast_private *ast = i2c->dev->dev_private; 991 int i; 992 u8 ujcrb7, jtemp; 993 994 for (i = 0; i < 0x10000; i++) { 995 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 996 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7); 997 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 998 if (ujcrb7 == jtemp) 999 break; 1000 } 1001 } 1002 1003 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1004 { 1005 struct ast_i2c_chan *i2c; 1006 int ret; 1007 1008 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1009 if (!i2c) 1010 return NULL; 1011 1012 i2c->adapter.owner = THIS_MODULE; 1013 i2c->adapter.class = I2C_CLASS_DDC; 1014 i2c->adapter.dev.parent = &dev->pdev->dev; 1015 i2c->dev = dev; 1016 i2c_set_adapdata(&i2c->adapter, i2c); 1017 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1018 "AST i2c bit bus"); 1019 i2c->adapter.algo_data = &i2c->bit; 1020 1021 i2c->bit.udelay = 20; 1022 i2c->bit.timeout = 2; 1023 i2c->bit.data = i2c; 1024 i2c->bit.setsda = set_data; 1025 i2c->bit.setscl = set_clock; 1026 i2c->bit.getsda = get_data; 1027 i2c->bit.getscl = get_clock; 1028 ret = i2c_bit_add_bus(&i2c->adapter); 1029 if (ret) { 1030 DRM_ERROR("Failed to register bit i2c\n"); 1031 goto out_free; 1032 } 1033 1034 return i2c; 1035 out_free: 1036 kfree(i2c); 1037 return NULL; 1038 } 1039 1040 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1041 { 1042 if (!i2c) 1043 return; 1044 i2c_del_adapter(&i2c->adapter); 1045 kfree(i2c); 1046 } 1047 1048 static void ast_show_cursor(struct drm_crtc *crtc) 1049 { 1050 struct ast_private *ast = crtc->dev->dev_private; 1051 u8 jreg; 1052 1053 jreg = 0x2; 1054 /* enable ARGB cursor */ 1055 jreg |= 1; 1056 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1057 } 1058 1059 static void ast_hide_cursor(struct drm_crtc *crtc) 1060 { 1061 struct ast_private *ast = crtc->dev->dev_private; 1062 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 1063 } 1064 1065 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1066 { 1067 union { 1068 u32 ul; 1069 u8 b[4]; 1070 } srcdata32[2], data32; 1071 union { 1072 u16 us; 1073 u8 b[2]; 1074 } data16; 1075 u32 csum = 0; 1076 s32 alpha_dst_delta, last_alpha_dst_delta; 1077 u8 *srcxor, *dstxor; 1078 int i, j; 1079 u32 per_pixel_copy, two_pixel_copy; 1080 1081 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1082 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1083 1084 srcxor = src; 1085 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1086 per_pixel_copy = width & 1; 1087 two_pixel_copy = width >> 1; 1088 1089 for (j = 0; j < height; j++) { 1090 for (i = 0; i < two_pixel_copy; i++) { 1091 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1092 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1093 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1094 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1095 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1096 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1097 1098 writel(data32.ul, dstxor); 1099 csum += data32.ul; 1100 1101 dstxor += 4; 1102 srcxor += 8; 1103 1104 } 1105 1106 for (i = 0; i < per_pixel_copy; i++) { 1107 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1108 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1109 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1110 writew(data16.us, dstxor); 1111 csum += (u32)data16.us; 1112 1113 dstxor += 2; 1114 srcxor += 4; 1115 } 1116 dstxor += last_alpha_dst_delta; 1117 } 1118 return csum; 1119 } 1120 1121 static int ast_cursor_set(struct drm_crtc *crtc, 1122 struct drm_file *file_priv, 1123 uint32_t handle, 1124 uint32_t width, 1125 uint32_t height) 1126 { 1127 struct ast_private *ast = crtc->dev->dev_private; 1128 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1129 struct drm_gem_object *obj; 1130 struct ast_bo *bo; 1131 uint64_t gpu_addr; 1132 u32 csum; 1133 int ret; 1134 struct ttm_bo_kmap_obj uobj_map; 1135 u8 *src, *dst; 1136 bool src_isiomem, dst_isiomem; 1137 if (!handle) { 1138 ast_hide_cursor(crtc); 1139 return 0; 1140 } 1141 1142 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT) 1143 return -EINVAL; 1144 1145 obj = drm_gem_object_lookup(file_priv, handle); 1146 if (!obj) { 1147 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle); 1148 return -ENOENT; 1149 } 1150 bo = gem_to_ast_bo(obj); 1151 1152 ret = ast_bo_reserve(bo, false); 1153 if (ret) 1154 goto fail; 1155 1156 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map); 1157 1158 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem); 1159 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem); 1160 1161 if (src_isiomem == true) 1162 DRM_ERROR("src cursor bo should be in main memory\n"); 1163 if (dst_isiomem == false) 1164 DRM_ERROR("dst bo should be in VRAM\n"); 1165 1166 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1167 1168 /* do data transfer to cursor cache */ 1169 csum = copy_cursor_image(src, dst, width, height); 1170 1171 /* write checksum + signature */ 1172 ttm_bo_kunmap(&uobj_map); 1173 ast_bo_unreserve(bo); 1174 { 1175 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1176 writel(csum, dst); 1177 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1178 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1179 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1180 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1181 1182 /* set pattern offset */ 1183 gpu_addr = ast->cursor_cache_gpu_addr; 1184 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1185 gpu_addr >>= 3; 1186 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff); 1187 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff); 1188 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff); 1189 } 1190 ast_crtc->cursor_width = width; 1191 ast_crtc->cursor_height = height; 1192 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width; 1193 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height; 1194 1195 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM; 1196 1197 ast_show_cursor(crtc); 1198 1199 drm_gem_object_unreference_unlocked(obj); 1200 return 0; 1201 fail: 1202 drm_gem_object_unreference_unlocked(obj); 1203 return ret; 1204 } 1205 1206 static int ast_cursor_move(struct drm_crtc *crtc, 1207 int x, int y) 1208 { 1209 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1210 struct ast_private *ast = crtc->dev->dev_private; 1211 int x_offset, y_offset; 1212 u8 *sig; 1213 1214 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1215 writel(x, sig + AST_HWC_SIGNATURE_X); 1216 writel(y, sig + AST_HWC_SIGNATURE_Y); 1217 1218 x_offset = ast_crtc->offset_x; 1219 y_offset = ast_crtc->offset_y; 1220 if (x < 0) { 1221 x_offset = (-x) + ast_crtc->offset_x; 1222 x = 0; 1223 } 1224 1225 if (y < 0) { 1226 y_offset = (-y) + ast_crtc->offset_y; 1227 y = 0; 1228 } 1229 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1230 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1231 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1232 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1233 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1234 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1235 1236 /* dummy write to fire HWC */ 1237 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00); 1238 1239 return 0; 1240 } 1241