1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include "ast_drv.h" 36 37 #include "ast_tables.h" 38 39 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 40 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 41 static int ast_cursor_set(struct drm_crtc *crtc, 42 struct drm_file *file_priv, 43 uint32_t handle, 44 uint32_t width, 45 uint32_t height); 46 static int ast_cursor_move(struct drm_crtc *crtc, 47 int x, int y); 48 49 static inline void ast_load_palette_index(struct ast_private *ast, 50 u8 index, u8 red, u8 green, 51 u8 blue) 52 { 53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 54 ast_io_read8(ast, AST_IO_SEQ_PORT); 55 ast_io_write8(ast, AST_IO_DAC_DATA, red); 56 ast_io_read8(ast, AST_IO_SEQ_PORT); 57 ast_io_write8(ast, AST_IO_DAC_DATA, green); 58 ast_io_read8(ast, AST_IO_SEQ_PORT); 59 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 60 ast_io_read8(ast, AST_IO_SEQ_PORT); 61 } 62 63 static void ast_crtc_load_lut(struct drm_crtc *crtc) 64 { 65 struct ast_private *ast = crtc->dev->dev_private; 66 u16 *r, *g, *b; 67 int i; 68 69 if (!crtc->enabled) 70 return; 71 72 r = crtc->gamma_store; 73 g = r + crtc->gamma_size; 74 b = g + crtc->gamma_size; 75 76 for (i = 0; i < 256; i++) 77 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8); 78 } 79 80 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, 81 struct drm_display_mode *adjusted_mode, 82 struct ast_vbios_mode_info *vbios_mode) 83 { 84 struct ast_private *ast = crtc->dev->dev_private; 85 const struct drm_framebuffer *fb = crtc->primary->fb; 86 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; 87 const struct ast_vbios_enhtable *best = NULL; 88 u32 hborder, vborder; 89 bool check_sync; 90 91 switch (fb->format->cpp[0] * 8) { 92 case 8: 93 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 94 color_index = VGAModeIndex - 1; 95 break; 96 case 16: 97 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 98 color_index = HiCModeIndex; 99 break; 100 case 24: 101 case 32: 102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 103 color_index = TrueCModeIndex; 104 break; 105 default: 106 return false; 107 } 108 109 switch (crtc->mode.crtc_hdisplay) { 110 case 640: 111 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 112 break; 113 case 800: 114 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 115 break; 116 case 1024: 117 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 118 break; 119 case 1280: 120 if (crtc->mode.crtc_vdisplay == 800) 121 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 122 else 123 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 124 break; 125 case 1360: 126 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 127 break; 128 case 1440: 129 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 130 break; 131 case 1600: 132 if (crtc->mode.crtc_vdisplay == 900) 133 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 134 else 135 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 136 break; 137 case 1680: 138 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 139 break; 140 case 1920: 141 if (crtc->mode.crtc_vdisplay == 1080) 142 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 143 else 144 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 145 break; 146 default: 147 return false; 148 } 149 150 refresh_rate = drm_mode_vrefresh(mode); 151 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 152 do { 153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 154 155 while (loop->refresh_rate != 0xff) { 156 if ((check_sync) && 157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 158 (loop->flags & PVSync)) || 159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 160 (loop->flags & NVSync)) || 161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 162 (loop->flags & PHSync)) || 163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 164 (loop->flags & NHSync)))) { 165 loop++; 166 continue; 167 } 168 if (loop->refresh_rate <= refresh_rate 169 && (!best || loop->refresh_rate > best->refresh_rate)) 170 best = loop; 171 loop++; 172 } 173 if (best || !check_sync) 174 break; 175 check_sync = 0; 176 } while (1); 177 if (best) 178 vbios_mode->enh_table = best; 179 180 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 181 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 182 183 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 184 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 185 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 186 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 187 vbios_mode->enh_table->hfp; 188 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 189 vbios_mode->enh_table->hfp + 190 vbios_mode->enh_table->hsync); 191 192 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 193 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 194 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 195 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 196 vbios_mode->enh_table->vfp; 197 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 198 vbios_mode->enh_table->vfp + 199 vbios_mode->enh_table->vsync); 200 201 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 202 mode_id = vbios_mode->enh_table->mode_id; 203 204 if (ast->chip == AST1180) { 205 /* TODO 1180 */ 206 } else { 207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); 208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 210 211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 212 if (vbios_mode->enh_table->flags & NewModeInfo) { 213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, 215 fb->format->cpp[0] * 8); 216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 219 220 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 221 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 222 } 223 } 224 225 return true; 226 227 228 } 229 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 230 struct ast_vbios_mode_info *vbios_mode) 231 { 232 struct ast_private *ast = crtc->dev->dev_private; 233 const struct ast_vbios_stdtable *stdtable; 234 u32 i; 235 u8 jreg; 236 237 stdtable = vbios_mode->std_table; 238 239 jreg = stdtable->misc; 240 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 241 242 /* Set SEQ */ 243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 244 for (i = 0; i < 4; i++) { 245 jreg = stdtable->seq[i]; 246 if (!i) 247 jreg |= 0x20; 248 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 249 } 250 251 /* Set CRTC */ 252 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 253 for (i = 0; i < 25; i++) 254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 255 256 /* set AR */ 257 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 258 for (i = 0; i < 20; i++) { 259 jreg = stdtable->ar[i]; 260 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 262 } 263 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 265 266 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 267 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 268 269 /* Set GR */ 270 for (i = 0; i < 9; i++) 271 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 272 } 273 274 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 275 struct ast_vbios_mode_info *vbios_mode) 276 { 277 struct ast_private *ast = crtc->dev->dev_private; 278 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 279 u16 temp, precache = 0; 280 281 if ((ast->chip == AST2500) && 282 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 283 precache = 40; 284 285 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 286 287 temp = (mode->crtc_htotal >> 3) - 5; 288 if (temp & 0x100) 289 jregAC |= 0x01; /* HT D[8] */ 290 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 291 292 temp = (mode->crtc_hdisplay >> 3) - 1; 293 if (temp & 0x100) 294 jregAC |= 0x04; /* HDE D[8] */ 295 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 296 297 temp = (mode->crtc_hblank_start >> 3) - 1; 298 if (temp & 0x100) 299 jregAC |= 0x10; /* HBS D[8] */ 300 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 301 302 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 303 if (temp & 0x20) 304 jreg05 |= 0x80; /* HBE D[5] */ 305 if (temp & 0x40) 306 jregAD |= 0x01; /* HBE D[5] */ 307 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 308 309 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 310 if (temp & 0x100) 311 jregAC |= 0x40; /* HRS D[5] */ 312 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 313 314 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 315 if (temp & 0x20) 316 jregAD |= 0x04; /* HRE D[5] */ 317 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 318 319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 320 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 321 322 /* vert timings */ 323 temp = (mode->crtc_vtotal) - 2; 324 if (temp & 0x100) 325 jreg07 |= 0x01; 326 if (temp & 0x200) 327 jreg07 |= 0x20; 328 if (temp & 0x400) 329 jregAE |= 0x01; 330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 331 332 temp = (mode->crtc_vsync_start) - 1; 333 if (temp & 0x100) 334 jreg07 |= 0x04; 335 if (temp & 0x200) 336 jreg07 |= 0x80; 337 if (temp & 0x400) 338 jregAE |= 0x08; 339 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 340 341 temp = (mode->crtc_vsync_end - 1) & 0x3f; 342 if (temp & 0x10) 343 jregAE |= 0x20; 344 if (temp & 0x20) 345 jregAE |= 0x40; 346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 347 348 temp = mode->crtc_vdisplay - 1; 349 if (temp & 0x100) 350 jreg07 |= 0x02; 351 if (temp & 0x200) 352 jreg07 |= 0x40; 353 if (temp & 0x400) 354 jregAE |= 0x02; 355 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 356 357 temp = mode->crtc_vblank_start - 1; 358 if (temp & 0x100) 359 jreg07 |= 0x08; 360 if (temp & 0x200) 361 jreg09 |= 0x20; 362 if (temp & 0x400) 363 jregAE |= 0x04; 364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 365 366 temp = mode->crtc_vblank_end - 1; 367 if (temp & 0x100) 368 jregAE |= 0x10; 369 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 370 371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 372 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 374 375 if (precache) 376 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 377 else 378 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 379 380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 381 } 382 383 static void ast_set_offset_reg(struct drm_crtc *crtc) 384 { 385 struct ast_private *ast = crtc->dev->dev_private; 386 const struct drm_framebuffer *fb = crtc->primary->fb; 387 388 u16 offset; 389 390 offset = fb->pitches[0] >> 3; 391 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 392 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 393 } 394 395 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, 396 struct ast_vbios_mode_info *vbios_mode) 397 { 398 struct ast_private *ast = dev->dev_private; 399 const struct ast_vbios_dclk_info *clk_info; 400 401 if (ast->chip == AST2500) 402 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 403 else 404 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 405 406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 408 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 409 (clk_info->param3 & 0xc0) | 410 ((clk_info->param3 & 0x3) << 4)); 411 } 412 413 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 414 struct ast_vbios_mode_info *vbios_mode) 415 { 416 struct ast_private *ast = crtc->dev->dev_private; 417 const struct drm_framebuffer *fb = crtc->primary->fb; 418 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 419 420 switch (fb->format->cpp[0] * 8) { 421 case 8: 422 jregA0 = 0x70; 423 jregA3 = 0x01; 424 jregA8 = 0x00; 425 break; 426 case 15: 427 case 16: 428 jregA0 = 0x70; 429 jregA3 = 0x04; 430 jregA8 = 0x02; 431 break; 432 case 32: 433 jregA0 = 0x70; 434 jregA3 = 0x08; 435 jregA8 = 0x02; 436 break; 437 } 438 439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 441 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 442 443 /* Set Threshold */ 444 if (ast->chip == AST2300 || ast->chip == AST2400 || 445 ast->chip == AST2500) { 446 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 447 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 448 } else if (ast->chip == AST2100 || 449 ast->chip == AST1100 || 450 ast->chip == AST2200 || 451 ast->chip == AST2150) { 452 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 453 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 454 } else { 455 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 456 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 457 } 458 } 459 460 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, 461 struct ast_vbios_mode_info *vbios_mode) 462 { 463 struct ast_private *ast = dev->dev_private; 464 u8 jreg; 465 466 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 467 jreg &= ~0xC0; 468 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 469 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 470 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 471 } 472 473 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 474 struct ast_vbios_mode_info *vbios_mode) 475 { 476 const struct drm_framebuffer *fb = crtc->primary->fb; 477 478 switch (fb->format->cpp[0] * 8) { 479 case 8: 480 break; 481 default: 482 return false; 483 } 484 return true; 485 } 486 487 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset) 488 { 489 struct ast_private *ast = crtc->dev->dev_private; 490 u32 addr; 491 492 addr = offset >> 2; 493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 494 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 496 497 } 498 499 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 500 { 501 struct ast_private *ast = crtc->dev->dev_private; 502 503 if (ast->chip == AST1180) 504 return; 505 506 switch (mode) { 507 case DRM_MODE_DPMS_ON: 508 case DRM_MODE_DPMS_STANDBY: 509 case DRM_MODE_DPMS_SUSPEND: 510 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 511 if (ast->tx_chip_type == AST_TX_DP501) 512 ast_set_dp501_video_output(crtc->dev, 1); 513 ast_crtc_load_lut(crtc); 514 break; 515 case DRM_MODE_DPMS_OFF: 516 if (ast->tx_chip_type == AST_TX_DP501) 517 ast_set_dp501_video_output(crtc->dev, 0); 518 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 519 break; 520 } 521 } 522 523 /* ast is different - we will force move buffers out of VRAM */ 524 static int ast_crtc_do_set_base(struct drm_crtc *crtc, 525 struct drm_framebuffer *fb, 526 int x, int y, int atomic) 527 { 528 struct ast_private *ast = crtc->dev->dev_private; 529 struct drm_gem_object *obj; 530 struct ast_framebuffer *ast_fb; 531 struct ast_bo *bo; 532 int ret; 533 u64 gpu_addr; 534 535 /* push the previous fb to system ram */ 536 if (!atomic && fb) { 537 ast_fb = to_ast_framebuffer(fb); 538 obj = ast_fb->obj; 539 bo = gem_to_ast_bo(obj); 540 ret = ast_bo_reserve(bo, false); 541 if (ret) 542 return ret; 543 ast_bo_push_sysram(bo); 544 ast_bo_unreserve(bo); 545 } 546 547 ast_fb = to_ast_framebuffer(crtc->primary->fb); 548 obj = ast_fb->obj; 549 bo = gem_to_ast_bo(obj); 550 551 ret = ast_bo_reserve(bo, false); 552 if (ret) 553 return ret; 554 555 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 556 if (ret) { 557 ast_bo_unreserve(bo); 558 return ret; 559 } 560 561 if (&ast->fbdev->afb == ast_fb) { 562 /* if pushing console in kmap it */ 563 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 564 if (ret) 565 DRM_ERROR("failed to kmap fbcon\n"); 566 else 567 ast_fbdev_set_base(ast, gpu_addr); 568 } 569 ast_bo_unreserve(bo); 570 571 ast_set_offset_reg(crtc); 572 ast_set_start_address_crt1(crtc, (u32)gpu_addr); 573 574 return 0; 575 } 576 577 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 578 struct drm_framebuffer *old_fb) 579 { 580 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0); 581 } 582 583 static int ast_crtc_mode_set(struct drm_crtc *crtc, 584 struct drm_display_mode *mode, 585 struct drm_display_mode *adjusted_mode, 586 int x, int y, 587 struct drm_framebuffer *old_fb) 588 { 589 struct drm_device *dev = crtc->dev; 590 struct ast_private *ast = crtc->dev->dev_private; 591 struct ast_vbios_mode_info vbios_mode; 592 bool ret; 593 if (ast->chip == AST1180) { 594 DRM_ERROR("AST 1180 modesetting not supported\n"); 595 return -EINVAL; 596 } 597 598 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); 599 if (ret == false) 600 return -EINVAL; 601 ast_open_key(ast); 602 603 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); 604 605 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); 606 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); 607 ast_set_offset_reg(crtc); 608 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); 609 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); 610 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); 611 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode); 612 613 ast_crtc_mode_set_base(crtc, x, y, old_fb); 614 615 return 0; 616 } 617 618 static void ast_crtc_disable(struct drm_crtc *crtc) 619 { 620 int ret; 621 622 DRM_DEBUG_KMS("\n"); 623 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 624 if (crtc->primary->fb) { 625 struct ast_framebuffer *ast_fb = to_ast_framebuffer(crtc->primary->fb); 626 struct drm_gem_object *obj = ast_fb->obj; 627 struct ast_bo *bo = gem_to_ast_bo(obj); 628 629 ret = ast_bo_reserve(bo, false); 630 if (ret) 631 return; 632 633 ast_bo_push_sysram(bo); 634 ast_bo_unreserve(bo); 635 } 636 crtc->primary->fb = NULL; 637 } 638 639 static void ast_crtc_prepare(struct drm_crtc *crtc) 640 { 641 642 } 643 644 static void ast_crtc_commit(struct drm_crtc *crtc) 645 { 646 struct ast_private *ast = crtc->dev->dev_private; 647 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 648 ast_crtc_load_lut(crtc); 649 } 650 651 652 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 653 .dpms = ast_crtc_dpms, 654 .mode_set = ast_crtc_mode_set, 655 .mode_set_base = ast_crtc_mode_set_base, 656 .disable = ast_crtc_disable, 657 .prepare = ast_crtc_prepare, 658 .commit = ast_crtc_commit, 659 660 }; 661 662 static void ast_crtc_reset(struct drm_crtc *crtc) 663 { 664 665 } 666 667 static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 668 u16 *blue, uint32_t size, 669 struct drm_modeset_acquire_ctx *ctx) 670 { 671 ast_crtc_load_lut(crtc); 672 673 return 0; 674 } 675 676 677 static void ast_crtc_destroy(struct drm_crtc *crtc) 678 { 679 drm_crtc_cleanup(crtc); 680 kfree(crtc); 681 } 682 683 static const struct drm_crtc_funcs ast_crtc_funcs = { 684 .cursor_set = ast_cursor_set, 685 .cursor_move = ast_cursor_move, 686 .reset = ast_crtc_reset, 687 .set_config = drm_crtc_helper_set_config, 688 .gamma_set = ast_crtc_gamma_set, 689 .destroy = ast_crtc_destroy, 690 }; 691 692 static int ast_crtc_init(struct drm_device *dev) 693 { 694 struct ast_crtc *crtc; 695 696 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 697 if (!crtc) 698 return -ENOMEM; 699 700 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); 701 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 702 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 703 return 0; 704 } 705 706 static void ast_encoder_destroy(struct drm_encoder *encoder) 707 { 708 drm_encoder_cleanup(encoder); 709 kfree(encoder); 710 } 711 712 713 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector) 714 { 715 int enc_id = connector->encoder_ids[0]; 716 /* pick the encoder ids */ 717 if (enc_id) 718 return drm_encoder_find(connector->dev, NULL, enc_id); 719 return NULL; 720 } 721 722 723 static const struct drm_encoder_funcs ast_enc_funcs = { 724 .destroy = ast_encoder_destroy, 725 }; 726 727 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode) 728 { 729 730 } 731 732 static void ast_encoder_mode_set(struct drm_encoder *encoder, 733 struct drm_display_mode *mode, 734 struct drm_display_mode *adjusted_mode) 735 { 736 } 737 738 static void ast_encoder_prepare(struct drm_encoder *encoder) 739 { 740 741 } 742 743 static void ast_encoder_commit(struct drm_encoder *encoder) 744 { 745 746 } 747 748 749 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = { 750 .dpms = ast_encoder_dpms, 751 .prepare = ast_encoder_prepare, 752 .commit = ast_encoder_commit, 753 .mode_set = ast_encoder_mode_set, 754 }; 755 756 static int ast_encoder_init(struct drm_device *dev) 757 { 758 struct ast_encoder *ast_encoder; 759 760 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL); 761 if (!ast_encoder) 762 return -ENOMEM; 763 764 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs, 765 DRM_MODE_ENCODER_DAC, NULL); 766 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); 767 768 ast_encoder->base.possible_crtcs = 1; 769 return 0; 770 } 771 772 static int ast_get_modes(struct drm_connector *connector) 773 { 774 struct ast_connector *ast_connector = to_ast_connector(connector); 775 struct ast_private *ast = connector->dev->dev_private; 776 struct edid *edid; 777 int ret; 778 bool flags = false; 779 if (ast->tx_chip_type == AST_TX_DP501) { 780 ast->dp501_maxclk = 0xff; 781 edid = kmalloc(128, GFP_KERNEL); 782 if (!edid) 783 return -ENOMEM; 784 785 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 786 if (flags) 787 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 788 else 789 kfree(edid); 790 } 791 if (!flags) 792 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 793 if (edid) { 794 drm_connector_update_edid_property(&ast_connector->base, edid); 795 ret = drm_add_edid_modes(connector, edid); 796 kfree(edid); 797 return ret; 798 } else 799 drm_connector_update_edid_property(&ast_connector->base, NULL); 800 return 0; 801 } 802 803 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, 804 struct drm_display_mode *mode) 805 { 806 struct ast_private *ast = connector->dev->dev_private; 807 int flags = MODE_NOMODE; 808 uint32_t jtemp; 809 810 if (ast->support_wide_screen) { 811 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 812 return MODE_OK; 813 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 814 return MODE_OK; 815 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 816 return MODE_OK; 817 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 818 return MODE_OK; 819 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 820 return MODE_OK; 821 822 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 823 (ast->chip == AST2300) || (ast->chip == AST2400) || 824 (ast->chip == AST2500) || (ast->chip == AST1180)) { 825 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 826 return MODE_OK; 827 828 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 829 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 830 if (jtemp & 0x01) 831 return MODE_NOMODE; 832 else 833 return MODE_OK; 834 } 835 } 836 } 837 switch (mode->hdisplay) { 838 case 640: 839 if (mode->vdisplay == 480) flags = MODE_OK; 840 break; 841 case 800: 842 if (mode->vdisplay == 600) flags = MODE_OK; 843 break; 844 case 1024: 845 if (mode->vdisplay == 768) flags = MODE_OK; 846 break; 847 case 1280: 848 if (mode->vdisplay == 1024) flags = MODE_OK; 849 break; 850 case 1600: 851 if (mode->vdisplay == 1200) flags = MODE_OK; 852 break; 853 default: 854 return flags; 855 } 856 857 return flags; 858 } 859 860 static void ast_connector_destroy(struct drm_connector *connector) 861 { 862 struct ast_connector *ast_connector = to_ast_connector(connector); 863 ast_i2c_destroy(ast_connector->i2c); 864 drm_connector_unregister(connector); 865 drm_connector_cleanup(connector); 866 kfree(connector); 867 } 868 869 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 870 .mode_valid = ast_mode_valid, 871 .get_modes = ast_get_modes, 872 .best_encoder = ast_best_single_encoder, 873 }; 874 875 static const struct drm_connector_funcs ast_connector_funcs = { 876 .dpms = drm_helper_connector_dpms, 877 .fill_modes = drm_helper_probe_single_connector_modes, 878 .destroy = ast_connector_destroy, 879 }; 880 881 static int ast_connector_init(struct drm_device *dev) 882 { 883 struct ast_connector *ast_connector; 884 struct drm_connector *connector; 885 struct drm_encoder *encoder; 886 887 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 888 if (!ast_connector) 889 return -ENOMEM; 890 891 connector = &ast_connector->base; 892 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA); 893 894 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 895 896 connector->interlace_allowed = 0; 897 connector->doublescan_allowed = 0; 898 899 drm_connector_register(connector); 900 901 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 902 903 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 904 drm_connector_attach_encoder(connector, encoder); 905 906 ast_connector->i2c = ast_i2c_create(dev); 907 if (!ast_connector->i2c) 908 DRM_ERROR("failed to add ddc bus for connector\n"); 909 910 return 0; 911 } 912 913 /* allocate cursor cache and pin at start of VRAM */ 914 static int ast_cursor_init(struct drm_device *dev) 915 { 916 struct ast_private *ast = dev->dev_private; 917 int size; 918 int ret; 919 struct drm_gem_object *obj; 920 struct ast_bo *bo; 921 uint64_t gpu_addr; 922 923 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM; 924 925 ret = ast_gem_create(dev, size, true, &obj); 926 if (ret) 927 return ret; 928 bo = gem_to_ast_bo(obj); 929 ret = ast_bo_reserve(bo, false); 930 if (unlikely(ret != 0)) 931 goto fail; 932 933 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 934 ast_bo_unreserve(bo); 935 if (ret) 936 goto fail; 937 938 /* kmap the object */ 939 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap); 940 if (ret) 941 goto fail; 942 943 ast->cursor_cache = obj; 944 ast->cursor_cache_gpu_addr = gpu_addr; 945 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr); 946 return 0; 947 fail: 948 return ret; 949 } 950 951 static void ast_cursor_fini(struct drm_device *dev) 952 { 953 struct ast_private *ast = dev->dev_private; 954 ttm_bo_kunmap(&ast->cache_kmap); 955 drm_gem_object_put_unlocked(ast->cursor_cache); 956 } 957 958 int ast_mode_init(struct drm_device *dev) 959 { 960 ast_cursor_init(dev); 961 ast_crtc_init(dev); 962 ast_encoder_init(dev); 963 ast_connector_init(dev); 964 return 0; 965 } 966 967 void ast_mode_fini(struct drm_device *dev) 968 { 969 ast_cursor_fini(dev); 970 } 971 972 static int get_clock(void *i2c_priv) 973 { 974 struct ast_i2c_chan *i2c = i2c_priv; 975 struct ast_private *ast = i2c->dev->dev_private; 976 uint32_t val, val2, count, pass; 977 978 count = 0; 979 pass = 0; 980 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 981 do { 982 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 983 if (val == val2) { 984 pass++; 985 } else { 986 pass = 0; 987 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 988 } 989 } while ((pass < 5) && (count++ < 0x10000)); 990 991 return val & 1 ? 1 : 0; 992 } 993 994 static int get_data(void *i2c_priv) 995 { 996 struct ast_i2c_chan *i2c = i2c_priv; 997 struct ast_private *ast = i2c->dev->dev_private; 998 uint32_t val, val2, count, pass; 999 1000 count = 0; 1001 pass = 0; 1002 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1003 do { 1004 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1005 if (val == val2) { 1006 pass++; 1007 } else { 1008 pass = 0; 1009 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1010 } 1011 } while ((pass < 5) && (count++ < 0x10000)); 1012 1013 return val & 1 ? 1 : 0; 1014 } 1015 1016 static void set_clock(void *i2c_priv, int clock) 1017 { 1018 struct ast_i2c_chan *i2c = i2c_priv; 1019 struct ast_private *ast = i2c->dev->dev_private; 1020 int i; 1021 u8 ujcrb7, jtemp; 1022 1023 for (i = 0; i < 0x10000; i++) { 1024 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1025 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); 1026 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1027 if (ujcrb7 == jtemp) 1028 break; 1029 } 1030 } 1031 1032 static void set_data(void *i2c_priv, int data) 1033 { 1034 struct ast_i2c_chan *i2c = i2c_priv; 1035 struct ast_private *ast = i2c->dev->dev_private; 1036 int i; 1037 u8 ujcrb7, jtemp; 1038 1039 for (i = 0; i < 0x10000; i++) { 1040 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1041 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); 1042 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1043 if (ujcrb7 == jtemp) 1044 break; 1045 } 1046 } 1047 1048 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1049 { 1050 struct ast_i2c_chan *i2c; 1051 int ret; 1052 1053 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1054 if (!i2c) 1055 return NULL; 1056 1057 i2c->adapter.owner = THIS_MODULE; 1058 i2c->adapter.class = I2C_CLASS_DDC; 1059 i2c->adapter.dev.parent = &dev->pdev->dev; 1060 i2c->dev = dev; 1061 i2c_set_adapdata(&i2c->adapter, i2c); 1062 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1063 "AST i2c bit bus"); 1064 i2c->adapter.algo_data = &i2c->bit; 1065 1066 i2c->bit.udelay = 20; 1067 i2c->bit.timeout = 2; 1068 i2c->bit.data = i2c; 1069 i2c->bit.setsda = set_data; 1070 i2c->bit.setscl = set_clock; 1071 i2c->bit.getsda = get_data; 1072 i2c->bit.getscl = get_clock; 1073 ret = i2c_bit_add_bus(&i2c->adapter); 1074 if (ret) { 1075 DRM_ERROR("Failed to register bit i2c\n"); 1076 goto out_free; 1077 } 1078 1079 return i2c; 1080 out_free: 1081 kfree(i2c); 1082 return NULL; 1083 } 1084 1085 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1086 { 1087 if (!i2c) 1088 return; 1089 i2c_del_adapter(&i2c->adapter); 1090 kfree(i2c); 1091 } 1092 1093 static void ast_show_cursor(struct drm_crtc *crtc) 1094 { 1095 struct ast_private *ast = crtc->dev->dev_private; 1096 u8 jreg; 1097 1098 jreg = 0x2; 1099 /* enable ARGB cursor */ 1100 jreg |= 1; 1101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1102 } 1103 1104 static void ast_hide_cursor(struct drm_crtc *crtc) 1105 { 1106 struct ast_private *ast = crtc->dev->dev_private; 1107 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 1108 } 1109 1110 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1111 { 1112 union { 1113 u32 ul; 1114 u8 b[4]; 1115 } srcdata32[2], data32; 1116 union { 1117 u16 us; 1118 u8 b[2]; 1119 } data16; 1120 u32 csum = 0; 1121 s32 alpha_dst_delta, last_alpha_dst_delta; 1122 u8 *srcxor, *dstxor; 1123 int i, j; 1124 u32 per_pixel_copy, two_pixel_copy; 1125 1126 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1127 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1128 1129 srcxor = src; 1130 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1131 per_pixel_copy = width & 1; 1132 two_pixel_copy = width >> 1; 1133 1134 for (j = 0; j < height; j++) { 1135 for (i = 0; i < two_pixel_copy; i++) { 1136 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1137 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1138 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1139 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1140 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1141 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1142 1143 writel(data32.ul, dstxor); 1144 csum += data32.ul; 1145 1146 dstxor += 4; 1147 srcxor += 8; 1148 1149 } 1150 1151 for (i = 0; i < per_pixel_copy; i++) { 1152 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1153 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1154 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1155 writew(data16.us, dstxor); 1156 csum += (u32)data16.us; 1157 1158 dstxor += 2; 1159 srcxor += 4; 1160 } 1161 dstxor += last_alpha_dst_delta; 1162 } 1163 return csum; 1164 } 1165 1166 static int ast_cursor_set(struct drm_crtc *crtc, 1167 struct drm_file *file_priv, 1168 uint32_t handle, 1169 uint32_t width, 1170 uint32_t height) 1171 { 1172 struct ast_private *ast = crtc->dev->dev_private; 1173 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1174 struct drm_gem_object *obj; 1175 struct ast_bo *bo; 1176 uint64_t gpu_addr; 1177 u32 csum; 1178 int ret; 1179 struct ttm_bo_kmap_obj uobj_map; 1180 u8 *src, *dst; 1181 bool src_isiomem, dst_isiomem; 1182 if (!handle) { 1183 ast_hide_cursor(crtc); 1184 return 0; 1185 } 1186 1187 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT) 1188 return -EINVAL; 1189 1190 obj = drm_gem_object_lookup(file_priv, handle); 1191 if (!obj) { 1192 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle); 1193 return -ENOENT; 1194 } 1195 bo = gem_to_ast_bo(obj); 1196 1197 ret = ast_bo_reserve(bo, false); 1198 if (ret) 1199 goto fail; 1200 1201 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map); 1202 1203 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem); 1204 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem); 1205 1206 if (src_isiomem == true) 1207 DRM_ERROR("src cursor bo should be in main memory\n"); 1208 if (dst_isiomem == false) 1209 DRM_ERROR("dst bo should be in VRAM\n"); 1210 1211 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1212 1213 /* do data transfer to cursor cache */ 1214 csum = copy_cursor_image(src, dst, width, height); 1215 1216 /* write checksum + signature */ 1217 ttm_bo_kunmap(&uobj_map); 1218 ast_bo_unreserve(bo); 1219 { 1220 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1221 writel(csum, dst); 1222 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1223 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1224 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1225 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1226 1227 /* set pattern offset */ 1228 gpu_addr = ast->cursor_cache_gpu_addr; 1229 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1230 gpu_addr >>= 3; 1231 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff); 1232 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff); 1233 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff); 1234 } 1235 ast_crtc->cursor_width = width; 1236 ast_crtc->cursor_height = height; 1237 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width; 1238 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height; 1239 1240 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM; 1241 1242 ast_show_cursor(crtc); 1243 1244 drm_gem_object_put_unlocked(obj); 1245 return 0; 1246 fail: 1247 drm_gem_object_put_unlocked(obj); 1248 return ret; 1249 } 1250 1251 static int ast_cursor_move(struct drm_crtc *crtc, 1252 int x, int y) 1253 { 1254 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1255 struct ast_private *ast = crtc->dev->dev_private; 1256 int x_offset, y_offset; 1257 u8 *sig; 1258 1259 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1260 writel(x, sig + AST_HWC_SIGNATURE_X); 1261 writel(y, sig + AST_HWC_SIGNATURE_Y); 1262 1263 x_offset = ast_crtc->offset_x; 1264 y_offset = ast_crtc->offset_y; 1265 if (x < 0) { 1266 x_offset = (-x) + ast_crtc->offset_x; 1267 x = 0; 1268 } 1269 1270 if (y < 0) { 1271 y_offset = (-y) + ast_crtc->offset_y; 1272 y = 0; 1273 } 1274 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1275 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1276 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1277 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1278 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1279 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1280 1281 /* dummy write to fire HWC */ 1282 ast_show_cursor(crtc); 1283 1284 return 0; 1285 } 1286