1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 31 #include <linux/export.h> 32 #include <linux/pci.h> 33 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_atomic_state_helper.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fourcc.h> 40 #include <drm/drm_gem_vram_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_simple_kms_helper.h> 44 45 #include "ast_drv.h" 46 #include "ast_tables.h" 47 48 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 49 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 50 static int ast_cursor_move(struct drm_crtc *crtc, 51 int x, int y); 52 53 54 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height); 55 static int ast_cursor_update(void *dst, void *src, unsigned int width, 56 unsigned int height); 57 static void ast_cursor_set_base(struct ast_private *ast, u64 address); 58 static int ast_cursor_move(struct drm_crtc *crtc, 59 int x, int y); 60 61 static inline void ast_load_palette_index(struct ast_private *ast, 62 u8 index, u8 red, u8 green, 63 u8 blue) 64 { 65 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 66 ast_io_read8(ast, AST_IO_SEQ_PORT); 67 ast_io_write8(ast, AST_IO_DAC_DATA, red); 68 ast_io_read8(ast, AST_IO_SEQ_PORT); 69 ast_io_write8(ast, AST_IO_DAC_DATA, green); 70 ast_io_read8(ast, AST_IO_SEQ_PORT); 71 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 72 ast_io_read8(ast, AST_IO_SEQ_PORT); 73 } 74 75 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc) 76 { 77 u16 *r, *g, *b; 78 int i; 79 80 if (!crtc->enabled) 81 return; 82 83 r = crtc->gamma_store; 84 g = r + crtc->gamma_size; 85 b = g + crtc->gamma_size; 86 87 for (i = 0; i < 256; i++) 88 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8); 89 } 90 91 static bool ast_get_vbios_mode_info(const struct drm_format_info *format, 92 const struct drm_display_mode *mode, 93 struct drm_display_mode *adjusted_mode, 94 struct ast_vbios_mode_info *vbios_mode) 95 { 96 u32 refresh_rate_index = 0, refresh_rate; 97 const struct ast_vbios_enhtable *best = NULL; 98 u32 hborder, vborder; 99 bool check_sync; 100 101 switch (format->cpp[0] * 8) { 102 case 8: 103 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 104 break; 105 case 16: 106 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 107 break; 108 case 24: 109 case 32: 110 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 111 break; 112 default: 113 return false; 114 } 115 116 switch (mode->crtc_hdisplay) { 117 case 640: 118 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 119 break; 120 case 800: 121 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 122 break; 123 case 1024: 124 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 125 break; 126 case 1280: 127 if (mode->crtc_vdisplay == 800) 128 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 129 else 130 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 131 break; 132 case 1360: 133 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 134 break; 135 case 1440: 136 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 137 break; 138 case 1600: 139 if (mode->crtc_vdisplay == 900) 140 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 141 else 142 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 143 break; 144 case 1680: 145 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 146 break; 147 case 1920: 148 if (mode->crtc_vdisplay == 1080) 149 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 150 else 151 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 152 break; 153 default: 154 return false; 155 } 156 157 refresh_rate = drm_mode_vrefresh(mode); 158 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 159 160 while (1) { 161 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 162 163 while (loop->refresh_rate != 0xff) { 164 if ((check_sync) && 165 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 166 (loop->flags & PVSync)) || 167 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 168 (loop->flags & NVSync)) || 169 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 170 (loop->flags & PHSync)) || 171 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 172 (loop->flags & NHSync)))) { 173 loop++; 174 continue; 175 } 176 if (loop->refresh_rate <= refresh_rate 177 && (!best || loop->refresh_rate > best->refresh_rate)) 178 best = loop; 179 loop++; 180 } 181 if (best || !check_sync) 182 break; 183 check_sync = 0; 184 } 185 186 if (best) 187 vbios_mode->enh_table = best; 188 189 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 190 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 191 192 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 193 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 194 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 195 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 196 vbios_mode->enh_table->hfp; 197 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 198 vbios_mode->enh_table->hfp + 199 vbios_mode->enh_table->hsync); 200 201 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 202 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 203 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 204 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 205 vbios_mode->enh_table->vfp; 206 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 207 vbios_mode->enh_table->vfp + 208 vbios_mode->enh_table->vsync); 209 210 return true; 211 } 212 213 static void ast_set_vbios_color_reg(struct ast_private *ast, 214 const struct drm_format_info *format, 215 const struct ast_vbios_mode_info *vbios_mode) 216 { 217 u32 color_index; 218 219 switch (format->cpp[0]) { 220 case 1: 221 color_index = VGAModeIndex - 1; 222 break; 223 case 2: 224 color_index = HiCModeIndex; 225 break; 226 case 3: 227 case 4: 228 color_index = TrueCModeIndex; 229 break; 230 default: 231 return; 232 } 233 234 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4)); 235 236 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 237 238 if (vbios_mode->enh_table->flags & NewModeInfo) { 239 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 240 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8); 241 } 242 } 243 244 static void ast_set_vbios_mode_reg(struct ast_private *ast, 245 const struct drm_display_mode *adjusted_mode, 246 const struct ast_vbios_mode_info *vbios_mode) 247 { 248 u32 refresh_rate_index, mode_id; 249 250 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 251 mode_id = vbios_mode->enh_table->mode_id; 252 253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 255 256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 257 258 if (vbios_mode->enh_table->flags & NewModeInfo) { 259 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 260 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 261 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 262 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 263 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 264 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 265 } 266 } 267 268 static void ast_set_std_reg(struct ast_private *ast, 269 struct drm_display_mode *mode, 270 struct ast_vbios_mode_info *vbios_mode) 271 { 272 const struct ast_vbios_stdtable *stdtable; 273 u32 i; 274 u8 jreg; 275 276 stdtable = vbios_mode->std_table; 277 278 jreg = stdtable->misc; 279 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 280 281 /* Set SEQ; except Screen Disable field */ 282 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 283 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]); 284 for (i = 1; i < 4; i++) { 285 jreg = stdtable->seq[i]; 286 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 287 } 288 289 /* Set CRTC; except base address and offset */ 290 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 291 for (i = 0; i < 12; i++) 292 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 293 for (i = 14; i < 19; i++) 294 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 295 for (i = 20; i < 25; i++) 296 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 297 298 /* set AR */ 299 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 300 for (i = 0; i < 20; i++) { 301 jreg = stdtable->ar[i]; 302 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 303 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 304 } 305 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 306 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 307 308 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 309 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 310 311 /* Set GR */ 312 for (i = 0; i < 9; i++) 313 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 314 } 315 316 static void ast_set_crtc_reg(struct ast_private *ast, 317 struct drm_display_mode *mode, 318 struct ast_vbios_mode_info *vbios_mode) 319 { 320 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 321 u16 temp, precache = 0; 322 323 if ((ast->chip == AST2500) && 324 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 325 precache = 40; 326 327 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 328 329 temp = (mode->crtc_htotal >> 3) - 5; 330 if (temp & 0x100) 331 jregAC |= 0x01; /* HT D[8] */ 332 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 333 334 temp = (mode->crtc_hdisplay >> 3) - 1; 335 if (temp & 0x100) 336 jregAC |= 0x04; /* HDE D[8] */ 337 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 338 339 temp = (mode->crtc_hblank_start >> 3) - 1; 340 if (temp & 0x100) 341 jregAC |= 0x10; /* HBS D[8] */ 342 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 343 344 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 345 if (temp & 0x20) 346 jreg05 |= 0x80; /* HBE D[5] */ 347 if (temp & 0x40) 348 jregAD |= 0x01; /* HBE D[5] */ 349 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 350 351 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 352 if (temp & 0x100) 353 jregAC |= 0x40; /* HRS D[5] */ 354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 355 356 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 357 if (temp & 0x20) 358 jregAD |= 0x04; /* HRE D[5] */ 359 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 360 361 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 363 364 /* vert timings */ 365 temp = (mode->crtc_vtotal) - 2; 366 if (temp & 0x100) 367 jreg07 |= 0x01; 368 if (temp & 0x200) 369 jreg07 |= 0x20; 370 if (temp & 0x400) 371 jregAE |= 0x01; 372 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 373 374 temp = (mode->crtc_vsync_start) - 1; 375 if (temp & 0x100) 376 jreg07 |= 0x04; 377 if (temp & 0x200) 378 jreg07 |= 0x80; 379 if (temp & 0x400) 380 jregAE |= 0x08; 381 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 382 383 temp = (mode->crtc_vsync_end - 1) & 0x3f; 384 if (temp & 0x10) 385 jregAE |= 0x20; 386 if (temp & 0x20) 387 jregAE |= 0x40; 388 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 389 390 temp = mode->crtc_vdisplay - 1; 391 if (temp & 0x100) 392 jreg07 |= 0x02; 393 if (temp & 0x200) 394 jreg07 |= 0x40; 395 if (temp & 0x400) 396 jregAE |= 0x02; 397 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 398 399 temp = mode->crtc_vblank_start - 1; 400 if (temp & 0x100) 401 jreg07 |= 0x08; 402 if (temp & 0x200) 403 jreg09 |= 0x20; 404 if (temp & 0x400) 405 jregAE |= 0x04; 406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 407 408 temp = mode->crtc_vblank_end - 1; 409 if (temp & 0x100) 410 jregAE |= 0x10; 411 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 412 413 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 415 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 416 417 if (precache) 418 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 419 else 420 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 421 422 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 423 } 424 425 static void ast_set_offset_reg(struct ast_private *ast, 426 struct drm_framebuffer *fb) 427 { 428 u16 offset; 429 430 offset = fb->pitches[0] >> 3; 431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 432 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 433 } 434 435 static void ast_set_dclk_reg(struct ast_private *ast, 436 struct drm_display_mode *mode, 437 struct ast_vbios_mode_info *vbios_mode) 438 { 439 const struct ast_vbios_dclk_info *clk_info; 440 441 if (ast->chip == AST2500) 442 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 443 else 444 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 445 446 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 447 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 448 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 449 (clk_info->param3 & 0xc0) | 450 ((clk_info->param3 & 0x3) << 4)); 451 } 452 453 static void ast_set_color_reg(struct ast_private *ast, 454 const struct drm_format_info *format) 455 { 456 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 457 458 switch (format->cpp[0] * 8) { 459 case 8: 460 jregA0 = 0x70; 461 jregA3 = 0x01; 462 jregA8 = 0x00; 463 break; 464 case 15: 465 case 16: 466 jregA0 = 0x70; 467 jregA3 = 0x04; 468 jregA8 = 0x02; 469 break; 470 case 32: 471 jregA0 = 0x70; 472 jregA3 = 0x08; 473 jregA8 = 0x02; 474 break; 475 } 476 477 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 478 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 479 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 480 } 481 482 static void ast_set_crtthd_reg(struct ast_private *ast) 483 { 484 /* Set Threshold */ 485 if (ast->chip == AST2300 || ast->chip == AST2400 || 486 ast->chip == AST2500) { 487 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 488 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 489 } else if (ast->chip == AST2100 || 490 ast->chip == AST1100 || 491 ast->chip == AST2200 || 492 ast->chip == AST2150) { 493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 494 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 495 } else { 496 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 497 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 498 } 499 } 500 501 static void ast_set_sync_reg(struct ast_private *ast, 502 struct drm_display_mode *mode, 503 struct ast_vbios_mode_info *vbios_mode) 504 { 505 u8 jreg; 506 507 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 508 jreg &= ~0xC0; 509 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 510 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 511 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 512 } 513 514 static void ast_set_start_address_crt1(struct ast_private *ast, 515 unsigned offset) 516 { 517 u32 addr; 518 519 addr = offset >> 2; 520 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 521 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 522 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 523 524 } 525 526 /* 527 * Primary plane 528 */ 529 530 static const uint32_t ast_primary_plane_formats[] = { 531 DRM_FORMAT_XRGB8888, 532 DRM_FORMAT_RGB565, 533 DRM_FORMAT_C8, 534 }; 535 536 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, 537 struct drm_plane_state *state) 538 { 539 struct drm_crtc_state *crtc_state; 540 struct ast_crtc_state *ast_crtc_state; 541 int ret; 542 543 if (!state->crtc) 544 return 0; 545 546 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 547 548 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 549 DRM_PLANE_HELPER_NO_SCALING, 550 DRM_PLANE_HELPER_NO_SCALING, 551 false, true); 552 if (ret) 553 return ret; 554 555 if (!state->visible) 556 return 0; 557 558 ast_crtc_state = to_ast_crtc_state(crtc_state); 559 560 ast_crtc_state->format = state->fb->format; 561 562 return 0; 563 } 564 565 static void 566 ast_primary_plane_helper_atomic_update(struct drm_plane *plane, 567 struct drm_plane_state *old_state) 568 { 569 struct drm_device *dev = plane->dev; 570 struct ast_private *ast = to_ast_private(dev); 571 struct drm_plane_state *state = plane->state; 572 struct drm_gem_vram_object *gbo; 573 s64 gpu_addr; 574 575 gbo = drm_gem_vram_of_gem(state->fb->obj[0]); 576 gpu_addr = drm_gem_vram_offset(gbo); 577 if (drm_WARN_ON_ONCE(dev, gpu_addr < 0)) 578 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */ 579 580 ast_set_offset_reg(ast, state->fb); 581 ast_set_start_address_crt1(ast, (u32)gpu_addr); 582 583 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00); 584 } 585 586 static void 587 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, 588 struct drm_plane_state *old_state) 589 { 590 struct ast_private *ast = to_ast_private(plane->dev); 591 592 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 593 } 594 595 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = { 596 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, 597 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, 598 .atomic_check = ast_primary_plane_helper_atomic_check, 599 .atomic_update = ast_primary_plane_helper_atomic_update, 600 .atomic_disable = ast_primary_plane_helper_atomic_disable, 601 }; 602 603 static const struct drm_plane_funcs ast_primary_plane_funcs = { 604 .update_plane = drm_atomic_helper_update_plane, 605 .disable_plane = drm_atomic_helper_disable_plane, 606 .destroy = drm_plane_cleanup, 607 .reset = drm_atomic_helper_plane_reset, 608 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 609 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 610 }; 611 612 /* 613 * Cursor plane 614 */ 615 616 static const uint32_t ast_cursor_plane_formats[] = { 617 DRM_FORMAT_ARGB8888, 618 }; 619 620 static int 621 ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane, 622 struct drm_plane_state *new_state) 623 { 624 struct drm_device *dev = plane->dev; 625 struct drm_framebuffer *fb = new_state->fb; 626 struct drm_crtc *crtc = new_state->crtc; 627 struct drm_gem_vram_object *gbo; 628 struct ast_private *ast; 629 int ret; 630 void *src, *dst; 631 632 if (!crtc || !fb) 633 return 0; 634 635 if (drm_WARN_ON_ONCE(dev, fb->width > AST_MAX_HWC_WIDTH) || 636 drm_WARN_ON_ONCE(dev, fb->height > AST_MAX_HWC_HEIGHT)) 637 return -EINVAL; /* BUG: didn't test in atomic_check() */ 638 639 ast = to_ast_private(dev); 640 641 gbo = drm_gem_vram_of_gem(fb->obj[0]); 642 src = drm_gem_vram_vmap(gbo); 643 if (IS_ERR(src)) { 644 ret = PTR_ERR(src); 645 goto err_drm_gem_vram_unpin; 646 } 647 648 dst = drm_gem_vram_vmap(ast->cursor.gbo[ast->cursor.next_index]); 649 if (IS_ERR(dst)) { 650 ret = PTR_ERR(dst); 651 goto err_drm_gem_vram_vunmap_src; 652 } 653 654 ret = ast_cursor_update(dst, src, fb->width, fb->height); 655 if (ret) 656 goto err_drm_gem_vram_vunmap_dst; 657 658 /* Always unmap buffers here. Destination buffers are 659 * perma-pinned while the driver is active. We're only 660 * changing ref-counters here. 661 */ 662 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); 663 drm_gem_vram_vunmap(gbo, src); 664 665 return 0; 666 667 err_drm_gem_vram_vunmap_dst: 668 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); 669 err_drm_gem_vram_vunmap_src: 670 drm_gem_vram_vunmap(gbo, src); 671 err_drm_gem_vram_unpin: 672 drm_gem_vram_unpin(gbo); 673 return ret; 674 } 675 676 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, 677 struct drm_plane_state *state) 678 { 679 struct drm_framebuffer *fb = state->fb; 680 struct drm_crtc_state *crtc_state; 681 int ret; 682 683 if (!state->crtc) 684 return 0; 685 686 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 687 688 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 689 DRM_PLANE_HELPER_NO_SCALING, 690 DRM_PLANE_HELPER_NO_SCALING, 691 true, true); 692 if (ret) 693 return ret; 694 695 if (!state->visible) 696 return 0; 697 698 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) 699 return -EINVAL; 700 701 return 0; 702 } 703 704 static void 705 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, 706 struct drm_plane_state *old_state) 707 { 708 struct drm_device *dev = plane->dev; 709 struct drm_plane_state *state = plane->state; 710 struct drm_crtc *crtc = state->crtc; 711 struct drm_framebuffer *fb = state->fb; 712 struct ast_private *ast = to_ast_private(plane->dev); 713 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 714 struct drm_gem_vram_object *gbo; 715 s64 off; 716 u8 jreg; 717 718 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - fb->width; 719 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - fb->height; 720 721 if (state->fb != old_state->fb) { 722 /* A new cursor image was installed. */ 723 gbo = ast->cursor.gbo[ast->cursor.next_index]; 724 off = drm_gem_vram_offset(gbo); 725 if (drm_WARN_ON_ONCE(dev, off < 0)) 726 return; /* Bug: we didn't pin cursor HW BO to VRAM. */ 727 ast_cursor_set_base(ast, off); 728 729 ++ast->cursor.next_index; 730 ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo); 731 } 732 733 ast_cursor_move(crtc, state->crtc_x, state->crtc_y); 734 735 jreg = 0x2; 736 /* enable ARGB cursor */ 737 jreg |= 1; 738 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 739 } 740 741 static void 742 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, 743 struct drm_plane_state *old_state) 744 { 745 struct ast_private *ast = to_ast_private(plane->dev); 746 747 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 748 } 749 750 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = { 751 .prepare_fb = ast_cursor_plane_helper_prepare_fb, 752 .cleanup_fb = NULL, /* not required for cursor plane */ 753 .atomic_check = ast_cursor_plane_helper_atomic_check, 754 .atomic_update = ast_cursor_plane_helper_atomic_update, 755 .atomic_disable = ast_cursor_plane_helper_atomic_disable, 756 }; 757 758 static const struct drm_plane_funcs ast_cursor_plane_funcs = { 759 .update_plane = drm_atomic_helper_update_plane, 760 .disable_plane = drm_atomic_helper_disable_plane, 761 .destroy = drm_plane_cleanup, 762 .reset = drm_atomic_helper_plane_reset, 763 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 764 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 765 }; 766 767 /* 768 * CRTC 769 */ 770 771 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 772 { 773 struct ast_private *ast = to_ast_private(crtc->dev); 774 775 /* TODO: Maybe control display signal generation with 776 * Sync Enable (bit CR17.7). 777 */ 778 switch (mode) { 779 case DRM_MODE_DPMS_ON: 780 case DRM_MODE_DPMS_STANDBY: 781 case DRM_MODE_DPMS_SUSPEND: 782 if (ast->tx_chip_type == AST_TX_DP501) 783 ast_set_dp501_video_output(crtc->dev, 1); 784 ast_crtc_load_lut(ast, crtc); 785 break; 786 case DRM_MODE_DPMS_OFF: 787 if (ast->tx_chip_type == AST_TX_DP501) 788 ast_set_dp501_video_output(crtc->dev, 0); 789 break; 790 } 791 } 792 793 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, 794 struct drm_crtc_state *state) 795 { 796 struct ast_crtc_state *ast_state; 797 const struct drm_format_info *format; 798 bool succ; 799 800 if (!state->enable) 801 return 0; /* no mode checks if CRTC is being disabled */ 802 803 ast_state = to_ast_crtc_state(state); 804 805 format = ast_state->format; 806 if (!format) 807 return 0; 808 809 succ = ast_get_vbios_mode_info(format, &state->mode, 810 &state->adjusted_mode, 811 &ast_state->vbios_mode_info); 812 if (!succ) 813 return -EINVAL; 814 815 return 0; 816 } 817 818 static void ast_crtc_helper_atomic_begin(struct drm_crtc *crtc, 819 struct drm_crtc_state *old_crtc_state) 820 { 821 struct ast_private *ast = to_ast_private(crtc->dev); 822 823 ast_open_key(ast); 824 } 825 826 static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, 827 struct drm_crtc_state *old_crtc_state) 828 { 829 struct drm_device *dev = crtc->dev; 830 struct ast_private *ast = to_ast_private(dev); 831 struct ast_crtc_state *ast_state; 832 const struct drm_format_info *format; 833 struct ast_vbios_mode_info *vbios_mode_info; 834 struct drm_display_mode *adjusted_mode; 835 836 ast_state = to_ast_crtc_state(crtc->state); 837 838 format = ast_state->format; 839 if (!format) 840 return; 841 842 vbios_mode_info = &ast_state->vbios_mode_info; 843 844 ast_set_color_reg(ast, format); 845 ast_set_vbios_color_reg(ast, format, vbios_mode_info); 846 847 if (!crtc->state->mode_changed) 848 return; 849 850 adjusted_mode = &crtc->state->adjusted_mode; 851 852 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info); 853 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); 854 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info); 855 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info); 856 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info); 857 ast_set_crtthd_reg(ast); 858 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info); 859 } 860 861 static void 862 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, 863 struct drm_crtc_state *old_crtc_state) 864 { 865 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 866 } 867 868 static void 869 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, 870 struct drm_crtc_state *old_crtc_state) 871 { 872 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 873 } 874 875 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 876 .atomic_check = ast_crtc_helper_atomic_check, 877 .atomic_begin = ast_crtc_helper_atomic_begin, 878 .atomic_flush = ast_crtc_helper_atomic_flush, 879 .atomic_enable = ast_crtc_helper_atomic_enable, 880 .atomic_disable = ast_crtc_helper_atomic_disable, 881 }; 882 883 static void ast_crtc_reset(struct drm_crtc *crtc) 884 { 885 struct ast_crtc_state *ast_state = 886 kzalloc(sizeof(*ast_state), GFP_KERNEL); 887 888 if (crtc->state) 889 crtc->funcs->atomic_destroy_state(crtc, crtc->state); 890 891 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base); 892 } 893 894 static void ast_crtc_destroy(struct drm_crtc *crtc) 895 { 896 drm_crtc_cleanup(crtc); 897 kfree(crtc); 898 } 899 900 static struct drm_crtc_state * 901 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 902 { 903 struct ast_crtc_state *new_ast_state, *ast_state; 904 struct drm_device *dev = crtc->dev; 905 906 if (drm_WARN_ON(dev, !crtc->state)) 907 return NULL; 908 909 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL); 910 if (!new_ast_state) 911 return NULL; 912 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base); 913 914 ast_state = to_ast_crtc_state(crtc->state); 915 916 new_ast_state->format = ast_state->format; 917 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info, 918 sizeof(new_ast_state->vbios_mode_info)); 919 920 return &new_ast_state->base; 921 } 922 923 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc, 924 struct drm_crtc_state *state) 925 { 926 struct ast_crtc_state *ast_state = to_ast_crtc_state(state); 927 928 __drm_atomic_helper_crtc_destroy_state(&ast_state->base); 929 kfree(ast_state); 930 } 931 932 static const struct drm_crtc_funcs ast_crtc_funcs = { 933 .reset = ast_crtc_reset, 934 .gamma_set = drm_atomic_helper_legacy_gamma_set, 935 .destroy = ast_crtc_destroy, 936 .set_config = drm_atomic_helper_set_config, 937 .page_flip = drm_atomic_helper_page_flip, 938 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state, 939 .atomic_destroy_state = ast_crtc_atomic_destroy_state, 940 }; 941 942 static int ast_crtc_init(struct drm_device *dev) 943 { 944 struct ast_private *ast = to_ast_private(dev); 945 struct ast_crtc *crtc; 946 int ret; 947 948 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 949 if (!crtc) 950 return -ENOMEM; 951 952 ret = drm_crtc_init_with_planes(dev, &crtc->base, &ast->primary_plane, 953 &ast->cursor_plane, &ast_crtc_funcs, 954 NULL); 955 if (ret) 956 goto err_kfree; 957 958 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 959 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 960 return 0; 961 962 err_kfree: 963 kfree(crtc); 964 return ret; 965 } 966 967 /* 968 * Encoder 969 */ 970 971 static int ast_encoder_init(struct drm_device *dev) 972 { 973 struct ast_private *ast = to_ast_private(dev); 974 struct drm_encoder *encoder = &ast->encoder; 975 int ret; 976 977 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC); 978 if (ret) 979 return ret; 980 981 encoder->possible_crtcs = 1; 982 983 return 0; 984 } 985 986 /* 987 * Connector 988 */ 989 990 static int ast_get_modes(struct drm_connector *connector) 991 { 992 struct ast_connector *ast_connector = to_ast_connector(connector); 993 struct ast_private *ast = to_ast_private(connector->dev); 994 struct edid *edid; 995 int ret; 996 bool flags = false; 997 if (ast->tx_chip_type == AST_TX_DP501) { 998 ast->dp501_maxclk = 0xff; 999 edid = kmalloc(128, GFP_KERNEL); 1000 if (!edid) 1001 return -ENOMEM; 1002 1003 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 1004 if (flags) 1005 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 1006 else 1007 kfree(edid); 1008 } 1009 if (!flags) 1010 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 1011 if (edid) { 1012 drm_connector_update_edid_property(&ast_connector->base, edid); 1013 ret = drm_add_edid_modes(connector, edid); 1014 kfree(edid); 1015 return ret; 1016 } else 1017 drm_connector_update_edid_property(&ast_connector->base, NULL); 1018 return 0; 1019 } 1020 1021 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, 1022 struct drm_display_mode *mode) 1023 { 1024 struct ast_private *ast = to_ast_private(connector->dev); 1025 int flags = MODE_NOMODE; 1026 uint32_t jtemp; 1027 1028 if (ast->support_wide_screen) { 1029 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 1030 return MODE_OK; 1031 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 1032 return MODE_OK; 1033 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 1034 return MODE_OK; 1035 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 1036 return MODE_OK; 1037 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 1038 return MODE_OK; 1039 1040 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 1041 (ast->chip == AST2300) || (ast->chip == AST2400) || 1042 (ast->chip == AST2500)) { 1043 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 1044 return MODE_OK; 1045 1046 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 1047 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 1048 if (jtemp & 0x01) 1049 return MODE_NOMODE; 1050 else 1051 return MODE_OK; 1052 } 1053 } 1054 } 1055 switch (mode->hdisplay) { 1056 case 640: 1057 if (mode->vdisplay == 480) flags = MODE_OK; 1058 break; 1059 case 800: 1060 if (mode->vdisplay == 600) flags = MODE_OK; 1061 break; 1062 case 1024: 1063 if (mode->vdisplay == 768) flags = MODE_OK; 1064 break; 1065 case 1280: 1066 if (mode->vdisplay == 1024) flags = MODE_OK; 1067 break; 1068 case 1600: 1069 if (mode->vdisplay == 1200) flags = MODE_OK; 1070 break; 1071 default: 1072 return flags; 1073 } 1074 1075 return flags; 1076 } 1077 1078 static void ast_connector_destroy(struct drm_connector *connector) 1079 { 1080 struct ast_connector *ast_connector = to_ast_connector(connector); 1081 ast_i2c_destroy(ast_connector->i2c); 1082 drm_connector_cleanup(connector); 1083 kfree(connector); 1084 } 1085 1086 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 1087 .get_modes = ast_get_modes, 1088 .mode_valid = ast_mode_valid, 1089 }; 1090 1091 static const struct drm_connector_funcs ast_connector_funcs = { 1092 .reset = drm_atomic_helper_connector_reset, 1093 .fill_modes = drm_helper_probe_single_connector_modes, 1094 .destroy = ast_connector_destroy, 1095 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1096 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1097 }; 1098 1099 static int ast_connector_init(struct drm_device *dev) 1100 { 1101 struct ast_connector *ast_connector; 1102 struct drm_connector *connector; 1103 struct drm_encoder *encoder; 1104 1105 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 1106 if (!ast_connector) 1107 return -ENOMEM; 1108 1109 connector = &ast_connector->base; 1110 ast_connector->i2c = ast_i2c_create(dev); 1111 if (!ast_connector->i2c) 1112 drm_err(dev, "failed to add ddc bus for connector\n"); 1113 1114 drm_connector_init_with_ddc(dev, connector, 1115 &ast_connector_funcs, 1116 DRM_MODE_CONNECTOR_VGA, 1117 &ast_connector->i2c->adapter); 1118 1119 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 1120 1121 connector->interlace_allowed = 0; 1122 connector->doublescan_allowed = 0; 1123 1124 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1125 1126 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 1127 drm_connector_attach_encoder(connector, encoder); 1128 1129 return 0; 1130 } 1131 1132 /* allocate cursor cache and pin at start of VRAM */ 1133 static int ast_cursor_init(struct drm_device *dev) 1134 { 1135 struct ast_private *ast = to_ast_private(dev); 1136 size_t size, i; 1137 struct drm_gem_vram_object *gbo; 1138 int ret; 1139 1140 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE); 1141 1142 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { 1143 gbo = drm_gem_vram_create(dev, size, 0); 1144 if (IS_ERR(gbo)) { 1145 ret = PTR_ERR(gbo); 1146 goto err_drm_gem_vram_put; 1147 } 1148 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM | 1149 DRM_GEM_VRAM_PL_FLAG_TOPDOWN); 1150 if (ret) { 1151 drm_gem_vram_put(gbo); 1152 goto err_drm_gem_vram_put; 1153 } 1154 1155 ast->cursor.gbo[i] = gbo; 1156 } 1157 1158 return 0; 1159 1160 err_drm_gem_vram_put: 1161 while (i) { 1162 --i; 1163 gbo = ast->cursor.gbo[i]; 1164 drm_gem_vram_unpin(gbo); 1165 drm_gem_vram_put(gbo); 1166 ast->cursor.gbo[i] = NULL; 1167 } 1168 return ret; 1169 } 1170 1171 static void ast_cursor_fini(struct drm_device *dev) 1172 { 1173 struct ast_private *ast = to_ast_private(dev); 1174 size_t i; 1175 struct drm_gem_vram_object *gbo; 1176 1177 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { 1178 gbo = ast->cursor.gbo[i]; 1179 drm_gem_vram_unpin(gbo); 1180 drm_gem_vram_put(gbo); 1181 } 1182 } 1183 1184 int ast_mode_init(struct drm_device *dev) 1185 { 1186 struct ast_private *ast = to_ast_private(dev); 1187 int ret; 1188 1189 memset(&ast->primary_plane, 0, sizeof(ast->primary_plane)); 1190 ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01, 1191 &ast_primary_plane_funcs, 1192 ast_primary_plane_formats, 1193 ARRAY_SIZE(ast_primary_plane_formats), 1194 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1195 if (ret) { 1196 drm_err(dev, "ast: drm_universal_plane_init() failed: %d\n", ret); 1197 return ret; 1198 } 1199 drm_plane_helper_add(&ast->primary_plane, 1200 &ast_primary_plane_helper_funcs); 1201 1202 ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01, 1203 &ast_cursor_plane_funcs, 1204 ast_cursor_plane_formats, 1205 ARRAY_SIZE(ast_cursor_plane_formats), 1206 NULL, DRM_PLANE_TYPE_CURSOR, NULL); 1207 if (ret) { 1208 drm_err(dev, "drm_universal_plane_failed(): %d\n", ret); 1209 return ret; 1210 } 1211 drm_plane_helper_add(&ast->cursor_plane, 1212 &ast_cursor_plane_helper_funcs); 1213 1214 ast_cursor_init(dev); 1215 ast_crtc_init(dev); 1216 ast_encoder_init(dev); 1217 ast_connector_init(dev); 1218 1219 return 0; 1220 } 1221 1222 void ast_mode_fini(struct drm_device *dev) 1223 { 1224 ast_cursor_fini(dev); 1225 } 1226 1227 static int get_clock(void *i2c_priv) 1228 { 1229 struct ast_i2c_chan *i2c = i2c_priv; 1230 struct ast_private *ast = to_ast_private(i2c->dev); 1231 uint32_t val, val2, count, pass; 1232 1233 count = 0; 1234 pass = 0; 1235 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1236 do { 1237 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1238 if (val == val2) { 1239 pass++; 1240 } else { 1241 pass = 0; 1242 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1243 } 1244 } while ((pass < 5) && (count++ < 0x10000)); 1245 1246 return val & 1 ? 1 : 0; 1247 } 1248 1249 static int get_data(void *i2c_priv) 1250 { 1251 struct ast_i2c_chan *i2c = i2c_priv; 1252 struct ast_private *ast = to_ast_private(i2c->dev); 1253 uint32_t val, val2, count, pass; 1254 1255 count = 0; 1256 pass = 0; 1257 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1258 do { 1259 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1260 if (val == val2) { 1261 pass++; 1262 } else { 1263 pass = 0; 1264 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1265 } 1266 } while ((pass < 5) && (count++ < 0x10000)); 1267 1268 return val & 1 ? 1 : 0; 1269 } 1270 1271 static void set_clock(void *i2c_priv, int clock) 1272 { 1273 struct ast_i2c_chan *i2c = i2c_priv; 1274 struct ast_private *ast = to_ast_private(i2c->dev); 1275 int i; 1276 u8 ujcrb7, jtemp; 1277 1278 for (i = 0; i < 0x10000; i++) { 1279 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1280 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); 1281 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1282 if (ujcrb7 == jtemp) 1283 break; 1284 } 1285 } 1286 1287 static void set_data(void *i2c_priv, int data) 1288 { 1289 struct ast_i2c_chan *i2c = i2c_priv; 1290 struct ast_private *ast = to_ast_private(i2c->dev); 1291 int i; 1292 u8 ujcrb7, jtemp; 1293 1294 for (i = 0; i < 0x10000; i++) { 1295 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1296 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); 1297 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1298 if (ujcrb7 == jtemp) 1299 break; 1300 } 1301 } 1302 1303 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1304 { 1305 struct ast_i2c_chan *i2c; 1306 int ret; 1307 1308 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1309 if (!i2c) 1310 return NULL; 1311 1312 i2c->adapter.owner = THIS_MODULE; 1313 i2c->adapter.class = I2C_CLASS_DDC; 1314 i2c->adapter.dev.parent = &dev->pdev->dev; 1315 i2c->dev = dev; 1316 i2c_set_adapdata(&i2c->adapter, i2c); 1317 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1318 "AST i2c bit bus"); 1319 i2c->adapter.algo_data = &i2c->bit; 1320 1321 i2c->bit.udelay = 20; 1322 i2c->bit.timeout = 2; 1323 i2c->bit.data = i2c; 1324 i2c->bit.setsda = set_data; 1325 i2c->bit.setscl = set_clock; 1326 i2c->bit.getsda = get_data; 1327 i2c->bit.getscl = get_clock; 1328 ret = i2c_bit_add_bus(&i2c->adapter); 1329 if (ret) { 1330 drm_err(dev, "Failed to register bit i2c\n"); 1331 goto out_free; 1332 } 1333 1334 return i2c; 1335 out_free: 1336 kfree(i2c); 1337 return NULL; 1338 } 1339 1340 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1341 { 1342 if (!i2c) 1343 return; 1344 i2c_del_adapter(&i2c->adapter); 1345 kfree(i2c); 1346 } 1347 1348 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1349 { 1350 union { 1351 u32 ul; 1352 u8 b[4]; 1353 } srcdata32[2], data32; 1354 union { 1355 u16 us; 1356 u8 b[2]; 1357 } data16; 1358 u32 csum = 0; 1359 s32 alpha_dst_delta, last_alpha_dst_delta; 1360 u8 *srcxor, *dstxor; 1361 int i, j; 1362 u32 per_pixel_copy, two_pixel_copy; 1363 1364 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1365 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1366 1367 srcxor = src; 1368 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1369 per_pixel_copy = width & 1; 1370 two_pixel_copy = width >> 1; 1371 1372 for (j = 0; j < height; j++) { 1373 for (i = 0; i < two_pixel_copy; i++) { 1374 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1375 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1376 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1377 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1378 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1379 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1380 1381 writel(data32.ul, dstxor); 1382 csum += data32.ul; 1383 1384 dstxor += 4; 1385 srcxor += 8; 1386 1387 } 1388 1389 for (i = 0; i < per_pixel_copy; i++) { 1390 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1391 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1392 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1393 writew(data16.us, dstxor); 1394 csum += (u32)data16.us; 1395 1396 dstxor += 2; 1397 srcxor += 4; 1398 } 1399 dstxor += last_alpha_dst_delta; 1400 } 1401 return csum; 1402 } 1403 1404 static int ast_cursor_update(void *dst, void *src, unsigned int width, 1405 unsigned int height) 1406 { 1407 u32 csum; 1408 1409 /* do data transfer to cursor cache */ 1410 csum = copy_cursor_image(src, dst, width, height); 1411 1412 /* write checksum + signature */ 1413 dst += AST_HWC_SIZE; 1414 writel(csum, dst); 1415 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1416 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1417 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1418 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1419 1420 return 0; 1421 } 1422 1423 static void ast_cursor_set_base(struct ast_private *ast, u64 address) 1424 { 1425 u8 addr0 = (address >> 3) & 0xff; 1426 u8 addr1 = (address >> 11) & 0xff; 1427 u8 addr2 = (address >> 19) & 0xff; 1428 1429 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); 1430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); 1431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); 1432 } 1433 1434 static int ast_cursor_move(struct drm_crtc *crtc, 1435 int x, int y) 1436 { 1437 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1438 struct ast_private *ast = to_ast_private(crtc->dev); 1439 struct drm_gem_vram_object *gbo; 1440 int x_offset, y_offset; 1441 u8 *dst, *sig; 1442 u8 jreg; 1443 1444 gbo = ast->cursor.gbo[ast->cursor.next_index]; 1445 dst = drm_gem_vram_vmap(gbo); 1446 if (IS_ERR(dst)) 1447 return PTR_ERR(dst); 1448 1449 sig = dst + AST_HWC_SIZE; 1450 writel(x, sig + AST_HWC_SIGNATURE_X); 1451 writel(y, sig + AST_HWC_SIGNATURE_Y); 1452 1453 x_offset = ast_crtc->offset_x; 1454 y_offset = ast_crtc->offset_y; 1455 if (x < 0) { 1456 x_offset = (-x) + ast_crtc->offset_x; 1457 x = 0; 1458 } 1459 1460 if (y < 0) { 1461 y_offset = (-y) + ast_crtc->offset_y; 1462 y = 0; 1463 } 1464 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1465 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1466 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1467 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1468 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1469 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1470 1471 /* dummy write to fire HWC */ 1472 jreg = 0x02 | 1473 0x01; /* enable ARGB4444 cursor */ 1474 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1475 1476 drm_gem_vram_vunmap(gbo, dst); 1477 1478 return 0; 1479 } 1480