1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include "ast_drv.h" 36 37 #include "ast_tables.h" 38 39 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 40 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 41 static int ast_cursor_set(struct drm_crtc *crtc, 42 struct drm_file *file_priv, 43 uint32_t handle, 44 uint32_t width, 45 uint32_t height); 46 static int ast_cursor_move(struct drm_crtc *crtc, 47 int x, int y); 48 49 static inline void ast_load_palette_index(struct ast_private *ast, 50 u8 index, u8 red, u8 green, 51 u8 blue) 52 { 53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 54 ast_io_read8(ast, AST_IO_SEQ_PORT); 55 ast_io_write8(ast, AST_IO_DAC_DATA, red); 56 ast_io_read8(ast, AST_IO_SEQ_PORT); 57 ast_io_write8(ast, AST_IO_DAC_DATA, green); 58 ast_io_read8(ast, AST_IO_SEQ_PORT); 59 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 60 ast_io_read8(ast, AST_IO_SEQ_PORT); 61 } 62 63 static void ast_crtc_load_lut(struct drm_crtc *crtc) 64 { 65 struct ast_private *ast = crtc->dev->dev_private; 66 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 67 int i; 68 69 if (!crtc->enabled) 70 return; 71 72 for (i = 0; i < 256; i++) 73 ast_load_palette_index(ast, i, ast_crtc->lut_r[i], 74 ast_crtc->lut_g[i], ast_crtc->lut_b[i]); 75 } 76 77 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, 78 struct drm_display_mode *adjusted_mode, 79 struct ast_vbios_mode_info *vbios_mode) 80 { 81 struct ast_private *ast = crtc->dev->dev_private; 82 const struct drm_framebuffer *fb = crtc->primary->fb; 83 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; 84 const struct ast_vbios_enhtable *best = NULL; 85 u32 hborder, vborder; 86 bool check_sync; 87 88 switch (fb->format->cpp[0] * 8) { 89 case 8: 90 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 91 color_index = VGAModeIndex - 1; 92 break; 93 case 16: 94 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 95 color_index = HiCModeIndex; 96 break; 97 case 24: 98 case 32: 99 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 100 color_index = TrueCModeIndex; 101 break; 102 default: 103 return false; 104 } 105 106 switch (crtc->mode.crtc_hdisplay) { 107 case 640: 108 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 109 break; 110 case 800: 111 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 112 break; 113 case 1024: 114 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 115 break; 116 case 1280: 117 if (crtc->mode.crtc_vdisplay == 800) 118 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 119 else 120 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 121 break; 122 case 1360: 123 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 124 break; 125 case 1440: 126 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 127 break; 128 case 1600: 129 if (crtc->mode.crtc_vdisplay == 900) 130 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 131 else 132 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 133 break; 134 case 1680: 135 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 136 break; 137 case 1920: 138 if (crtc->mode.crtc_vdisplay == 1080) 139 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 140 else 141 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 142 break; 143 default: 144 return false; 145 } 146 147 refresh_rate = drm_mode_vrefresh(mode); 148 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 149 do { 150 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 151 152 while (loop->refresh_rate != 0xff) { 153 if ((check_sync) && 154 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 155 (loop->flags & PVSync)) || 156 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 157 (loop->flags & NVSync)) || 158 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 159 (loop->flags & PHSync)) || 160 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 161 (loop->flags & NHSync)))) { 162 loop++; 163 continue; 164 } 165 if (loop->refresh_rate <= refresh_rate 166 && (!best || loop->refresh_rate > best->refresh_rate)) 167 best = loop; 168 loop++; 169 } 170 if (best || !check_sync) 171 break; 172 check_sync = 0; 173 } while (1); 174 if (best) 175 vbios_mode->enh_table = best; 176 177 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 178 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 179 180 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 181 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 182 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 183 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 184 vbios_mode->enh_table->hfp; 185 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 186 vbios_mode->enh_table->hfp + 187 vbios_mode->enh_table->hsync); 188 189 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 190 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 191 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 192 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 193 vbios_mode->enh_table->vfp; 194 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 195 vbios_mode->enh_table->vfp + 196 vbios_mode->enh_table->vsync); 197 198 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 199 mode_id = vbios_mode->enh_table->mode_id; 200 201 if (ast->chip == AST1180) { 202 /* TODO 1180 */ 203 } else { 204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); 205 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 206 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 207 208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 209 if (vbios_mode->enh_table->flags & NewModeInfo) { 210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, 212 fb->format->cpp[0] * 8); 213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 216 217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 219 } 220 } 221 222 return true; 223 224 225 } 226 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 227 struct ast_vbios_mode_info *vbios_mode) 228 { 229 struct ast_private *ast = crtc->dev->dev_private; 230 const struct ast_vbios_stdtable *stdtable; 231 u32 i; 232 u8 jreg; 233 234 stdtable = vbios_mode->std_table; 235 236 jreg = stdtable->misc; 237 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 238 239 /* Set SEQ */ 240 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 241 for (i = 0; i < 4; i++) { 242 jreg = stdtable->seq[i]; 243 if (!i) 244 jreg |= 0x20; 245 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 246 } 247 248 /* Set CRTC */ 249 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 250 for (i = 0; i < 25; i++) 251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 252 253 /* set AR */ 254 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 255 for (i = 0; i < 20; i++) { 256 jreg = stdtable->ar[i]; 257 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 258 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 259 } 260 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 262 263 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 265 266 /* Set GR */ 267 for (i = 0; i < 9; i++) 268 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 269 } 270 271 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 272 struct ast_vbios_mode_info *vbios_mode) 273 { 274 struct ast_private *ast = crtc->dev->dev_private; 275 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 276 u16 temp, precache = 0; 277 278 if ((ast->chip == AST2500) && 279 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 280 precache = 40; 281 282 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 283 284 temp = (mode->crtc_htotal >> 3) - 5; 285 if (temp & 0x100) 286 jregAC |= 0x01; /* HT D[8] */ 287 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 288 289 temp = (mode->crtc_hdisplay >> 3) - 1; 290 if (temp & 0x100) 291 jregAC |= 0x04; /* HDE D[8] */ 292 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 293 294 temp = (mode->crtc_hblank_start >> 3) - 1; 295 if (temp & 0x100) 296 jregAC |= 0x10; /* HBS D[8] */ 297 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 298 299 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 300 if (temp & 0x20) 301 jreg05 |= 0x80; /* HBE D[5] */ 302 if (temp & 0x40) 303 jregAD |= 0x01; /* HBE D[5] */ 304 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 305 306 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 307 if (temp & 0x100) 308 jregAC |= 0x40; /* HRS D[5] */ 309 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 310 311 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 312 if (temp & 0x20) 313 jregAD |= 0x04; /* HRE D[5] */ 314 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 315 316 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 317 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 318 319 /* vert timings */ 320 temp = (mode->crtc_vtotal) - 2; 321 if (temp & 0x100) 322 jreg07 |= 0x01; 323 if (temp & 0x200) 324 jreg07 |= 0x20; 325 if (temp & 0x400) 326 jregAE |= 0x01; 327 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 328 329 temp = (mode->crtc_vsync_start) - 1; 330 if (temp & 0x100) 331 jreg07 |= 0x04; 332 if (temp & 0x200) 333 jreg07 |= 0x80; 334 if (temp & 0x400) 335 jregAE |= 0x08; 336 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 337 338 temp = (mode->crtc_vsync_end - 1) & 0x3f; 339 if (temp & 0x10) 340 jregAE |= 0x20; 341 if (temp & 0x20) 342 jregAE |= 0x40; 343 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 344 345 temp = mode->crtc_vdisplay - 1; 346 if (temp & 0x100) 347 jreg07 |= 0x02; 348 if (temp & 0x200) 349 jreg07 |= 0x40; 350 if (temp & 0x400) 351 jregAE |= 0x02; 352 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 353 354 temp = mode->crtc_vblank_start - 1; 355 if (temp & 0x100) 356 jreg07 |= 0x08; 357 if (temp & 0x200) 358 jreg09 |= 0x20; 359 if (temp & 0x400) 360 jregAE |= 0x04; 361 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 362 363 temp = mode->crtc_vblank_end - 1; 364 if (temp & 0x100) 365 jregAE |= 0x10; 366 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 367 368 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 369 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 370 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 371 372 if (precache) 373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 374 else 375 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 376 377 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 378 } 379 380 static void ast_set_offset_reg(struct drm_crtc *crtc) 381 { 382 struct ast_private *ast = crtc->dev->dev_private; 383 const struct drm_framebuffer *fb = crtc->primary->fb; 384 385 u16 offset; 386 387 offset = fb->pitches[0] >> 3; 388 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 389 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 390 } 391 392 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, 393 struct ast_vbios_mode_info *vbios_mode) 394 { 395 struct ast_private *ast = dev->dev_private; 396 const struct ast_vbios_dclk_info *clk_info; 397 398 if (ast->chip == AST2500) 399 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 400 else 401 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 402 403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 404 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 406 (clk_info->param3 & 0xc0) | 407 ((clk_info->param3 & 0x3) << 4)); 408 } 409 410 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 411 struct ast_vbios_mode_info *vbios_mode) 412 { 413 struct ast_private *ast = crtc->dev->dev_private; 414 const struct drm_framebuffer *fb = crtc->primary->fb; 415 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 416 417 switch (fb->format->cpp[0] * 8) { 418 case 8: 419 jregA0 = 0x70; 420 jregA3 = 0x01; 421 jregA8 = 0x00; 422 break; 423 case 15: 424 case 16: 425 jregA0 = 0x70; 426 jregA3 = 0x04; 427 jregA8 = 0x02; 428 break; 429 case 32: 430 jregA0 = 0x70; 431 jregA3 = 0x08; 432 jregA8 = 0x02; 433 break; 434 } 435 436 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 437 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 438 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 439 440 /* Set Threshold */ 441 if (ast->chip == AST2300 || ast->chip == AST2400 || 442 ast->chip == AST2500) { 443 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 444 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 445 } else if (ast->chip == AST2100 || 446 ast->chip == AST1100 || 447 ast->chip == AST2200 || 448 ast->chip == AST2150) { 449 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 450 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 451 } else { 452 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 453 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 454 } 455 } 456 457 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, 458 struct ast_vbios_mode_info *vbios_mode) 459 { 460 struct ast_private *ast = dev->dev_private; 461 u8 jreg; 462 463 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 464 jreg &= ~0xC0; 465 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 466 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 467 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 468 } 469 470 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 471 struct ast_vbios_mode_info *vbios_mode) 472 { 473 const struct drm_framebuffer *fb = crtc->primary->fb; 474 475 switch (fb->format->cpp[0] * 8) { 476 case 8: 477 break; 478 default: 479 return false; 480 } 481 return true; 482 } 483 484 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset) 485 { 486 struct ast_private *ast = crtc->dev->dev_private; 487 u32 addr; 488 489 addr = offset >> 2; 490 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 491 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 492 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 493 494 } 495 496 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 497 { 498 struct ast_private *ast = crtc->dev->dev_private; 499 500 if (ast->chip == AST1180) 501 return; 502 503 switch (mode) { 504 case DRM_MODE_DPMS_ON: 505 case DRM_MODE_DPMS_STANDBY: 506 case DRM_MODE_DPMS_SUSPEND: 507 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 508 if (ast->tx_chip_type == AST_TX_DP501) 509 ast_set_dp501_video_output(crtc->dev, 1); 510 ast_crtc_load_lut(crtc); 511 break; 512 case DRM_MODE_DPMS_OFF: 513 if (ast->tx_chip_type == AST_TX_DP501) 514 ast_set_dp501_video_output(crtc->dev, 0); 515 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 516 break; 517 } 518 } 519 520 /* ast is different - we will force move buffers out of VRAM */ 521 static int ast_crtc_do_set_base(struct drm_crtc *crtc, 522 struct drm_framebuffer *fb, 523 int x, int y, int atomic) 524 { 525 struct ast_private *ast = crtc->dev->dev_private; 526 struct drm_gem_object *obj; 527 struct ast_framebuffer *ast_fb; 528 struct ast_bo *bo; 529 int ret; 530 u64 gpu_addr; 531 532 /* push the previous fb to system ram */ 533 if (!atomic && fb) { 534 ast_fb = to_ast_framebuffer(fb); 535 obj = ast_fb->obj; 536 bo = gem_to_ast_bo(obj); 537 ret = ast_bo_reserve(bo, false); 538 if (ret) 539 return ret; 540 ast_bo_push_sysram(bo); 541 ast_bo_unreserve(bo); 542 } 543 544 ast_fb = to_ast_framebuffer(crtc->primary->fb); 545 obj = ast_fb->obj; 546 bo = gem_to_ast_bo(obj); 547 548 ret = ast_bo_reserve(bo, false); 549 if (ret) 550 return ret; 551 552 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 553 if (ret) { 554 ast_bo_unreserve(bo); 555 return ret; 556 } 557 558 if (&ast->fbdev->afb == ast_fb) { 559 /* if pushing console in kmap it */ 560 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 561 if (ret) 562 DRM_ERROR("failed to kmap fbcon\n"); 563 else 564 ast_fbdev_set_base(ast, gpu_addr); 565 } 566 ast_bo_unreserve(bo); 567 568 ast_set_start_address_crt1(crtc, (u32)gpu_addr); 569 570 return 0; 571 } 572 573 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 574 struct drm_framebuffer *old_fb) 575 { 576 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0); 577 } 578 579 static int ast_crtc_mode_set(struct drm_crtc *crtc, 580 struct drm_display_mode *mode, 581 struct drm_display_mode *adjusted_mode, 582 int x, int y, 583 struct drm_framebuffer *old_fb) 584 { 585 struct drm_device *dev = crtc->dev; 586 struct ast_private *ast = crtc->dev->dev_private; 587 struct ast_vbios_mode_info vbios_mode; 588 bool ret; 589 if (ast->chip == AST1180) { 590 DRM_ERROR("AST 1180 modesetting not supported\n"); 591 return -EINVAL; 592 } 593 594 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); 595 if (ret == false) 596 return -EINVAL; 597 ast_open_key(ast); 598 599 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); 600 601 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); 602 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); 603 ast_set_offset_reg(crtc); 604 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); 605 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); 606 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); 607 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode); 608 609 ast_crtc_mode_set_base(crtc, x, y, old_fb); 610 611 return 0; 612 } 613 614 static void ast_crtc_disable(struct drm_crtc *crtc) 615 { 616 617 } 618 619 static void ast_crtc_prepare(struct drm_crtc *crtc) 620 { 621 622 } 623 624 static void ast_crtc_commit(struct drm_crtc *crtc) 625 { 626 struct ast_private *ast = crtc->dev->dev_private; 627 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 628 } 629 630 631 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 632 .dpms = ast_crtc_dpms, 633 .mode_set = ast_crtc_mode_set, 634 .mode_set_base = ast_crtc_mode_set_base, 635 .disable = ast_crtc_disable, 636 .load_lut = ast_crtc_load_lut, 637 .prepare = ast_crtc_prepare, 638 .commit = ast_crtc_commit, 639 640 }; 641 642 static void ast_crtc_reset(struct drm_crtc *crtc) 643 { 644 645 } 646 647 static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 648 u16 *blue, uint32_t size) 649 { 650 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 651 int i; 652 653 /* userspace palettes are always correct as is */ 654 for (i = 0; i < size; i++) { 655 ast_crtc->lut_r[i] = red[i] >> 8; 656 ast_crtc->lut_g[i] = green[i] >> 8; 657 ast_crtc->lut_b[i] = blue[i] >> 8; 658 } 659 ast_crtc_load_lut(crtc); 660 661 return 0; 662 } 663 664 665 static void ast_crtc_destroy(struct drm_crtc *crtc) 666 { 667 drm_crtc_cleanup(crtc); 668 kfree(crtc); 669 } 670 671 static const struct drm_crtc_funcs ast_crtc_funcs = { 672 .cursor_set = ast_cursor_set, 673 .cursor_move = ast_cursor_move, 674 .reset = ast_crtc_reset, 675 .set_config = drm_crtc_helper_set_config, 676 .gamma_set = ast_crtc_gamma_set, 677 .destroy = ast_crtc_destroy, 678 }; 679 680 static int ast_crtc_init(struct drm_device *dev) 681 { 682 struct ast_crtc *crtc; 683 int i; 684 685 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 686 if (!crtc) 687 return -ENOMEM; 688 689 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); 690 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 691 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 692 693 for (i = 0; i < 256; i++) { 694 crtc->lut_r[i] = i; 695 crtc->lut_g[i] = i; 696 crtc->lut_b[i] = i; 697 } 698 return 0; 699 } 700 701 static void ast_encoder_destroy(struct drm_encoder *encoder) 702 { 703 drm_encoder_cleanup(encoder); 704 kfree(encoder); 705 } 706 707 708 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector) 709 { 710 int enc_id = connector->encoder_ids[0]; 711 /* pick the encoder ids */ 712 if (enc_id) 713 return drm_encoder_find(connector->dev, enc_id); 714 return NULL; 715 } 716 717 718 static const struct drm_encoder_funcs ast_enc_funcs = { 719 .destroy = ast_encoder_destroy, 720 }; 721 722 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode) 723 { 724 725 } 726 727 static void ast_encoder_mode_set(struct drm_encoder *encoder, 728 struct drm_display_mode *mode, 729 struct drm_display_mode *adjusted_mode) 730 { 731 } 732 733 static void ast_encoder_prepare(struct drm_encoder *encoder) 734 { 735 736 } 737 738 static void ast_encoder_commit(struct drm_encoder *encoder) 739 { 740 741 } 742 743 744 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = { 745 .dpms = ast_encoder_dpms, 746 .prepare = ast_encoder_prepare, 747 .commit = ast_encoder_commit, 748 .mode_set = ast_encoder_mode_set, 749 }; 750 751 static int ast_encoder_init(struct drm_device *dev) 752 { 753 struct ast_encoder *ast_encoder; 754 755 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL); 756 if (!ast_encoder) 757 return -ENOMEM; 758 759 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs, 760 DRM_MODE_ENCODER_DAC, NULL); 761 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); 762 763 ast_encoder->base.possible_crtcs = 1; 764 return 0; 765 } 766 767 static int ast_get_modes(struct drm_connector *connector) 768 { 769 struct ast_connector *ast_connector = to_ast_connector(connector); 770 struct ast_private *ast = connector->dev->dev_private; 771 struct edid *edid; 772 int ret; 773 bool flags = false; 774 if (ast->tx_chip_type == AST_TX_DP501) { 775 ast->dp501_maxclk = 0xff; 776 edid = kmalloc(128, GFP_KERNEL); 777 if (!edid) 778 return -ENOMEM; 779 780 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 781 if (flags) 782 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 783 else 784 kfree(edid); 785 } 786 if (!flags) 787 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 788 if (edid) { 789 drm_mode_connector_update_edid_property(&ast_connector->base, edid); 790 ret = drm_add_edid_modes(connector, edid); 791 kfree(edid); 792 return ret; 793 } else 794 drm_mode_connector_update_edid_property(&ast_connector->base, NULL); 795 return 0; 796 } 797 798 static int ast_mode_valid(struct drm_connector *connector, 799 struct drm_display_mode *mode) 800 { 801 struct ast_private *ast = connector->dev->dev_private; 802 int flags = MODE_NOMODE; 803 uint32_t jtemp; 804 805 if (ast->support_wide_screen) { 806 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 807 return MODE_OK; 808 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 809 return MODE_OK; 810 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 811 return MODE_OK; 812 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 813 return MODE_OK; 814 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 815 return MODE_OK; 816 817 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 818 (ast->chip == AST2300) || (ast->chip == AST2400) || 819 (ast->chip == AST2500) || (ast->chip == AST1180)) { 820 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 821 return MODE_OK; 822 823 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 824 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 825 if (jtemp & 0x01) 826 return MODE_NOMODE; 827 else 828 return MODE_OK; 829 } 830 } 831 } 832 switch (mode->hdisplay) { 833 case 640: 834 if (mode->vdisplay == 480) flags = MODE_OK; 835 break; 836 case 800: 837 if (mode->vdisplay == 600) flags = MODE_OK; 838 break; 839 case 1024: 840 if (mode->vdisplay == 768) flags = MODE_OK; 841 break; 842 case 1280: 843 if (mode->vdisplay == 1024) flags = MODE_OK; 844 break; 845 case 1600: 846 if (mode->vdisplay == 1200) flags = MODE_OK; 847 break; 848 default: 849 return flags; 850 } 851 852 return flags; 853 } 854 855 static void ast_connector_destroy(struct drm_connector *connector) 856 { 857 struct ast_connector *ast_connector = to_ast_connector(connector); 858 ast_i2c_destroy(ast_connector->i2c); 859 drm_connector_unregister(connector); 860 drm_connector_cleanup(connector); 861 kfree(connector); 862 } 863 864 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 865 .mode_valid = ast_mode_valid, 866 .get_modes = ast_get_modes, 867 .best_encoder = ast_best_single_encoder, 868 }; 869 870 static const struct drm_connector_funcs ast_connector_funcs = { 871 .dpms = drm_helper_connector_dpms, 872 .fill_modes = drm_helper_probe_single_connector_modes, 873 .destroy = ast_connector_destroy, 874 }; 875 876 static int ast_connector_init(struct drm_device *dev) 877 { 878 struct ast_connector *ast_connector; 879 struct drm_connector *connector; 880 struct drm_encoder *encoder; 881 882 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 883 if (!ast_connector) 884 return -ENOMEM; 885 886 connector = &ast_connector->base; 887 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA); 888 889 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 890 891 connector->interlace_allowed = 0; 892 connector->doublescan_allowed = 0; 893 894 drm_connector_register(connector); 895 896 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 897 898 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 899 drm_mode_connector_attach_encoder(connector, encoder); 900 901 ast_connector->i2c = ast_i2c_create(dev); 902 if (!ast_connector->i2c) 903 DRM_ERROR("failed to add ddc bus for connector\n"); 904 905 return 0; 906 } 907 908 /* allocate cursor cache and pin at start of VRAM */ 909 static int ast_cursor_init(struct drm_device *dev) 910 { 911 struct ast_private *ast = dev->dev_private; 912 int size; 913 int ret; 914 struct drm_gem_object *obj; 915 struct ast_bo *bo; 916 uint64_t gpu_addr; 917 918 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM; 919 920 ret = ast_gem_create(dev, size, true, &obj); 921 if (ret) 922 return ret; 923 bo = gem_to_ast_bo(obj); 924 ret = ast_bo_reserve(bo, false); 925 if (unlikely(ret != 0)) 926 goto fail; 927 928 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 929 ast_bo_unreserve(bo); 930 if (ret) 931 goto fail; 932 933 /* kmap the object */ 934 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap); 935 if (ret) 936 goto fail; 937 938 ast->cursor_cache = obj; 939 ast->cursor_cache_gpu_addr = gpu_addr; 940 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr); 941 return 0; 942 fail: 943 return ret; 944 } 945 946 static void ast_cursor_fini(struct drm_device *dev) 947 { 948 struct ast_private *ast = dev->dev_private; 949 ttm_bo_kunmap(&ast->cache_kmap); 950 drm_gem_object_unreference_unlocked(ast->cursor_cache); 951 } 952 953 int ast_mode_init(struct drm_device *dev) 954 { 955 ast_cursor_init(dev); 956 ast_crtc_init(dev); 957 ast_encoder_init(dev); 958 ast_connector_init(dev); 959 return 0; 960 } 961 962 void ast_mode_fini(struct drm_device *dev) 963 { 964 ast_cursor_fini(dev); 965 } 966 967 static int get_clock(void *i2c_priv) 968 { 969 struct ast_i2c_chan *i2c = i2c_priv; 970 struct ast_private *ast = i2c->dev->dev_private; 971 uint32_t val; 972 973 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4; 974 return val & 1 ? 1 : 0; 975 } 976 977 static int get_data(void *i2c_priv) 978 { 979 struct ast_i2c_chan *i2c = i2c_priv; 980 struct ast_private *ast = i2c->dev->dev_private; 981 uint32_t val; 982 983 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5; 984 return val & 1 ? 1 : 0; 985 } 986 987 static void set_clock(void *i2c_priv, int clock) 988 { 989 struct ast_i2c_chan *i2c = i2c_priv; 990 struct ast_private *ast = i2c->dev->dev_private; 991 int i; 992 u8 ujcrb7, jtemp; 993 994 for (i = 0; i < 0x10000; i++) { 995 ujcrb7 = ((clock & 0x01) ? 0 : 1); 996 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7); 997 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 998 if (ujcrb7 == jtemp) 999 break; 1000 } 1001 } 1002 1003 static void set_data(void *i2c_priv, int data) 1004 { 1005 struct ast_i2c_chan *i2c = i2c_priv; 1006 struct ast_private *ast = i2c->dev->dev_private; 1007 int i; 1008 u8 ujcrb7, jtemp; 1009 1010 for (i = 0; i < 0x10000; i++) { 1011 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1012 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7); 1013 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1014 if (ujcrb7 == jtemp) 1015 break; 1016 } 1017 } 1018 1019 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1020 { 1021 struct ast_i2c_chan *i2c; 1022 int ret; 1023 1024 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1025 if (!i2c) 1026 return NULL; 1027 1028 i2c->adapter.owner = THIS_MODULE; 1029 i2c->adapter.class = I2C_CLASS_DDC; 1030 i2c->adapter.dev.parent = &dev->pdev->dev; 1031 i2c->dev = dev; 1032 i2c_set_adapdata(&i2c->adapter, i2c); 1033 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1034 "AST i2c bit bus"); 1035 i2c->adapter.algo_data = &i2c->bit; 1036 1037 i2c->bit.udelay = 20; 1038 i2c->bit.timeout = 2; 1039 i2c->bit.data = i2c; 1040 i2c->bit.setsda = set_data; 1041 i2c->bit.setscl = set_clock; 1042 i2c->bit.getsda = get_data; 1043 i2c->bit.getscl = get_clock; 1044 ret = i2c_bit_add_bus(&i2c->adapter); 1045 if (ret) { 1046 DRM_ERROR("Failed to register bit i2c\n"); 1047 goto out_free; 1048 } 1049 1050 return i2c; 1051 out_free: 1052 kfree(i2c); 1053 return NULL; 1054 } 1055 1056 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1057 { 1058 if (!i2c) 1059 return; 1060 i2c_del_adapter(&i2c->adapter); 1061 kfree(i2c); 1062 } 1063 1064 static void ast_show_cursor(struct drm_crtc *crtc) 1065 { 1066 struct ast_private *ast = crtc->dev->dev_private; 1067 u8 jreg; 1068 1069 jreg = 0x2; 1070 /* enable ARGB cursor */ 1071 jreg |= 1; 1072 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1073 } 1074 1075 static void ast_hide_cursor(struct drm_crtc *crtc) 1076 { 1077 struct ast_private *ast = crtc->dev->dev_private; 1078 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 1079 } 1080 1081 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1082 { 1083 union { 1084 u32 ul; 1085 u8 b[4]; 1086 } srcdata32[2], data32; 1087 union { 1088 u16 us; 1089 u8 b[2]; 1090 } data16; 1091 u32 csum = 0; 1092 s32 alpha_dst_delta, last_alpha_dst_delta; 1093 u8 *srcxor, *dstxor; 1094 int i, j; 1095 u32 per_pixel_copy, two_pixel_copy; 1096 1097 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1098 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1099 1100 srcxor = src; 1101 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1102 per_pixel_copy = width & 1; 1103 two_pixel_copy = width >> 1; 1104 1105 for (j = 0; j < height; j++) { 1106 for (i = 0; i < two_pixel_copy; i++) { 1107 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1108 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1109 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1110 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1111 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1112 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1113 1114 writel(data32.ul, dstxor); 1115 csum += data32.ul; 1116 1117 dstxor += 4; 1118 srcxor += 8; 1119 1120 } 1121 1122 for (i = 0; i < per_pixel_copy; i++) { 1123 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1124 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1125 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1126 writew(data16.us, dstxor); 1127 csum += (u32)data16.us; 1128 1129 dstxor += 2; 1130 srcxor += 4; 1131 } 1132 dstxor += last_alpha_dst_delta; 1133 } 1134 return csum; 1135 } 1136 1137 static int ast_cursor_set(struct drm_crtc *crtc, 1138 struct drm_file *file_priv, 1139 uint32_t handle, 1140 uint32_t width, 1141 uint32_t height) 1142 { 1143 struct ast_private *ast = crtc->dev->dev_private; 1144 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1145 struct drm_gem_object *obj; 1146 struct ast_bo *bo; 1147 uint64_t gpu_addr; 1148 u32 csum; 1149 int ret; 1150 struct ttm_bo_kmap_obj uobj_map; 1151 u8 *src, *dst; 1152 bool src_isiomem, dst_isiomem; 1153 if (!handle) { 1154 ast_hide_cursor(crtc); 1155 return 0; 1156 } 1157 1158 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT) 1159 return -EINVAL; 1160 1161 obj = drm_gem_object_lookup(file_priv, handle); 1162 if (!obj) { 1163 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle); 1164 return -ENOENT; 1165 } 1166 bo = gem_to_ast_bo(obj); 1167 1168 ret = ast_bo_reserve(bo, false); 1169 if (ret) 1170 goto fail; 1171 1172 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map); 1173 1174 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem); 1175 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem); 1176 1177 if (src_isiomem == true) 1178 DRM_ERROR("src cursor bo should be in main memory\n"); 1179 if (dst_isiomem == false) 1180 DRM_ERROR("dst bo should be in VRAM\n"); 1181 1182 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1183 1184 /* do data transfer to cursor cache */ 1185 csum = copy_cursor_image(src, dst, width, height); 1186 1187 /* write checksum + signature */ 1188 ttm_bo_kunmap(&uobj_map); 1189 ast_bo_unreserve(bo); 1190 { 1191 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1192 writel(csum, dst); 1193 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1194 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1195 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1196 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1197 1198 /* set pattern offset */ 1199 gpu_addr = ast->cursor_cache_gpu_addr; 1200 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1201 gpu_addr >>= 3; 1202 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff); 1203 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff); 1204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff); 1205 } 1206 ast_crtc->cursor_width = width; 1207 ast_crtc->cursor_height = height; 1208 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width; 1209 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height; 1210 1211 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM; 1212 1213 ast_show_cursor(crtc); 1214 1215 drm_gem_object_unreference_unlocked(obj); 1216 return 0; 1217 fail: 1218 drm_gem_object_unreference_unlocked(obj); 1219 return ret; 1220 } 1221 1222 static int ast_cursor_move(struct drm_crtc *crtc, 1223 int x, int y) 1224 { 1225 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1226 struct ast_private *ast = crtc->dev->dev_private; 1227 int x_offset, y_offset; 1228 u8 *sig; 1229 1230 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1231 writel(x, sig + AST_HWC_SIGNATURE_X); 1232 writel(y, sig + AST_HWC_SIGNATURE_Y); 1233 1234 x_offset = ast_crtc->offset_x; 1235 y_offset = ast_crtc->offset_y; 1236 if (x < 0) { 1237 x_offset = (-x) + ast_crtc->offset_x; 1238 x = 0; 1239 } 1240 1241 if (y < 0) { 1242 y_offset = (-y) + ast_crtc->offset_y; 1243 y = 0; 1244 } 1245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1247 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1250 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1251 1252 /* dummy write to fire HWC */ 1253 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00); 1254 1255 return 0; 1256 } 1257