1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include <drm/drm_probe_helper.h> 36 #include "ast_drv.h" 37 38 #include "ast_tables.h" 39 40 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 41 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 42 static int ast_cursor_set(struct drm_crtc *crtc, 43 struct drm_file *file_priv, 44 uint32_t handle, 45 uint32_t width, 46 uint32_t height); 47 static int ast_cursor_move(struct drm_crtc *crtc, 48 int x, int y); 49 50 static inline void ast_load_palette_index(struct ast_private *ast, 51 u8 index, u8 red, u8 green, 52 u8 blue) 53 { 54 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 55 ast_io_read8(ast, AST_IO_SEQ_PORT); 56 ast_io_write8(ast, AST_IO_DAC_DATA, red); 57 ast_io_read8(ast, AST_IO_SEQ_PORT); 58 ast_io_write8(ast, AST_IO_DAC_DATA, green); 59 ast_io_read8(ast, AST_IO_SEQ_PORT); 60 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 61 ast_io_read8(ast, AST_IO_SEQ_PORT); 62 } 63 64 static void ast_crtc_load_lut(struct drm_crtc *crtc) 65 { 66 struct ast_private *ast = crtc->dev->dev_private; 67 u16 *r, *g, *b; 68 int i; 69 70 if (!crtc->enabled) 71 return; 72 73 r = crtc->gamma_store; 74 g = r + crtc->gamma_size; 75 b = g + crtc->gamma_size; 76 77 for (i = 0; i < 256; i++) 78 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8); 79 } 80 81 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, 82 struct drm_display_mode *adjusted_mode, 83 struct ast_vbios_mode_info *vbios_mode) 84 { 85 struct ast_private *ast = crtc->dev->dev_private; 86 const struct drm_framebuffer *fb = crtc->primary->fb; 87 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; 88 const struct ast_vbios_enhtable *best = NULL; 89 u32 hborder, vborder; 90 bool check_sync; 91 92 switch (fb->format->cpp[0] * 8) { 93 case 8: 94 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 95 color_index = VGAModeIndex - 1; 96 break; 97 case 16: 98 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 99 color_index = HiCModeIndex; 100 break; 101 case 24: 102 case 32: 103 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 104 color_index = TrueCModeIndex; 105 break; 106 default: 107 return false; 108 } 109 110 switch (crtc->mode.crtc_hdisplay) { 111 case 640: 112 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 113 break; 114 case 800: 115 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 116 break; 117 case 1024: 118 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 119 break; 120 case 1280: 121 if (crtc->mode.crtc_vdisplay == 800) 122 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 123 else 124 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 125 break; 126 case 1360: 127 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 128 break; 129 case 1440: 130 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 131 break; 132 case 1600: 133 if (crtc->mode.crtc_vdisplay == 900) 134 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 135 else 136 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 137 break; 138 case 1680: 139 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 140 break; 141 case 1920: 142 if (crtc->mode.crtc_vdisplay == 1080) 143 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 144 else 145 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 146 break; 147 default: 148 return false; 149 } 150 151 refresh_rate = drm_mode_vrefresh(mode); 152 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 153 do { 154 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 155 156 while (loop->refresh_rate != 0xff) { 157 if ((check_sync) && 158 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 159 (loop->flags & PVSync)) || 160 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 161 (loop->flags & NVSync)) || 162 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 163 (loop->flags & PHSync)) || 164 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 165 (loop->flags & NHSync)))) { 166 loop++; 167 continue; 168 } 169 if (loop->refresh_rate <= refresh_rate 170 && (!best || loop->refresh_rate > best->refresh_rate)) 171 best = loop; 172 loop++; 173 } 174 if (best || !check_sync) 175 break; 176 check_sync = 0; 177 } while (1); 178 if (best) 179 vbios_mode->enh_table = best; 180 181 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 182 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 183 184 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 185 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 186 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 187 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 188 vbios_mode->enh_table->hfp; 189 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 190 vbios_mode->enh_table->hfp + 191 vbios_mode->enh_table->hsync); 192 193 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 194 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 195 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 196 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 197 vbios_mode->enh_table->vfp; 198 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 199 vbios_mode->enh_table->vfp + 200 vbios_mode->enh_table->vsync); 201 202 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 203 mode_id = vbios_mode->enh_table->mode_id; 204 205 if (ast->chip == AST1180) { 206 /* TODO 1180 */ 207 } else { 208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); 209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 211 212 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 213 if (vbios_mode->enh_table->flags & NewModeInfo) { 214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, 216 fb->format->cpp[0] * 8); 217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 219 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 220 221 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 222 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 223 } 224 } 225 226 return true; 227 228 229 } 230 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 231 struct ast_vbios_mode_info *vbios_mode) 232 { 233 struct ast_private *ast = crtc->dev->dev_private; 234 const struct ast_vbios_stdtable *stdtable; 235 u32 i; 236 u8 jreg; 237 238 stdtable = vbios_mode->std_table; 239 240 jreg = stdtable->misc; 241 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 242 243 /* Set SEQ */ 244 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 245 for (i = 0; i < 4; i++) { 246 jreg = stdtable->seq[i]; 247 if (!i) 248 jreg |= 0x20; 249 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 250 } 251 252 /* Set CRTC */ 253 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 254 for (i = 0; i < 25; i++) 255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 256 257 /* set AR */ 258 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 259 for (i = 0; i < 20; i++) { 260 jreg = stdtable->ar[i]; 261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 262 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 263 } 264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 265 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 266 267 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 268 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 269 270 /* Set GR */ 271 for (i = 0; i < 9; i++) 272 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 273 } 274 275 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 276 struct ast_vbios_mode_info *vbios_mode) 277 { 278 struct ast_private *ast = crtc->dev->dev_private; 279 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 280 u16 temp, precache = 0; 281 282 if ((ast->chip == AST2500) && 283 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 284 precache = 40; 285 286 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 287 288 temp = (mode->crtc_htotal >> 3) - 5; 289 if (temp & 0x100) 290 jregAC |= 0x01; /* HT D[8] */ 291 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 292 293 temp = (mode->crtc_hdisplay >> 3) - 1; 294 if (temp & 0x100) 295 jregAC |= 0x04; /* HDE D[8] */ 296 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 297 298 temp = (mode->crtc_hblank_start >> 3) - 1; 299 if (temp & 0x100) 300 jregAC |= 0x10; /* HBS D[8] */ 301 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 302 303 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 304 if (temp & 0x20) 305 jreg05 |= 0x80; /* HBE D[5] */ 306 if (temp & 0x40) 307 jregAD |= 0x01; /* HBE D[5] */ 308 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 309 310 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 311 if (temp & 0x100) 312 jregAC |= 0x40; /* HRS D[5] */ 313 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 314 315 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 316 if (temp & 0x20) 317 jregAD |= 0x04; /* HRE D[5] */ 318 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 319 320 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 321 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 322 323 /* vert timings */ 324 temp = (mode->crtc_vtotal) - 2; 325 if (temp & 0x100) 326 jreg07 |= 0x01; 327 if (temp & 0x200) 328 jreg07 |= 0x20; 329 if (temp & 0x400) 330 jregAE |= 0x01; 331 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 332 333 temp = (mode->crtc_vsync_start) - 1; 334 if (temp & 0x100) 335 jreg07 |= 0x04; 336 if (temp & 0x200) 337 jreg07 |= 0x80; 338 if (temp & 0x400) 339 jregAE |= 0x08; 340 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 341 342 temp = (mode->crtc_vsync_end - 1) & 0x3f; 343 if (temp & 0x10) 344 jregAE |= 0x20; 345 if (temp & 0x20) 346 jregAE |= 0x40; 347 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 348 349 temp = mode->crtc_vdisplay - 1; 350 if (temp & 0x100) 351 jreg07 |= 0x02; 352 if (temp & 0x200) 353 jreg07 |= 0x40; 354 if (temp & 0x400) 355 jregAE |= 0x02; 356 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 357 358 temp = mode->crtc_vblank_start - 1; 359 if (temp & 0x100) 360 jreg07 |= 0x08; 361 if (temp & 0x200) 362 jreg09 |= 0x20; 363 if (temp & 0x400) 364 jregAE |= 0x04; 365 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 366 367 temp = mode->crtc_vblank_end - 1; 368 if (temp & 0x100) 369 jregAE |= 0x10; 370 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 371 372 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 374 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 375 376 if (precache) 377 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 378 else 379 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 380 381 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 382 } 383 384 static void ast_set_offset_reg(struct drm_crtc *crtc) 385 { 386 struct ast_private *ast = crtc->dev->dev_private; 387 const struct drm_framebuffer *fb = crtc->primary->fb; 388 389 u16 offset; 390 391 offset = fb->pitches[0] >> 3; 392 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 393 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 394 } 395 396 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, 397 struct ast_vbios_mode_info *vbios_mode) 398 { 399 struct ast_private *ast = dev->dev_private; 400 const struct ast_vbios_dclk_info *clk_info; 401 402 if (ast->chip == AST2500) 403 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 404 else 405 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 406 407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 408 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 409 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 410 (clk_info->param3 & 0xc0) | 411 ((clk_info->param3 & 0x3) << 4)); 412 } 413 414 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 415 struct ast_vbios_mode_info *vbios_mode) 416 { 417 struct ast_private *ast = crtc->dev->dev_private; 418 const struct drm_framebuffer *fb = crtc->primary->fb; 419 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 420 421 switch (fb->format->cpp[0] * 8) { 422 case 8: 423 jregA0 = 0x70; 424 jregA3 = 0x01; 425 jregA8 = 0x00; 426 break; 427 case 15: 428 case 16: 429 jregA0 = 0x70; 430 jregA3 = 0x04; 431 jregA8 = 0x02; 432 break; 433 case 32: 434 jregA0 = 0x70; 435 jregA3 = 0x08; 436 jregA8 = 0x02; 437 break; 438 } 439 440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 441 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 442 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 443 444 /* Set Threshold */ 445 if (ast->chip == AST2300 || ast->chip == AST2400 || 446 ast->chip == AST2500) { 447 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 448 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 449 } else if (ast->chip == AST2100 || 450 ast->chip == AST1100 || 451 ast->chip == AST2200 || 452 ast->chip == AST2150) { 453 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 454 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 455 } else { 456 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 457 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 458 } 459 } 460 461 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, 462 struct ast_vbios_mode_info *vbios_mode) 463 { 464 struct ast_private *ast = dev->dev_private; 465 u8 jreg; 466 467 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 468 jreg &= ~0xC0; 469 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 470 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 471 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 472 } 473 474 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 475 struct ast_vbios_mode_info *vbios_mode) 476 { 477 const struct drm_framebuffer *fb = crtc->primary->fb; 478 479 switch (fb->format->cpp[0] * 8) { 480 case 8: 481 break; 482 default: 483 return false; 484 } 485 return true; 486 } 487 488 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset) 489 { 490 struct ast_private *ast = crtc->dev->dev_private; 491 u32 addr; 492 493 addr = offset >> 2; 494 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 496 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 497 498 } 499 500 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 501 { 502 struct ast_private *ast = crtc->dev->dev_private; 503 504 if (ast->chip == AST1180) 505 return; 506 507 switch (mode) { 508 case DRM_MODE_DPMS_ON: 509 case DRM_MODE_DPMS_STANDBY: 510 case DRM_MODE_DPMS_SUSPEND: 511 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 512 if (ast->tx_chip_type == AST_TX_DP501) 513 ast_set_dp501_video_output(crtc->dev, 1); 514 ast_crtc_load_lut(crtc); 515 break; 516 case DRM_MODE_DPMS_OFF: 517 if (ast->tx_chip_type == AST_TX_DP501) 518 ast_set_dp501_video_output(crtc->dev, 0); 519 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 520 break; 521 } 522 } 523 524 /* ast is different - we will force move buffers out of VRAM */ 525 static int ast_crtc_do_set_base(struct drm_crtc *crtc, 526 struct drm_framebuffer *fb, 527 int x, int y, int atomic) 528 { 529 struct ast_private *ast = crtc->dev->dev_private; 530 struct drm_gem_object *obj; 531 struct ast_framebuffer *ast_fb; 532 struct ast_bo *bo; 533 int ret; 534 u64 gpu_addr; 535 536 /* push the previous fb to system ram */ 537 if (!atomic && fb) { 538 ast_fb = to_ast_framebuffer(fb); 539 obj = ast_fb->obj; 540 bo = gem_to_ast_bo(obj); 541 ret = ast_bo_reserve(bo, false); 542 if (ret) 543 return ret; 544 ast_bo_push_sysram(bo); 545 ast_bo_unreserve(bo); 546 } 547 548 ast_fb = to_ast_framebuffer(crtc->primary->fb); 549 obj = ast_fb->obj; 550 bo = gem_to_ast_bo(obj); 551 552 ret = ast_bo_reserve(bo, false); 553 if (ret) 554 return ret; 555 556 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 557 if (ret) { 558 ast_bo_unreserve(bo); 559 return ret; 560 } 561 562 if (&ast->fbdev->afb == ast_fb) { 563 /* if pushing console in kmap it */ 564 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 565 if (ret) 566 DRM_ERROR("failed to kmap fbcon\n"); 567 else 568 ast_fbdev_set_base(ast, gpu_addr); 569 } 570 ast_bo_unreserve(bo); 571 572 ast_set_offset_reg(crtc); 573 ast_set_start_address_crt1(crtc, (u32)gpu_addr); 574 575 return 0; 576 } 577 578 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 579 struct drm_framebuffer *old_fb) 580 { 581 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0); 582 } 583 584 static int ast_crtc_mode_set(struct drm_crtc *crtc, 585 struct drm_display_mode *mode, 586 struct drm_display_mode *adjusted_mode, 587 int x, int y, 588 struct drm_framebuffer *old_fb) 589 { 590 struct drm_device *dev = crtc->dev; 591 struct ast_private *ast = crtc->dev->dev_private; 592 struct ast_vbios_mode_info vbios_mode; 593 bool ret; 594 if (ast->chip == AST1180) { 595 DRM_ERROR("AST 1180 modesetting not supported\n"); 596 return -EINVAL; 597 } 598 599 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); 600 if (ret == false) 601 return -EINVAL; 602 ast_open_key(ast); 603 604 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); 605 606 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); 607 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); 608 ast_set_offset_reg(crtc); 609 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); 610 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); 611 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); 612 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode); 613 614 ast_crtc_mode_set_base(crtc, x, y, old_fb); 615 616 return 0; 617 } 618 619 static void ast_crtc_disable(struct drm_crtc *crtc) 620 { 621 int ret; 622 623 DRM_DEBUG_KMS("\n"); 624 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 625 if (crtc->primary->fb) { 626 struct ast_framebuffer *ast_fb = to_ast_framebuffer(crtc->primary->fb); 627 struct drm_gem_object *obj = ast_fb->obj; 628 struct ast_bo *bo = gem_to_ast_bo(obj); 629 630 ret = ast_bo_reserve(bo, false); 631 if (ret) 632 return; 633 634 ast_bo_push_sysram(bo); 635 ast_bo_unreserve(bo); 636 } 637 crtc->primary->fb = NULL; 638 } 639 640 static void ast_crtc_prepare(struct drm_crtc *crtc) 641 { 642 643 } 644 645 static void ast_crtc_commit(struct drm_crtc *crtc) 646 { 647 struct ast_private *ast = crtc->dev->dev_private; 648 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 649 ast_crtc_load_lut(crtc); 650 } 651 652 653 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 654 .dpms = ast_crtc_dpms, 655 .mode_set = ast_crtc_mode_set, 656 .mode_set_base = ast_crtc_mode_set_base, 657 .disable = ast_crtc_disable, 658 .prepare = ast_crtc_prepare, 659 .commit = ast_crtc_commit, 660 661 }; 662 663 static void ast_crtc_reset(struct drm_crtc *crtc) 664 { 665 666 } 667 668 static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 669 u16 *blue, uint32_t size, 670 struct drm_modeset_acquire_ctx *ctx) 671 { 672 ast_crtc_load_lut(crtc); 673 674 return 0; 675 } 676 677 678 static void ast_crtc_destroy(struct drm_crtc *crtc) 679 { 680 drm_crtc_cleanup(crtc); 681 kfree(crtc); 682 } 683 684 static const struct drm_crtc_funcs ast_crtc_funcs = { 685 .cursor_set = ast_cursor_set, 686 .cursor_move = ast_cursor_move, 687 .reset = ast_crtc_reset, 688 .set_config = drm_crtc_helper_set_config, 689 .gamma_set = ast_crtc_gamma_set, 690 .destroy = ast_crtc_destroy, 691 }; 692 693 static int ast_crtc_init(struct drm_device *dev) 694 { 695 struct ast_crtc *crtc; 696 697 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 698 if (!crtc) 699 return -ENOMEM; 700 701 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); 702 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 703 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 704 return 0; 705 } 706 707 static void ast_encoder_destroy(struct drm_encoder *encoder) 708 { 709 drm_encoder_cleanup(encoder); 710 kfree(encoder); 711 } 712 713 714 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector) 715 { 716 int enc_id = connector->encoder_ids[0]; 717 /* pick the encoder ids */ 718 if (enc_id) 719 return drm_encoder_find(connector->dev, NULL, enc_id); 720 return NULL; 721 } 722 723 724 static const struct drm_encoder_funcs ast_enc_funcs = { 725 .destroy = ast_encoder_destroy, 726 }; 727 728 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode) 729 { 730 731 } 732 733 static void ast_encoder_mode_set(struct drm_encoder *encoder, 734 struct drm_display_mode *mode, 735 struct drm_display_mode *adjusted_mode) 736 { 737 } 738 739 static void ast_encoder_prepare(struct drm_encoder *encoder) 740 { 741 742 } 743 744 static void ast_encoder_commit(struct drm_encoder *encoder) 745 { 746 747 } 748 749 750 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = { 751 .dpms = ast_encoder_dpms, 752 .prepare = ast_encoder_prepare, 753 .commit = ast_encoder_commit, 754 .mode_set = ast_encoder_mode_set, 755 }; 756 757 static int ast_encoder_init(struct drm_device *dev) 758 { 759 struct ast_encoder *ast_encoder; 760 761 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL); 762 if (!ast_encoder) 763 return -ENOMEM; 764 765 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs, 766 DRM_MODE_ENCODER_DAC, NULL); 767 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); 768 769 ast_encoder->base.possible_crtcs = 1; 770 return 0; 771 } 772 773 static int ast_get_modes(struct drm_connector *connector) 774 { 775 struct ast_connector *ast_connector = to_ast_connector(connector); 776 struct ast_private *ast = connector->dev->dev_private; 777 struct edid *edid; 778 int ret; 779 bool flags = false; 780 if (ast->tx_chip_type == AST_TX_DP501) { 781 ast->dp501_maxclk = 0xff; 782 edid = kmalloc(128, GFP_KERNEL); 783 if (!edid) 784 return -ENOMEM; 785 786 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 787 if (flags) 788 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 789 else 790 kfree(edid); 791 } 792 if (!flags) 793 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 794 if (edid) { 795 drm_connector_update_edid_property(&ast_connector->base, edid); 796 ret = drm_add_edid_modes(connector, edid); 797 kfree(edid); 798 return ret; 799 } else 800 drm_connector_update_edid_property(&ast_connector->base, NULL); 801 return 0; 802 } 803 804 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, 805 struct drm_display_mode *mode) 806 { 807 struct ast_private *ast = connector->dev->dev_private; 808 int flags = MODE_NOMODE; 809 uint32_t jtemp; 810 811 if (ast->support_wide_screen) { 812 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 813 return MODE_OK; 814 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 815 return MODE_OK; 816 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 817 return MODE_OK; 818 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 819 return MODE_OK; 820 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 821 return MODE_OK; 822 823 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 824 (ast->chip == AST2300) || (ast->chip == AST2400) || 825 (ast->chip == AST2500) || (ast->chip == AST1180)) { 826 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 827 return MODE_OK; 828 829 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 830 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 831 if (jtemp & 0x01) 832 return MODE_NOMODE; 833 else 834 return MODE_OK; 835 } 836 } 837 } 838 switch (mode->hdisplay) { 839 case 640: 840 if (mode->vdisplay == 480) flags = MODE_OK; 841 break; 842 case 800: 843 if (mode->vdisplay == 600) flags = MODE_OK; 844 break; 845 case 1024: 846 if (mode->vdisplay == 768) flags = MODE_OK; 847 break; 848 case 1280: 849 if (mode->vdisplay == 1024) flags = MODE_OK; 850 break; 851 case 1600: 852 if (mode->vdisplay == 1200) flags = MODE_OK; 853 break; 854 default: 855 return flags; 856 } 857 858 return flags; 859 } 860 861 static void ast_connector_destroy(struct drm_connector *connector) 862 { 863 struct ast_connector *ast_connector = to_ast_connector(connector); 864 ast_i2c_destroy(ast_connector->i2c); 865 drm_connector_unregister(connector); 866 drm_connector_cleanup(connector); 867 kfree(connector); 868 } 869 870 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 871 .mode_valid = ast_mode_valid, 872 .get_modes = ast_get_modes, 873 .best_encoder = ast_best_single_encoder, 874 }; 875 876 static const struct drm_connector_funcs ast_connector_funcs = { 877 .dpms = drm_helper_connector_dpms, 878 .fill_modes = drm_helper_probe_single_connector_modes, 879 .destroy = ast_connector_destroy, 880 }; 881 882 static int ast_connector_init(struct drm_device *dev) 883 { 884 struct ast_connector *ast_connector; 885 struct drm_connector *connector; 886 struct drm_encoder *encoder; 887 888 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 889 if (!ast_connector) 890 return -ENOMEM; 891 892 connector = &ast_connector->base; 893 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA); 894 895 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 896 897 connector->interlace_allowed = 0; 898 connector->doublescan_allowed = 0; 899 900 drm_connector_register(connector); 901 902 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 903 904 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 905 drm_connector_attach_encoder(connector, encoder); 906 907 ast_connector->i2c = ast_i2c_create(dev); 908 if (!ast_connector->i2c) 909 DRM_ERROR("failed to add ddc bus for connector\n"); 910 911 return 0; 912 } 913 914 /* allocate cursor cache and pin at start of VRAM */ 915 static int ast_cursor_init(struct drm_device *dev) 916 { 917 struct ast_private *ast = dev->dev_private; 918 int size; 919 int ret; 920 struct drm_gem_object *obj; 921 struct ast_bo *bo; 922 uint64_t gpu_addr; 923 924 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM; 925 926 ret = ast_gem_create(dev, size, true, &obj); 927 if (ret) 928 return ret; 929 bo = gem_to_ast_bo(obj); 930 ret = ast_bo_reserve(bo, false); 931 if (unlikely(ret != 0)) 932 goto fail; 933 934 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 935 ast_bo_unreserve(bo); 936 if (ret) 937 goto fail; 938 939 /* kmap the object */ 940 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap); 941 if (ret) 942 goto fail; 943 944 ast->cursor_cache = obj; 945 ast->cursor_cache_gpu_addr = gpu_addr; 946 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr); 947 return 0; 948 fail: 949 return ret; 950 } 951 952 static void ast_cursor_fini(struct drm_device *dev) 953 { 954 struct ast_private *ast = dev->dev_private; 955 ttm_bo_kunmap(&ast->cache_kmap); 956 drm_gem_object_put_unlocked(ast->cursor_cache); 957 } 958 959 int ast_mode_init(struct drm_device *dev) 960 { 961 ast_cursor_init(dev); 962 ast_crtc_init(dev); 963 ast_encoder_init(dev); 964 ast_connector_init(dev); 965 return 0; 966 } 967 968 void ast_mode_fini(struct drm_device *dev) 969 { 970 ast_cursor_fini(dev); 971 } 972 973 static int get_clock(void *i2c_priv) 974 { 975 struct ast_i2c_chan *i2c = i2c_priv; 976 struct ast_private *ast = i2c->dev->dev_private; 977 uint32_t val, val2, count, pass; 978 979 count = 0; 980 pass = 0; 981 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 982 do { 983 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 984 if (val == val2) { 985 pass++; 986 } else { 987 pass = 0; 988 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 989 } 990 } while ((pass < 5) && (count++ < 0x10000)); 991 992 return val & 1 ? 1 : 0; 993 } 994 995 static int get_data(void *i2c_priv) 996 { 997 struct ast_i2c_chan *i2c = i2c_priv; 998 struct ast_private *ast = i2c->dev->dev_private; 999 uint32_t val, val2, count, pass; 1000 1001 count = 0; 1002 pass = 0; 1003 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1004 do { 1005 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1006 if (val == val2) { 1007 pass++; 1008 } else { 1009 pass = 0; 1010 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1011 } 1012 } while ((pass < 5) && (count++ < 0x10000)); 1013 1014 return val & 1 ? 1 : 0; 1015 } 1016 1017 static void set_clock(void *i2c_priv, int clock) 1018 { 1019 struct ast_i2c_chan *i2c = i2c_priv; 1020 struct ast_private *ast = i2c->dev->dev_private; 1021 int i; 1022 u8 ujcrb7, jtemp; 1023 1024 for (i = 0; i < 0x10000; i++) { 1025 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1026 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); 1027 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1028 if (ujcrb7 == jtemp) 1029 break; 1030 } 1031 } 1032 1033 static void set_data(void *i2c_priv, int data) 1034 { 1035 struct ast_i2c_chan *i2c = i2c_priv; 1036 struct ast_private *ast = i2c->dev->dev_private; 1037 int i; 1038 u8 ujcrb7, jtemp; 1039 1040 for (i = 0; i < 0x10000; i++) { 1041 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1042 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); 1043 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1044 if (ujcrb7 == jtemp) 1045 break; 1046 } 1047 } 1048 1049 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1050 { 1051 struct ast_i2c_chan *i2c; 1052 int ret; 1053 1054 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1055 if (!i2c) 1056 return NULL; 1057 1058 i2c->adapter.owner = THIS_MODULE; 1059 i2c->adapter.class = I2C_CLASS_DDC; 1060 i2c->adapter.dev.parent = &dev->pdev->dev; 1061 i2c->dev = dev; 1062 i2c_set_adapdata(&i2c->adapter, i2c); 1063 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1064 "AST i2c bit bus"); 1065 i2c->adapter.algo_data = &i2c->bit; 1066 1067 i2c->bit.udelay = 20; 1068 i2c->bit.timeout = 2; 1069 i2c->bit.data = i2c; 1070 i2c->bit.setsda = set_data; 1071 i2c->bit.setscl = set_clock; 1072 i2c->bit.getsda = get_data; 1073 i2c->bit.getscl = get_clock; 1074 ret = i2c_bit_add_bus(&i2c->adapter); 1075 if (ret) { 1076 DRM_ERROR("Failed to register bit i2c\n"); 1077 goto out_free; 1078 } 1079 1080 return i2c; 1081 out_free: 1082 kfree(i2c); 1083 return NULL; 1084 } 1085 1086 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1087 { 1088 if (!i2c) 1089 return; 1090 i2c_del_adapter(&i2c->adapter); 1091 kfree(i2c); 1092 } 1093 1094 static void ast_show_cursor(struct drm_crtc *crtc) 1095 { 1096 struct ast_private *ast = crtc->dev->dev_private; 1097 u8 jreg; 1098 1099 jreg = 0x2; 1100 /* enable ARGB cursor */ 1101 jreg |= 1; 1102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1103 } 1104 1105 static void ast_hide_cursor(struct drm_crtc *crtc) 1106 { 1107 struct ast_private *ast = crtc->dev->dev_private; 1108 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 1109 } 1110 1111 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1112 { 1113 union { 1114 u32 ul; 1115 u8 b[4]; 1116 } srcdata32[2], data32; 1117 union { 1118 u16 us; 1119 u8 b[2]; 1120 } data16; 1121 u32 csum = 0; 1122 s32 alpha_dst_delta, last_alpha_dst_delta; 1123 u8 *srcxor, *dstxor; 1124 int i, j; 1125 u32 per_pixel_copy, two_pixel_copy; 1126 1127 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1128 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1129 1130 srcxor = src; 1131 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1132 per_pixel_copy = width & 1; 1133 two_pixel_copy = width >> 1; 1134 1135 for (j = 0; j < height; j++) { 1136 for (i = 0; i < two_pixel_copy; i++) { 1137 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1138 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1139 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1140 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1141 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1142 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1143 1144 writel(data32.ul, dstxor); 1145 csum += data32.ul; 1146 1147 dstxor += 4; 1148 srcxor += 8; 1149 1150 } 1151 1152 for (i = 0; i < per_pixel_copy; i++) { 1153 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1154 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1155 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1156 writew(data16.us, dstxor); 1157 csum += (u32)data16.us; 1158 1159 dstxor += 2; 1160 srcxor += 4; 1161 } 1162 dstxor += last_alpha_dst_delta; 1163 } 1164 return csum; 1165 } 1166 1167 static int ast_cursor_set(struct drm_crtc *crtc, 1168 struct drm_file *file_priv, 1169 uint32_t handle, 1170 uint32_t width, 1171 uint32_t height) 1172 { 1173 struct ast_private *ast = crtc->dev->dev_private; 1174 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1175 struct drm_gem_object *obj; 1176 struct ast_bo *bo; 1177 uint64_t gpu_addr; 1178 u32 csum; 1179 int ret; 1180 struct ttm_bo_kmap_obj uobj_map; 1181 u8 *src, *dst; 1182 bool src_isiomem, dst_isiomem; 1183 if (!handle) { 1184 ast_hide_cursor(crtc); 1185 return 0; 1186 } 1187 1188 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT) 1189 return -EINVAL; 1190 1191 obj = drm_gem_object_lookup(file_priv, handle); 1192 if (!obj) { 1193 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle); 1194 return -ENOENT; 1195 } 1196 bo = gem_to_ast_bo(obj); 1197 1198 ret = ast_bo_reserve(bo, false); 1199 if (ret) 1200 goto fail; 1201 1202 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map); 1203 1204 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem); 1205 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem); 1206 1207 if (src_isiomem == true) 1208 DRM_ERROR("src cursor bo should be in main memory\n"); 1209 if (dst_isiomem == false) 1210 DRM_ERROR("dst bo should be in VRAM\n"); 1211 1212 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1213 1214 /* do data transfer to cursor cache */ 1215 csum = copy_cursor_image(src, dst, width, height); 1216 1217 /* write checksum + signature */ 1218 ttm_bo_kunmap(&uobj_map); 1219 ast_bo_unreserve(bo); 1220 { 1221 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1222 writel(csum, dst); 1223 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1224 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1225 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1226 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1227 1228 /* set pattern offset */ 1229 gpu_addr = ast->cursor_cache_gpu_addr; 1230 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; 1231 gpu_addr >>= 3; 1232 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff); 1233 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff); 1234 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff); 1235 } 1236 ast_crtc->cursor_width = width; 1237 ast_crtc->cursor_height = height; 1238 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width; 1239 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height; 1240 1241 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM; 1242 1243 ast_show_cursor(crtc); 1244 1245 drm_gem_object_put_unlocked(obj); 1246 return 0; 1247 fail: 1248 drm_gem_object_put_unlocked(obj); 1249 return ret; 1250 } 1251 1252 static int ast_cursor_move(struct drm_crtc *crtc, 1253 int x, int y) 1254 { 1255 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1256 struct ast_private *ast = crtc->dev->dev_private; 1257 int x_offset, y_offset; 1258 u8 *sig; 1259 1260 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE; 1261 writel(x, sig + AST_HWC_SIGNATURE_X); 1262 writel(y, sig + AST_HWC_SIGNATURE_Y); 1263 1264 x_offset = ast_crtc->offset_x; 1265 y_offset = ast_crtc->offset_y; 1266 if (x < 0) { 1267 x_offset = (-x) + ast_crtc->offset_x; 1268 x = 0; 1269 } 1270 1271 if (y < 0) { 1272 y_offset = (-y) + ast_crtc->offset_y; 1273 y = 0; 1274 } 1275 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1276 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1277 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1278 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1279 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1280 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1281 1282 /* dummy write to fire HWC */ 1283 ast_show_cursor(crtc); 1284 1285 return 0; 1286 } 1287