1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 31 #include <linux/export.h> 32 #include <linux/pci.h> 33 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_atomic_state_helper.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fourcc.h> 40 #include <drm/drm_gem_vram_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_simple_kms_helper.h> 44 45 #include "ast_drv.h" 46 #include "ast_tables.h" 47 48 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 49 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 50 static int ast_cursor_move(struct drm_crtc *crtc, 51 int x, int y); 52 53 54 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height); 55 static int ast_cursor_update(void *dst, void *src, unsigned int width, 56 unsigned int height); 57 static void ast_cursor_set_base(struct ast_private *ast, u64 address); 58 static int ast_cursor_move(struct drm_crtc *crtc, 59 int x, int y); 60 61 static inline void ast_load_palette_index(struct ast_private *ast, 62 u8 index, u8 red, u8 green, 63 u8 blue) 64 { 65 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 66 ast_io_read8(ast, AST_IO_SEQ_PORT); 67 ast_io_write8(ast, AST_IO_DAC_DATA, red); 68 ast_io_read8(ast, AST_IO_SEQ_PORT); 69 ast_io_write8(ast, AST_IO_DAC_DATA, green); 70 ast_io_read8(ast, AST_IO_SEQ_PORT); 71 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 72 ast_io_read8(ast, AST_IO_SEQ_PORT); 73 } 74 75 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc) 76 { 77 u16 *r, *g, *b; 78 int i; 79 80 if (!crtc->enabled) 81 return; 82 83 r = crtc->gamma_store; 84 g = r + crtc->gamma_size; 85 b = g + crtc->gamma_size; 86 87 for (i = 0; i < 256; i++) 88 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8); 89 } 90 91 static bool ast_get_vbios_mode_info(const struct drm_format_info *format, 92 const struct drm_display_mode *mode, 93 struct drm_display_mode *adjusted_mode, 94 struct ast_vbios_mode_info *vbios_mode) 95 { 96 u32 refresh_rate_index = 0, refresh_rate; 97 const struct ast_vbios_enhtable *best = NULL; 98 u32 hborder, vborder; 99 bool check_sync; 100 101 switch (format->cpp[0] * 8) { 102 case 8: 103 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 104 break; 105 case 16: 106 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 107 break; 108 case 24: 109 case 32: 110 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 111 break; 112 default: 113 return false; 114 } 115 116 switch (mode->crtc_hdisplay) { 117 case 640: 118 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 119 break; 120 case 800: 121 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 122 break; 123 case 1024: 124 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 125 break; 126 case 1280: 127 if (mode->crtc_vdisplay == 800) 128 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 129 else 130 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 131 break; 132 case 1360: 133 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 134 break; 135 case 1440: 136 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 137 break; 138 case 1600: 139 if (mode->crtc_vdisplay == 900) 140 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 141 else 142 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 143 break; 144 case 1680: 145 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 146 break; 147 case 1920: 148 if (mode->crtc_vdisplay == 1080) 149 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 150 else 151 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 152 break; 153 default: 154 return false; 155 } 156 157 refresh_rate = drm_mode_vrefresh(mode); 158 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 159 160 while (1) { 161 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 162 163 while (loop->refresh_rate != 0xff) { 164 if ((check_sync) && 165 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 166 (loop->flags & PVSync)) || 167 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 168 (loop->flags & NVSync)) || 169 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 170 (loop->flags & PHSync)) || 171 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 172 (loop->flags & NHSync)))) { 173 loop++; 174 continue; 175 } 176 if (loop->refresh_rate <= refresh_rate 177 && (!best || loop->refresh_rate > best->refresh_rate)) 178 best = loop; 179 loop++; 180 } 181 if (best || !check_sync) 182 break; 183 check_sync = 0; 184 } 185 186 if (best) 187 vbios_mode->enh_table = best; 188 189 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 190 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 191 192 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 193 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 194 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 195 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 196 vbios_mode->enh_table->hfp; 197 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 198 vbios_mode->enh_table->hfp + 199 vbios_mode->enh_table->hsync); 200 201 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 202 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 203 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 204 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 205 vbios_mode->enh_table->vfp; 206 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 207 vbios_mode->enh_table->vfp + 208 vbios_mode->enh_table->vsync); 209 210 return true; 211 } 212 213 static void ast_set_vbios_color_reg(struct ast_private *ast, 214 const struct drm_format_info *format, 215 const struct ast_vbios_mode_info *vbios_mode) 216 { 217 u32 color_index; 218 219 switch (format->cpp[0]) { 220 case 1: 221 color_index = VGAModeIndex - 1; 222 break; 223 case 2: 224 color_index = HiCModeIndex; 225 break; 226 case 3: 227 case 4: 228 color_index = TrueCModeIndex; 229 default: 230 return; 231 } 232 233 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4)); 234 235 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 236 237 if (vbios_mode->enh_table->flags & NewModeInfo) { 238 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 239 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8); 240 } 241 } 242 243 static void ast_set_vbios_mode_reg(struct ast_private *ast, 244 const struct drm_display_mode *adjusted_mode, 245 const struct ast_vbios_mode_info *vbios_mode) 246 { 247 u32 refresh_rate_index, mode_id; 248 249 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 250 mode_id = vbios_mode->enh_table->mode_id; 251 252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 254 255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 256 257 if (vbios_mode->enh_table->flags & NewModeInfo) { 258 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 259 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 260 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 261 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 262 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 263 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 264 } 265 } 266 267 static void ast_set_std_reg(struct ast_private *ast, 268 struct drm_display_mode *mode, 269 struct ast_vbios_mode_info *vbios_mode) 270 { 271 const struct ast_vbios_stdtable *stdtable; 272 u32 i; 273 u8 jreg; 274 275 stdtable = vbios_mode->std_table; 276 277 jreg = stdtable->misc; 278 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 279 280 /* Set SEQ; except Screen Disable field */ 281 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 282 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]); 283 for (i = 1; i < 4; i++) { 284 jreg = stdtable->seq[i]; 285 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 286 } 287 288 /* Set CRTC; except base address and offset */ 289 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 290 for (i = 0; i < 12; i++) 291 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 292 for (i = 14; i < 19; i++) 293 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 294 for (i = 20; i < 25; i++) 295 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 296 297 /* set AR */ 298 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 299 for (i = 0; i < 20; i++) { 300 jreg = stdtable->ar[i]; 301 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 302 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 303 } 304 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 305 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 306 307 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 308 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 309 310 /* Set GR */ 311 for (i = 0; i < 9; i++) 312 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 313 } 314 315 static void ast_set_crtc_reg(struct ast_private *ast, 316 struct drm_display_mode *mode, 317 struct ast_vbios_mode_info *vbios_mode) 318 { 319 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 320 u16 temp, precache = 0; 321 322 if ((ast->chip == AST2500) && 323 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 324 precache = 40; 325 326 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 327 328 temp = (mode->crtc_htotal >> 3) - 5; 329 if (temp & 0x100) 330 jregAC |= 0x01; /* HT D[8] */ 331 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 332 333 temp = (mode->crtc_hdisplay >> 3) - 1; 334 if (temp & 0x100) 335 jregAC |= 0x04; /* HDE D[8] */ 336 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 337 338 temp = (mode->crtc_hblank_start >> 3) - 1; 339 if (temp & 0x100) 340 jregAC |= 0x10; /* HBS D[8] */ 341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 342 343 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 344 if (temp & 0x20) 345 jreg05 |= 0x80; /* HBE D[5] */ 346 if (temp & 0x40) 347 jregAD |= 0x01; /* HBE D[5] */ 348 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 349 350 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 351 if (temp & 0x100) 352 jregAC |= 0x40; /* HRS D[5] */ 353 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 354 355 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 356 if (temp & 0x20) 357 jregAD |= 0x04; /* HRE D[5] */ 358 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 359 360 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 361 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 362 363 /* vert timings */ 364 temp = (mode->crtc_vtotal) - 2; 365 if (temp & 0x100) 366 jreg07 |= 0x01; 367 if (temp & 0x200) 368 jreg07 |= 0x20; 369 if (temp & 0x400) 370 jregAE |= 0x01; 371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 372 373 temp = (mode->crtc_vsync_start) - 1; 374 if (temp & 0x100) 375 jreg07 |= 0x04; 376 if (temp & 0x200) 377 jreg07 |= 0x80; 378 if (temp & 0x400) 379 jregAE |= 0x08; 380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 381 382 temp = (mode->crtc_vsync_end - 1) & 0x3f; 383 if (temp & 0x10) 384 jregAE |= 0x20; 385 if (temp & 0x20) 386 jregAE |= 0x40; 387 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 388 389 temp = mode->crtc_vdisplay - 1; 390 if (temp & 0x100) 391 jreg07 |= 0x02; 392 if (temp & 0x200) 393 jreg07 |= 0x40; 394 if (temp & 0x400) 395 jregAE |= 0x02; 396 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 397 398 temp = mode->crtc_vblank_start - 1; 399 if (temp & 0x100) 400 jreg07 |= 0x08; 401 if (temp & 0x200) 402 jreg09 |= 0x20; 403 if (temp & 0x400) 404 jregAE |= 0x04; 405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 406 407 temp = mode->crtc_vblank_end - 1; 408 if (temp & 0x100) 409 jregAE |= 0x10; 410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 411 412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 413 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 415 416 if (precache) 417 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 418 else 419 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 420 421 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 422 } 423 424 static void ast_set_offset_reg(struct ast_private *ast, 425 struct drm_framebuffer *fb) 426 { 427 u16 offset; 428 429 offset = fb->pitches[0] >> 3; 430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 432 } 433 434 static void ast_set_dclk_reg(struct ast_private *ast, 435 struct drm_display_mode *mode, 436 struct ast_vbios_mode_info *vbios_mode) 437 { 438 const struct ast_vbios_dclk_info *clk_info; 439 440 if (ast->chip == AST2500) 441 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 442 else 443 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 444 445 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 446 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 447 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 448 (clk_info->param3 & 0xc0) | 449 ((clk_info->param3 & 0x3) << 4)); 450 } 451 452 static void ast_set_color_reg(struct ast_private *ast, 453 const struct drm_format_info *format) 454 { 455 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 456 457 switch (format->cpp[0] * 8) { 458 case 8: 459 jregA0 = 0x70; 460 jregA3 = 0x01; 461 jregA8 = 0x00; 462 break; 463 case 15: 464 case 16: 465 jregA0 = 0x70; 466 jregA3 = 0x04; 467 jregA8 = 0x02; 468 break; 469 case 32: 470 jregA0 = 0x70; 471 jregA3 = 0x08; 472 jregA8 = 0x02; 473 break; 474 } 475 476 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 477 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 478 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 479 } 480 481 static void ast_set_crtthd_reg(struct ast_private *ast) 482 { 483 /* Set Threshold */ 484 if (ast->chip == AST2300 || ast->chip == AST2400 || 485 ast->chip == AST2500) { 486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 487 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 488 } else if (ast->chip == AST2100 || 489 ast->chip == AST1100 || 490 ast->chip == AST2200 || 491 ast->chip == AST2150) { 492 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 494 } else { 495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 496 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 497 } 498 } 499 500 static void ast_set_sync_reg(struct ast_private *ast, 501 struct drm_display_mode *mode, 502 struct ast_vbios_mode_info *vbios_mode) 503 { 504 u8 jreg; 505 506 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 507 jreg &= ~0xC0; 508 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 509 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 510 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 511 } 512 513 static void ast_set_start_address_crt1(struct ast_private *ast, 514 unsigned offset) 515 { 516 u32 addr; 517 518 addr = offset >> 2; 519 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 520 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 521 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 522 523 } 524 525 /* 526 * Primary plane 527 */ 528 529 static const uint32_t ast_primary_plane_formats[] = { 530 DRM_FORMAT_XRGB8888, 531 DRM_FORMAT_RGB565, 532 DRM_FORMAT_C8, 533 }; 534 535 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, 536 struct drm_plane_state *state) 537 { 538 struct drm_crtc_state *crtc_state; 539 struct ast_crtc_state *ast_crtc_state; 540 int ret; 541 542 if (!state->crtc) 543 return 0; 544 545 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 546 547 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 548 DRM_PLANE_HELPER_NO_SCALING, 549 DRM_PLANE_HELPER_NO_SCALING, 550 false, true); 551 if (ret) 552 return ret; 553 554 if (!state->visible) 555 return 0; 556 557 ast_crtc_state = to_ast_crtc_state(crtc_state); 558 559 ast_crtc_state->format = state->fb->format; 560 561 return 0; 562 } 563 564 void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, 565 struct drm_plane_state *old_state) 566 { 567 struct ast_private *ast = plane->dev->dev_private; 568 struct drm_plane_state *state = plane->state; 569 struct drm_gem_vram_object *gbo; 570 s64 gpu_addr; 571 572 gbo = drm_gem_vram_of_gem(state->fb->obj[0]); 573 gpu_addr = drm_gem_vram_offset(gbo); 574 if (WARN_ON_ONCE(gpu_addr < 0)) 575 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */ 576 577 ast_set_offset_reg(ast, state->fb); 578 ast_set_start_address_crt1(ast, (u32)gpu_addr); 579 580 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00); 581 } 582 583 static void 584 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, 585 struct drm_plane_state *old_state) 586 { 587 struct ast_private *ast = plane->dev->dev_private; 588 589 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 590 } 591 592 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = { 593 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, 594 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, 595 .atomic_check = ast_primary_plane_helper_atomic_check, 596 .atomic_update = ast_primary_plane_helper_atomic_update, 597 .atomic_disable = ast_primary_plane_helper_atomic_disable, 598 }; 599 600 static const struct drm_plane_funcs ast_primary_plane_funcs = { 601 .update_plane = drm_atomic_helper_update_plane, 602 .disable_plane = drm_atomic_helper_disable_plane, 603 .destroy = drm_plane_cleanup, 604 .reset = drm_atomic_helper_plane_reset, 605 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 606 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 607 }; 608 609 /* 610 * Cursor plane 611 */ 612 613 static const uint32_t ast_cursor_plane_formats[] = { 614 DRM_FORMAT_ARGB8888, 615 }; 616 617 static int 618 ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane, 619 struct drm_plane_state *new_state) 620 { 621 struct drm_framebuffer *fb = new_state->fb; 622 struct drm_crtc *crtc = new_state->crtc; 623 struct drm_gem_vram_object *gbo; 624 struct ast_private *ast; 625 int ret; 626 void *src, *dst; 627 628 if (!crtc || !fb) 629 return 0; 630 631 if (WARN_ON_ONCE(fb->width > AST_MAX_HWC_WIDTH) || 632 WARN_ON_ONCE(fb->height > AST_MAX_HWC_HEIGHT)) 633 return -EINVAL; /* BUG: didn't test in atomic_check() */ 634 635 ast = crtc->dev->dev_private; 636 637 gbo = drm_gem_vram_of_gem(fb->obj[0]); 638 src = drm_gem_vram_vmap(gbo); 639 if (IS_ERR(src)) { 640 ret = PTR_ERR(src); 641 goto err_drm_gem_vram_unpin; 642 } 643 644 dst = drm_gem_vram_vmap(ast->cursor.gbo[ast->cursor.next_index]); 645 if (IS_ERR(dst)) { 646 ret = PTR_ERR(dst); 647 goto err_drm_gem_vram_vunmap_src; 648 } 649 650 ret = ast_cursor_update(dst, src, fb->width, fb->height); 651 if (ret) 652 goto err_drm_gem_vram_vunmap_dst; 653 654 /* Always unmap buffers here. Destination buffers are 655 * perma-pinned while the driver is active. We're only 656 * changing ref-counters here. 657 */ 658 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); 659 drm_gem_vram_vunmap(gbo, src); 660 661 return 0; 662 663 err_drm_gem_vram_vunmap_dst: 664 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); 665 err_drm_gem_vram_vunmap_src: 666 drm_gem_vram_vunmap(gbo, src); 667 err_drm_gem_vram_unpin: 668 drm_gem_vram_unpin(gbo); 669 return ret; 670 } 671 672 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, 673 struct drm_plane_state *state) 674 { 675 struct drm_framebuffer *fb = state->fb; 676 struct drm_crtc_state *crtc_state; 677 int ret; 678 679 if (!state->crtc) 680 return 0; 681 682 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 683 684 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 685 DRM_PLANE_HELPER_NO_SCALING, 686 DRM_PLANE_HELPER_NO_SCALING, 687 true, true); 688 if (ret) 689 return ret; 690 691 if (!state->visible) 692 return 0; 693 694 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) 695 return -EINVAL; 696 697 return 0; 698 } 699 700 static void 701 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, 702 struct drm_plane_state *old_state) 703 { 704 struct drm_plane_state *state = plane->state; 705 struct drm_crtc *crtc = state->crtc; 706 struct drm_framebuffer *fb = state->fb; 707 struct ast_private *ast = plane->dev->dev_private; 708 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 709 struct drm_gem_vram_object *gbo; 710 s64 off; 711 u8 jreg; 712 713 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - fb->width; 714 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - fb->height; 715 716 if (state->fb != old_state->fb) { 717 /* A new cursor image was installed. */ 718 gbo = ast->cursor.gbo[ast->cursor.next_index]; 719 off = drm_gem_vram_offset(gbo); 720 if (WARN_ON_ONCE(off < 0)) 721 return; /* Bug: we didn't pin cursor HW BO to VRAM. */ 722 ast_cursor_set_base(ast, off); 723 724 ++ast->cursor.next_index; 725 ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo); 726 } 727 728 ast_cursor_move(crtc, state->crtc_x, state->crtc_y); 729 730 jreg = 0x2; 731 /* enable ARGB cursor */ 732 jreg |= 1; 733 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 734 } 735 736 static void 737 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, 738 struct drm_plane_state *old_state) 739 { 740 struct ast_private *ast = plane->dev->dev_private; 741 742 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 743 } 744 745 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = { 746 .prepare_fb = ast_cursor_plane_helper_prepare_fb, 747 .cleanup_fb = NULL, /* not required for cursor plane */ 748 .atomic_check = ast_cursor_plane_helper_atomic_check, 749 .atomic_update = ast_cursor_plane_helper_atomic_update, 750 .atomic_disable = ast_cursor_plane_helper_atomic_disable, 751 }; 752 753 static const struct drm_plane_funcs ast_cursor_plane_funcs = { 754 .update_plane = drm_atomic_helper_update_plane, 755 .disable_plane = drm_atomic_helper_disable_plane, 756 .destroy = drm_plane_cleanup, 757 .reset = drm_atomic_helper_plane_reset, 758 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 759 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 760 }; 761 762 /* 763 * CRTC 764 */ 765 766 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 767 { 768 struct ast_private *ast = crtc->dev->dev_private; 769 770 if (ast->chip == AST1180) 771 return; 772 773 /* TODO: Maybe control display signal generation with 774 * Sync Enable (bit CR17.7). 775 */ 776 switch (mode) { 777 case DRM_MODE_DPMS_ON: 778 case DRM_MODE_DPMS_STANDBY: 779 case DRM_MODE_DPMS_SUSPEND: 780 if (ast->tx_chip_type == AST_TX_DP501) 781 ast_set_dp501_video_output(crtc->dev, 1); 782 ast_crtc_load_lut(ast, crtc); 783 break; 784 case DRM_MODE_DPMS_OFF: 785 if (ast->tx_chip_type == AST_TX_DP501) 786 ast_set_dp501_video_output(crtc->dev, 0); 787 break; 788 } 789 } 790 791 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, 792 struct drm_crtc_state *state) 793 { 794 struct ast_private *ast = crtc->dev->dev_private; 795 struct ast_crtc_state *ast_state; 796 const struct drm_format_info *format; 797 bool succ; 798 799 if (ast->chip == AST1180) { 800 DRM_ERROR("AST 1180 modesetting not supported\n"); 801 return -EINVAL; 802 } 803 804 ast_state = to_ast_crtc_state(state); 805 806 format = ast_state->format; 807 if (!format) 808 return 0; 809 810 succ = ast_get_vbios_mode_info(format, &state->mode, 811 &state->adjusted_mode, 812 &ast_state->vbios_mode_info); 813 if (!succ) 814 return -EINVAL; 815 816 return 0; 817 } 818 819 static void ast_crtc_helper_atomic_begin(struct drm_crtc *crtc, 820 struct drm_crtc_state *old_crtc_state) 821 { 822 struct ast_private *ast = crtc->dev->dev_private; 823 824 ast_open_key(ast); 825 } 826 827 static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, 828 struct drm_crtc_state *old_crtc_state) 829 { 830 struct drm_device *dev = crtc->dev; 831 struct ast_private *ast = dev->dev_private; 832 struct ast_crtc_state *ast_state; 833 const struct drm_format_info *format; 834 struct ast_vbios_mode_info *vbios_mode_info; 835 struct drm_display_mode *adjusted_mode; 836 837 ast_state = to_ast_crtc_state(crtc->state); 838 839 format = ast_state->format; 840 if (!format) 841 return; 842 843 vbios_mode_info = &ast_state->vbios_mode_info; 844 845 ast_set_color_reg(ast, format); 846 ast_set_vbios_color_reg(ast, format, vbios_mode_info); 847 848 if (!crtc->state->mode_changed) 849 return; 850 851 adjusted_mode = &crtc->state->adjusted_mode; 852 853 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info); 854 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); 855 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info); 856 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info); 857 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info); 858 ast_set_crtthd_reg(ast); 859 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info); 860 } 861 862 static void 863 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, 864 struct drm_crtc_state *old_crtc_state) 865 { 866 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 867 } 868 869 static void 870 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, 871 struct drm_crtc_state *old_crtc_state) 872 { 873 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 874 } 875 876 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 877 .atomic_check = ast_crtc_helper_atomic_check, 878 .atomic_begin = ast_crtc_helper_atomic_begin, 879 .atomic_flush = ast_crtc_helper_atomic_flush, 880 .atomic_enable = ast_crtc_helper_atomic_enable, 881 .atomic_disable = ast_crtc_helper_atomic_disable, 882 }; 883 884 static void ast_crtc_destroy(struct drm_crtc *crtc) 885 { 886 drm_crtc_cleanup(crtc); 887 kfree(crtc); 888 } 889 890 static struct drm_crtc_state * 891 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 892 { 893 struct ast_crtc_state *new_ast_state, *ast_state; 894 895 if (WARN_ON(!crtc->state)) 896 return NULL; 897 898 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL); 899 if (!new_ast_state) 900 return NULL; 901 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base); 902 903 ast_state = to_ast_crtc_state(crtc->state); 904 905 new_ast_state->format = ast_state->format; 906 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info, 907 sizeof(new_ast_state->vbios_mode_info)); 908 909 return &new_ast_state->base; 910 } 911 912 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc, 913 struct drm_crtc_state *state) 914 { 915 struct ast_crtc_state *ast_state = to_ast_crtc_state(state); 916 917 __drm_atomic_helper_crtc_destroy_state(&ast_state->base); 918 kfree(ast_state); 919 } 920 921 static const struct drm_crtc_funcs ast_crtc_funcs = { 922 .reset = drm_atomic_helper_crtc_reset, 923 .set_config = drm_crtc_helper_set_config, 924 .gamma_set = drm_atomic_helper_legacy_gamma_set, 925 .destroy = ast_crtc_destroy, 926 .set_config = drm_atomic_helper_set_config, 927 .page_flip = drm_atomic_helper_page_flip, 928 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state, 929 .atomic_destroy_state = ast_crtc_atomic_destroy_state, 930 }; 931 932 static int ast_crtc_init(struct drm_device *dev) 933 { 934 struct ast_private *ast = dev->dev_private; 935 struct ast_crtc *crtc; 936 int ret; 937 938 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 939 if (!crtc) 940 return -ENOMEM; 941 942 ret = drm_crtc_init_with_planes(dev, &crtc->base, &ast->primary_plane, 943 &ast->cursor_plane, &ast_crtc_funcs, 944 NULL); 945 if (ret) 946 goto err_kfree; 947 948 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 949 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 950 return 0; 951 952 err_kfree: 953 kfree(crtc); 954 return ret; 955 } 956 957 /* 958 * Encoder 959 */ 960 961 static int ast_encoder_init(struct drm_device *dev) 962 { 963 struct ast_private *ast = dev->dev_private; 964 struct drm_encoder *encoder = &ast->encoder; 965 int ret; 966 967 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC); 968 if (ret) 969 return ret; 970 971 encoder->possible_crtcs = 1; 972 973 return 0; 974 } 975 976 /* 977 * Connector 978 */ 979 980 static int ast_get_modes(struct drm_connector *connector) 981 { 982 struct ast_connector *ast_connector = to_ast_connector(connector); 983 struct ast_private *ast = connector->dev->dev_private; 984 struct edid *edid; 985 int ret; 986 bool flags = false; 987 if (ast->tx_chip_type == AST_TX_DP501) { 988 ast->dp501_maxclk = 0xff; 989 edid = kmalloc(128, GFP_KERNEL); 990 if (!edid) 991 return -ENOMEM; 992 993 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 994 if (flags) 995 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 996 else 997 kfree(edid); 998 } 999 if (!flags) 1000 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 1001 if (edid) { 1002 drm_connector_update_edid_property(&ast_connector->base, edid); 1003 ret = drm_add_edid_modes(connector, edid); 1004 kfree(edid); 1005 return ret; 1006 } else 1007 drm_connector_update_edid_property(&ast_connector->base, NULL); 1008 return 0; 1009 } 1010 1011 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, 1012 struct drm_display_mode *mode) 1013 { 1014 struct ast_private *ast = connector->dev->dev_private; 1015 int flags = MODE_NOMODE; 1016 uint32_t jtemp; 1017 1018 if (ast->support_wide_screen) { 1019 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 1020 return MODE_OK; 1021 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 1022 return MODE_OK; 1023 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 1024 return MODE_OK; 1025 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 1026 return MODE_OK; 1027 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 1028 return MODE_OK; 1029 1030 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 1031 (ast->chip == AST2300) || (ast->chip == AST2400) || 1032 (ast->chip == AST2500) || (ast->chip == AST1180)) { 1033 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 1034 return MODE_OK; 1035 1036 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 1037 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 1038 if (jtemp & 0x01) 1039 return MODE_NOMODE; 1040 else 1041 return MODE_OK; 1042 } 1043 } 1044 } 1045 switch (mode->hdisplay) { 1046 case 640: 1047 if (mode->vdisplay == 480) flags = MODE_OK; 1048 break; 1049 case 800: 1050 if (mode->vdisplay == 600) flags = MODE_OK; 1051 break; 1052 case 1024: 1053 if (mode->vdisplay == 768) flags = MODE_OK; 1054 break; 1055 case 1280: 1056 if (mode->vdisplay == 1024) flags = MODE_OK; 1057 break; 1058 case 1600: 1059 if (mode->vdisplay == 1200) flags = MODE_OK; 1060 break; 1061 default: 1062 return flags; 1063 } 1064 1065 return flags; 1066 } 1067 1068 static void ast_connector_destroy(struct drm_connector *connector) 1069 { 1070 struct ast_connector *ast_connector = to_ast_connector(connector); 1071 ast_i2c_destroy(ast_connector->i2c); 1072 drm_connector_unregister(connector); 1073 drm_connector_cleanup(connector); 1074 kfree(connector); 1075 } 1076 1077 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 1078 .get_modes = ast_get_modes, 1079 .mode_valid = ast_mode_valid, 1080 }; 1081 1082 static const struct drm_connector_funcs ast_connector_funcs = { 1083 .reset = drm_atomic_helper_connector_reset, 1084 .fill_modes = drm_helper_probe_single_connector_modes, 1085 .destroy = ast_connector_destroy, 1086 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1087 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1088 }; 1089 1090 static int ast_connector_init(struct drm_device *dev) 1091 { 1092 struct ast_connector *ast_connector; 1093 struct drm_connector *connector; 1094 struct drm_encoder *encoder; 1095 1096 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 1097 if (!ast_connector) 1098 return -ENOMEM; 1099 1100 connector = &ast_connector->base; 1101 ast_connector->i2c = ast_i2c_create(dev); 1102 if (!ast_connector->i2c) 1103 DRM_ERROR("failed to add ddc bus for connector\n"); 1104 1105 drm_connector_init_with_ddc(dev, connector, 1106 &ast_connector_funcs, 1107 DRM_MODE_CONNECTOR_VGA, 1108 &ast_connector->i2c->adapter); 1109 1110 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 1111 1112 connector->interlace_allowed = 0; 1113 connector->doublescan_allowed = 0; 1114 1115 drm_connector_register(connector); 1116 1117 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1118 1119 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 1120 drm_connector_attach_encoder(connector, encoder); 1121 1122 return 0; 1123 } 1124 1125 /* allocate cursor cache and pin at start of VRAM */ 1126 static int ast_cursor_init(struct drm_device *dev) 1127 { 1128 struct ast_private *ast = dev->dev_private; 1129 size_t size, i; 1130 struct drm_gem_vram_object *gbo; 1131 int ret; 1132 1133 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE); 1134 1135 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { 1136 gbo = drm_gem_vram_create(dev, size, 0); 1137 if (IS_ERR(gbo)) { 1138 ret = PTR_ERR(gbo); 1139 goto err_drm_gem_vram_put; 1140 } 1141 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM | 1142 DRM_GEM_VRAM_PL_FLAG_TOPDOWN); 1143 if (ret) { 1144 drm_gem_vram_put(gbo); 1145 goto err_drm_gem_vram_put; 1146 } 1147 1148 ast->cursor.gbo[i] = gbo; 1149 } 1150 1151 return 0; 1152 1153 err_drm_gem_vram_put: 1154 while (i) { 1155 --i; 1156 gbo = ast->cursor.gbo[i]; 1157 drm_gem_vram_unpin(gbo); 1158 drm_gem_vram_put(gbo); 1159 ast->cursor.gbo[i] = NULL; 1160 } 1161 return ret; 1162 } 1163 1164 static void ast_cursor_fini(struct drm_device *dev) 1165 { 1166 struct ast_private *ast = dev->dev_private; 1167 size_t i; 1168 struct drm_gem_vram_object *gbo; 1169 1170 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { 1171 gbo = ast->cursor.gbo[i]; 1172 drm_gem_vram_unpin(gbo); 1173 drm_gem_vram_put(gbo); 1174 } 1175 } 1176 1177 int ast_mode_init(struct drm_device *dev) 1178 { 1179 struct ast_private *ast = dev->dev_private; 1180 int ret; 1181 1182 memset(&ast->primary_plane, 0, sizeof(ast->primary_plane)); 1183 ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01, 1184 &ast_primary_plane_funcs, 1185 ast_primary_plane_formats, 1186 ARRAY_SIZE(ast_primary_plane_formats), 1187 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1188 if (ret) { 1189 DRM_ERROR("ast: drm_universal_plane_init() failed: %d\n", ret); 1190 return ret; 1191 } 1192 drm_plane_helper_add(&ast->primary_plane, 1193 &ast_primary_plane_helper_funcs); 1194 1195 ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01, 1196 &ast_cursor_plane_funcs, 1197 ast_cursor_plane_formats, 1198 ARRAY_SIZE(ast_cursor_plane_formats), 1199 NULL, DRM_PLANE_TYPE_CURSOR, NULL); 1200 if (ret) { 1201 DRM_ERROR("drm_universal_plane_failed(): %d\n", ret); 1202 return ret; 1203 } 1204 drm_plane_helper_add(&ast->cursor_plane, 1205 &ast_cursor_plane_helper_funcs); 1206 1207 ast_cursor_init(dev); 1208 ast_crtc_init(dev); 1209 ast_encoder_init(dev); 1210 ast_connector_init(dev); 1211 1212 return 0; 1213 } 1214 1215 void ast_mode_fini(struct drm_device *dev) 1216 { 1217 ast_cursor_fini(dev); 1218 } 1219 1220 static int get_clock(void *i2c_priv) 1221 { 1222 struct ast_i2c_chan *i2c = i2c_priv; 1223 struct ast_private *ast = i2c->dev->dev_private; 1224 uint32_t val, val2, count, pass; 1225 1226 count = 0; 1227 pass = 0; 1228 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1229 do { 1230 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1231 if (val == val2) { 1232 pass++; 1233 } else { 1234 pass = 0; 1235 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1236 } 1237 } while ((pass < 5) && (count++ < 0x10000)); 1238 1239 return val & 1 ? 1 : 0; 1240 } 1241 1242 static int get_data(void *i2c_priv) 1243 { 1244 struct ast_i2c_chan *i2c = i2c_priv; 1245 struct ast_private *ast = i2c->dev->dev_private; 1246 uint32_t val, val2, count, pass; 1247 1248 count = 0; 1249 pass = 0; 1250 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1251 do { 1252 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1253 if (val == val2) { 1254 pass++; 1255 } else { 1256 pass = 0; 1257 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1258 } 1259 } while ((pass < 5) && (count++ < 0x10000)); 1260 1261 return val & 1 ? 1 : 0; 1262 } 1263 1264 static void set_clock(void *i2c_priv, int clock) 1265 { 1266 struct ast_i2c_chan *i2c = i2c_priv; 1267 struct ast_private *ast = i2c->dev->dev_private; 1268 int i; 1269 u8 ujcrb7, jtemp; 1270 1271 for (i = 0; i < 0x10000; i++) { 1272 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1273 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); 1274 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1275 if (ujcrb7 == jtemp) 1276 break; 1277 } 1278 } 1279 1280 static void set_data(void *i2c_priv, int data) 1281 { 1282 struct ast_i2c_chan *i2c = i2c_priv; 1283 struct ast_private *ast = i2c->dev->dev_private; 1284 int i; 1285 u8 ujcrb7, jtemp; 1286 1287 for (i = 0; i < 0x10000; i++) { 1288 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1289 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); 1290 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1291 if (ujcrb7 == jtemp) 1292 break; 1293 } 1294 } 1295 1296 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1297 { 1298 struct ast_i2c_chan *i2c; 1299 int ret; 1300 1301 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1302 if (!i2c) 1303 return NULL; 1304 1305 i2c->adapter.owner = THIS_MODULE; 1306 i2c->adapter.class = I2C_CLASS_DDC; 1307 i2c->adapter.dev.parent = &dev->pdev->dev; 1308 i2c->dev = dev; 1309 i2c_set_adapdata(&i2c->adapter, i2c); 1310 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1311 "AST i2c bit bus"); 1312 i2c->adapter.algo_data = &i2c->bit; 1313 1314 i2c->bit.udelay = 20; 1315 i2c->bit.timeout = 2; 1316 i2c->bit.data = i2c; 1317 i2c->bit.setsda = set_data; 1318 i2c->bit.setscl = set_clock; 1319 i2c->bit.getsda = get_data; 1320 i2c->bit.getscl = get_clock; 1321 ret = i2c_bit_add_bus(&i2c->adapter); 1322 if (ret) { 1323 DRM_ERROR("Failed to register bit i2c\n"); 1324 goto out_free; 1325 } 1326 1327 return i2c; 1328 out_free: 1329 kfree(i2c); 1330 return NULL; 1331 } 1332 1333 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1334 { 1335 if (!i2c) 1336 return; 1337 i2c_del_adapter(&i2c->adapter); 1338 kfree(i2c); 1339 } 1340 1341 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1342 { 1343 union { 1344 u32 ul; 1345 u8 b[4]; 1346 } srcdata32[2], data32; 1347 union { 1348 u16 us; 1349 u8 b[2]; 1350 } data16; 1351 u32 csum = 0; 1352 s32 alpha_dst_delta, last_alpha_dst_delta; 1353 u8 *srcxor, *dstxor; 1354 int i, j; 1355 u32 per_pixel_copy, two_pixel_copy; 1356 1357 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1358 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1359 1360 srcxor = src; 1361 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1362 per_pixel_copy = width & 1; 1363 two_pixel_copy = width >> 1; 1364 1365 for (j = 0; j < height; j++) { 1366 for (i = 0; i < two_pixel_copy; i++) { 1367 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1368 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1369 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1370 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1371 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1372 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1373 1374 writel(data32.ul, dstxor); 1375 csum += data32.ul; 1376 1377 dstxor += 4; 1378 srcxor += 8; 1379 1380 } 1381 1382 for (i = 0; i < per_pixel_copy; i++) { 1383 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1384 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1385 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1386 writew(data16.us, dstxor); 1387 csum += (u32)data16.us; 1388 1389 dstxor += 2; 1390 srcxor += 4; 1391 } 1392 dstxor += last_alpha_dst_delta; 1393 } 1394 return csum; 1395 } 1396 1397 static int ast_cursor_update(void *dst, void *src, unsigned int width, 1398 unsigned int height) 1399 { 1400 u32 csum; 1401 1402 /* do data transfer to cursor cache */ 1403 csum = copy_cursor_image(src, dst, width, height); 1404 1405 /* write checksum + signature */ 1406 dst += AST_HWC_SIZE; 1407 writel(csum, dst); 1408 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1409 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1410 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1411 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1412 1413 return 0; 1414 } 1415 1416 static void ast_cursor_set_base(struct ast_private *ast, u64 address) 1417 { 1418 u8 addr0 = (address >> 3) & 0xff; 1419 u8 addr1 = (address >> 11) & 0xff; 1420 u8 addr2 = (address >> 19) & 0xff; 1421 1422 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); 1423 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); 1424 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); 1425 } 1426 1427 static int ast_cursor_move(struct drm_crtc *crtc, 1428 int x, int y) 1429 { 1430 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1431 struct ast_private *ast = crtc->dev->dev_private; 1432 struct drm_gem_vram_object *gbo; 1433 int x_offset, y_offset; 1434 u8 *dst, *sig; 1435 u8 jreg; 1436 1437 gbo = ast->cursor.gbo[ast->cursor.next_index]; 1438 dst = drm_gem_vram_vmap(gbo); 1439 if (IS_ERR(dst)) 1440 return PTR_ERR(dst); 1441 1442 sig = dst + AST_HWC_SIZE; 1443 writel(x, sig + AST_HWC_SIGNATURE_X); 1444 writel(y, sig + AST_HWC_SIGNATURE_Y); 1445 1446 x_offset = ast_crtc->offset_x; 1447 y_offset = ast_crtc->offset_y; 1448 if (x < 0) { 1449 x_offset = (-x) + ast_crtc->offset_x; 1450 x = 0; 1451 } 1452 1453 if (y < 0) { 1454 y_offset = (-y) + ast_crtc->offset_y; 1455 y = 0; 1456 } 1457 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1458 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1459 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1460 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1461 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1462 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1463 1464 /* dummy write to fire HWC */ 1465 jreg = 0x02 | 1466 0x01; /* enable ARGB4444 cursor */ 1467 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1468 1469 drm_gem_vram_vunmap(gbo, dst); 1470 1471 return 0; 1472 } 1473