1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/pci.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_drv.h> 34 #include <drm/drm_gem.h> 35 #include <drm/drm_gem_vram_helper.h> 36 #include <drm/drm_managed.h> 37 38 #include "ast_drv.h" 39 40 void ast_set_index_reg_mask(struct ast_private *ast, 41 uint32_t base, uint8_t index, 42 uint8_t mask, uint8_t val) 43 { 44 u8 tmp; 45 ast_io_write8(ast, base, index); 46 tmp = (ast_io_read8(ast, base + 1) & mask) | val; 47 ast_set_index_reg(ast, base, index, tmp); 48 } 49 50 uint8_t ast_get_index_reg(struct ast_private *ast, 51 uint32_t base, uint8_t index) 52 { 53 uint8_t ret; 54 ast_io_write8(ast, base, index); 55 ret = ast_io_read8(ast, base + 1); 56 return ret; 57 } 58 59 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 60 uint32_t base, uint8_t index, uint8_t mask) 61 { 62 uint8_t ret; 63 ast_io_write8(ast, base, index); 64 ret = ast_io_read8(ast, base + 1) & mask; 65 return ret; 66 } 67 68 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) 69 { 70 struct device_node *np = dev->dev->of_node; 71 struct ast_private *ast = to_ast_private(dev); 72 struct pci_dev *pdev = to_pci_dev(dev->dev); 73 uint32_t data, jregd0, jregd1; 74 75 /* Defaults */ 76 ast->config_mode = ast_use_defaults; 77 *scu_rev = 0xffffffff; 78 79 /* Check if we have device-tree properties */ 80 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", 81 scu_rev)) { 82 /* We do, disable P2A access */ 83 ast->config_mode = ast_use_dt; 84 drm_info(dev, "Using device-tree for configuration\n"); 85 return; 86 } 87 88 /* Not all families have a P2A bridge */ 89 if (pdev->device != PCI_CHIP_AST2000) 90 return; 91 92 /* 93 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 94 * is disabled. We force using P2A if VGA only mode bit 95 * is set D[7] 96 */ 97 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 98 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 99 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { 100 /* Patch AST2500 */ 101 if (((pdev->revision & 0xF0) == 0x40) 102 && ((jregd0 & AST_VRAM_INIT_STATUS_MASK) == 0)) 103 ast_patch_ahb_2500(ast); 104 105 /* Double check it's actually working */ 106 data = ast_read32(ast, 0xf004); 107 if ((data != 0xFFFFFFFF) && (data != 0x00)) { 108 /* P2A works, grab silicon revision */ 109 ast->config_mode = ast_use_p2a; 110 111 drm_info(dev, "Using P2A bridge for configuration\n"); 112 113 /* Read SCU7c (silicon revision register) */ 114 ast_write32(ast, 0xf004, 0x1e6e0000); 115 ast_write32(ast, 0xf000, 0x1); 116 *scu_rev = ast_read32(ast, 0x1207c); 117 return; 118 } 119 } 120 121 /* We have a P2A bridge but it's disabled */ 122 drm_info(dev, "P2A bridge disabled, using default configuration\n"); 123 } 124 125 static int ast_detect_chip(struct drm_device *dev, bool *need_post) 126 { 127 struct ast_private *ast = to_ast_private(dev); 128 struct pci_dev *pdev = to_pci_dev(dev->dev); 129 uint32_t jreg, scu_rev; 130 131 /* 132 * If VGA isn't enabled, we need to enable now or subsequent 133 * access to the scratch registers will fail. We also inform 134 * our caller that it needs to POST the chip 135 * (Assumption: VGA not enabled -> need to POST) 136 */ 137 if (!ast_is_vga_enabled(dev)) { 138 ast_enable_vga(dev); 139 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n"); 140 *need_post = true; 141 } else 142 *need_post = false; 143 144 145 /* Enable extended register access */ 146 ast_open_key(ast); 147 ast_enable_mmio(dev); 148 149 /* Find out whether P2A works or whether to use device-tree */ 150 ast_detect_config_mode(dev, &scu_rev); 151 152 /* Identify chipset */ 153 if (pdev->revision >= 0x50) { 154 ast->chip = AST2600; 155 drm_info(dev, "AST 2600 detected\n"); 156 } else if (pdev->revision >= 0x40) { 157 ast->chip = AST2500; 158 drm_info(dev, "AST 2500 detected\n"); 159 } else if (pdev->revision >= 0x30) { 160 ast->chip = AST2400; 161 drm_info(dev, "AST 2400 detected\n"); 162 } else if (pdev->revision >= 0x20) { 163 ast->chip = AST2300; 164 drm_info(dev, "AST 2300 detected\n"); 165 } else if (pdev->revision >= 0x10) { 166 switch (scu_rev & 0x0300) { 167 case 0x0200: 168 ast->chip = AST1100; 169 drm_info(dev, "AST 1100 detected\n"); 170 break; 171 case 0x0100: 172 ast->chip = AST2200; 173 drm_info(dev, "AST 2200 detected\n"); 174 break; 175 case 0x0000: 176 ast->chip = AST2150; 177 drm_info(dev, "AST 2150 detected\n"); 178 break; 179 default: 180 ast->chip = AST2100; 181 drm_info(dev, "AST 2100 detected\n"); 182 break; 183 } 184 ast->vga2_clone = false; 185 } else { 186 ast->chip = AST2000; 187 drm_info(dev, "AST 2000 detected\n"); 188 } 189 190 /* Check if we support wide screen */ 191 switch (ast->chip) { 192 case AST2000: 193 ast->support_wide_screen = false; 194 break; 195 default: 196 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 197 if (!(jreg & 0x80)) 198 ast->support_wide_screen = true; 199 else if (jreg & 0x01) 200 ast->support_wide_screen = true; 201 else { 202 ast->support_wide_screen = false; 203 if (ast->chip == AST2300 && 204 (scu_rev & 0x300) == 0x0) /* ast1300 */ 205 ast->support_wide_screen = true; 206 if (ast->chip == AST2400 && 207 (scu_rev & 0x300) == 0x100) /* ast1400 */ 208 ast->support_wide_screen = true; 209 if (ast->chip == AST2500 && 210 scu_rev == 0x100) /* ast2510 */ 211 ast->support_wide_screen = true; 212 if (ast->chip == AST2600) /* ast2600 */ 213 ast->support_wide_screen = true; 214 } 215 break; 216 } 217 218 /* Check 3rd Tx option (digital output afaik) */ 219 ast->tx_chip_type = AST_TX_NONE; 220 221 /* 222 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 223 * enabled, in that case, assume we have a SIL164 TMDS transmitter 224 * 225 * Don't make that assumption if we the chip wasn't enabled and 226 * is at power-on reset, otherwise we'll incorrectly "detect" a 227 * SIL164 when there is none. 228 */ 229 if (!*need_post) { 230 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); 231 if (jreg & 0x80) 232 ast->tx_chip_type = AST_TX_SIL164; 233 } 234 235 if ((ast->chip == AST2300) || (ast->chip == AST2400)) { 236 /* 237 * On AST2300 and 2400, look the configuration set by the SoC in 238 * the SOC scratch register #1 bits 11:8 (interestingly marked 239 * as "reserved" in the spec) 240 */ 241 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 242 switch (jreg) { 243 case 0x04: 244 ast->tx_chip_type = AST_TX_SIL164; 245 break; 246 case 0x08: 247 ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL); 248 if (ast->dp501_fw_addr) { 249 /* backup firmware */ 250 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { 251 drmm_kfree(dev, ast->dp501_fw_addr); 252 ast->dp501_fw_addr = NULL; 253 } 254 } 255 fallthrough; 256 case 0x0c: 257 ast->tx_chip_type = AST_TX_DP501; 258 } 259 } 260 261 /* Print stuff for diagnostic purposes */ 262 switch(ast->tx_chip_type) { 263 case AST_TX_SIL164: 264 drm_info(dev, "Using Sil164 TMDS transmitter\n"); 265 break; 266 case AST_TX_DP501: 267 drm_info(dev, "Using DP501 DisplayPort transmitter\n"); 268 break; 269 default: 270 drm_info(dev, "Analog VGA only\n"); 271 } 272 return 0; 273 } 274 275 static int ast_get_dram_info(struct drm_device *dev) 276 { 277 struct device_node *np = dev->dev->of_node; 278 struct ast_private *ast = to_ast_private(dev); 279 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; 280 uint32_t denum, num, div, ref_pll, dsel; 281 282 switch (ast->config_mode) { 283 case ast_use_dt: 284 /* 285 * If some properties are missing, use reasonable 286 * defaults for AST2400 287 */ 288 if (of_property_read_u32(np, "aspeed,mcr-configuration", 289 &mcr_cfg)) 290 mcr_cfg = 0x00000577; 291 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", 292 &mcr_scu_mpll)) 293 mcr_scu_mpll = 0x000050C0; 294 if (of_property_read_u32(np, "aspeed,mcr-scu-strap", 295 &mcr_scu_strap)) 296 mcr_scu_strap = 0; 297 break; 298 case ast_use_p2a: 299 ast_write32(ast, 0xf004, 0x1e6e0000); 300 ast_write32(ast, 0xf000, 0x1); 301 mcr_cfg = ast_read32(ast, 0x10004); 302 mcr_scu_mpll = ast_read32(ast, 0x10120); 303 mcr_scu_strap = ast_read32(ast, 0x10170); 304 break; 305 case ast_use_defaults: 306 default: 307 ast->dram_bus_width = 16; 308 ast->dram_type = AST_DRAM_1Gx16; 309 if (ast->chip == AST2500) 310 ast->mclk = 800; 311 else 312 ast->mclk = 396; 313 return 0; 314 } 315 316 if (mcr_cfg & 0x40) 317 ast->dram_bus_width = 16; 318 else 319 ast->dram_bus_width = 32; 320 321 if (ast->chip == AST2500) { 322 switch (mcr_cfg & 0x03) { 323 case 0: 324 ast->dram_type = AST_DRAM_1Gx16; 325 break; 326 default: 327 case 1: 328 ast->dram_type = AST_DRAM_2Gx16; 329 break; 330 case 2: 331 ast->dram_type = AST_DRAM_4Gx16; 332 break; 333 case 3: 334 ast->dram_type = AST_DRAM_8Gx16; 335 break; 336 } 337 } else if (ast->chip == AST2300 || ast->chip == AST2400) { 338 switch (mcr_cfg & 0x03) { 339 case 0: 340 ast->dram_type = AST_DRAM_512Mx16; 341 break; 342 default: 343 case 1: 344 ast->dram_type = AST_DRAM_1Gx16; 345 break; 346 case 2: 347 ast->dram_type = AST_DRAM_2Gx16; 348 break; 349 case 3: 350 ast->dram_type = AST_DRAM_4Gx16; 351 break; 352 } 353 } else { 354 switch (mcr_cfg & 0x0c) { 355 case 0: 356 case 4: 357 ast->dram_type = AST_DRAM_512Mx16; 358 break; 359 case 8: 360 if (mcr_cfg & 0x40) 361 ast->dram_type = AST_DRAM_1Gx16; 362 else 363 ast->dram_type = AST_DRAM_512Mx32; 364 break; 365 case 0xc: 366 ast->dram_type = AST_DRAM_1Gx32; 367 break; 368 } 369 } 370 371 if (mcr_scu_strap & 0x2000) 372 ref_pll = 14318; 373 else 374 ref_pll = 12000; 375 376 denum = mcr_scu_mpll & 0x1f; 377 num = (mcr_scu_mpll & 0x3fe0) >> 5; 378 dsel = (mcr_scu_mpll & 0xc000) >> 14; 379 switch (dsel) { 380 case 3: 381 div = 0x4; 382 break; 383 case 2: 384 case 1: 385 div = 0x2; 386 break; 387 default: 388 div = 0x1; 389 break; 390 } 391 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); 392 return 0; 393 } 394 395 /* 396 * Run this function as part of the HW device cleanup; not 397 * when the DRM device gets released. 398 */ 399 static void ast_device_release(void *data) 400 { 401 struct ast_private *ast = data; 402 403 /* enable standard VGA decode */ 404 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); 405 } 406 407 struct ast_private *ast_device_create(const struct drm_driver *drv, 408 struct pci_dev *pdev, 409 unsigned long flags) 410 { 411 struct drm_device *dev; 412 struct ast_private *ast; 413 bool need_post; 414 int ret = 0; 415 416 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base); 417 if (IS_ERR(ast)) 418 return ast; 419 dev = &ast->base; 420 421 pci_set_drvdata(pdev, dev); 422 423 ast->regs = pcim_iomap(pdev, 1, 0); 424 if (!ast->regs) 425 return ERR_PTR(-EIO); 426 427 /* 428 * If we don't have IO space at all, use MMIO now and 429 * assume the chip has MMIO enabled by default (rev 0x20 430 * and higher). 431 */ 432 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { 433 drm_info(dev, "platform has no IO space, trying MMIO\n"); 434 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 435 } 436 437 /* "map" IO regs if the above hasn't done so already */ 438 if (!ast->ioregs) { 439 ast->ioregs = pcim_iomap(pdev, 2, 0); 440 if (!ast->ioregs) 441 return ERR_PTR(-EIO); 442 } 443 444 ast_detect_chip(dev, &need_post); 445 446 ret = ast_get_dram_info(dev); 447 if (ret) 448 return ERR_PTR(ret); 449 450 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n", 451 ast->mclk, ast->dram_type, ast->dram_bus_width); 452 453 if (need_post) 454 ast_post_gpu(dev); 455 456 ret = ast_mm_init(ast); 457 if (ret) 458 return ERR_PTR(ret); 459 460 /* map reserved buffer */ 461 ast->dp501_fw_buf = NULL; 462 if (dev->vram_mm->vram_size < pci_resource_len(pdev, 0)) { 463 ast->dp501_fw_buf = pci_iomap_range(pdev, 0, dev->vram_mm->vram_size, 0); 464 if (!ast->dp501_fw_buf) 465 drm_info(dev, "failed to map reserved buffer!\n"); 466 } 467 468 ret = ast_mode_config_init(ast); 469 if (ret) 470 return ERR_PTR(ret); 471 472 ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast); 473 if (ret) 474 return ERR_PTR(ret); 475 476 return ast; 477 } 478