1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/pci.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_drv.h> 34 #include <drm/drm_gem.h> 35 #include <drm/drm_gem_vram_helper.h> 36 #include <drm/drm_managed.h> 37 38 #include "ast_drv.h" 39 40 void ast_set_index_reg_mask(struct ast_private *ast, 41 uint32_t base, uint8_t index, 42 uint8_t mask, uint8_t val) 43 { 44 u8 tmp; 45 ast_io_write8(ast, base, index); 46 tmp = (ast_io_read8(ast, base + 1) & mask) | val; 47 ast_set_index_reg(ast, base, index, tmp); 48 } 49 50 uint8_t ast_get_index_reg(struct ast_private *ast, 51 uint32_t base, uint8_t index) 52 { 53 uint8_t ret; 54 ast_io_write8(ast, base, index); 55 ret = ast_io_read8(ast, base + 1); 56 return ret; 57 } 58 59 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 60 uint32_t base, uint8_t index, uint8_t mask) 61 { 62 uint8_t ret; 63 ast_io_write8(ast, base, index); 64 ret = ast_io_read8(ast, base + 1) & mask; 65 return ret; 66 } 67 68 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) 69 { 70 struct device_node *np = dev->dev->of_node; 71 struct ast_private *ast = to_ast_private(dev); 72 struct pci_dev *pdev = to_pci_dev(dev->dev); 73 uint32_t data, jregd0, jregd1; 74 75 /* Defaults */ 76 ast->config_mode = ast_use_defaults; 77 *scu_rev = 0xffffffff; 78 79 /* Check if we have device-tree properties */ 80 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", 81 scu_rev)) { 82 /* We do, disable P2A access */ 83 ast->config_mode = ast_use_dt; 84 drm_info(dev, "Using device-tree for configuration\n"); 85 return; 86 } 87 88 /* Not all families have a P2A bridge */ 89 if (pdev->device != PCI_CHIP_AST2000) 90 return; 91 92 /* 93 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 94 * is disabled. We force using P2A if VGA only mode bit 95 * is set D[7] 96 */ 97 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 98 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 99 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { 100 /* Double check it's actually working */ 101 data = ast_read32(ast, 0xf004); 102 if ((data != 0xFFFFFFFF) && (data != 0x00)) { 103 /* P2A works, grab silicon revision */ 104 ast->config_mode = ast_use_p2a; 105 106 drm_info(dev, "Using P2A bridge for configuration\n"); 107 108 /* Read SCU7c (silicon revision register) */ 109 ast_write32(ast, 0xf004, 0x1e6e0000); 110 ast_write32(ast, 0xf000, 0x1); 111 *scu_rev = ast_read32(ast, 0x1207c); 112 return; 113 } 114 } 115 116 /* We have a P2A bridge but it's disabled */ 117 drm_info(dev, "P2A bridge disabled, using default configuration\n"); 118 } 119 120 static int ast_detect_chip(struct drm_device *dev, bool *need_post) 121 { 122 struct ast_private *ast = to_ast_private(dev); 123 struct pci_dev *pdev = to_pci_dev(dev->dev); 124 uint32_t jreg, scu_rev; 125 126 /* 127 * If VGA isn't enabled, we need to enable now or subsequent 128 * access to the scratch registers will fail. We also inform 129 * our caller that it needs to POST the chip 130 * (Assumption: VGA not enabled -> need to POST) 131 */ 132 if (!ast_is_vga_enabled(dev)) { 133 ast_enable_vga(dev); 134 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n"); 135 *need_post = true; 136 } else 137 *need_post = false; 138 139 140 /* Enable extended register access */ 141 ast_open_key(ast); 142 ast_enable_mmio(dev); 143 144 /* Find out whether P2A works or whether to use device-tree */ 145 ast_detect_config_mode(dev, &scu_rev); 146 147 /* Identify chipset */ 148 if (pdev->revision >= 0x50) { 149 ast->chip = AST2600; 150 drm_info(dev, "AST 2600 detected\n"); 151 } else if (pdev->revision >= 0x40) { 152 ast->chip = AST2500; 153 drm_info(dev, "AST 2500 detected\n"); 154 } else if (pdev->revision >= 0x30) { 155 ast->chip = AST2400; 156 drm_info(dev, "AST 2400 detected\n"); 157 } else if (pdev->revision >= 0x20) { 158 ast->chip = AST2300; 159 drm_info(dev, "AST 2300 detected\n"); 160 } else if (pdev->revision >= 0x10) { 161 switch (scu_rev & 0x0300) { 162 case 0x0200: 163 ast->chip = AST1100; 164 drm_info(dev, "AST 1100 detected\n"); 165 break; 166 case 0x0100: 167 ast->chip = AST2200; 168 drm_info(dev, "AST 2200 detected\n"); 169 break; 170 case 0x0000: 171 ast->chip = AST2150; 172 drm_info(dev, "AST 2150 detected\n"); 173 break; 174 default: 175 ast->chip = AST2100; 176 drm_info(dev, "AST 2100 detected\n"); 177 break; 178 } 179 ast->vga2_clone = false; 180 } else { 181 ast->chip = AST2000; 182 drm_info(dev, "AST 2000 detected\n"); 183 } 184 185 /* Check if we support wide screen */ 186 switch (ast->chip) { 187 case AST2000: 188 ast->support_wide_screen = false; 189 break; 190 default: 191 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 192 if (!(jreg & 0x80)) 193 ast->support_wide_screen = true; 194 else if (jreg & 0x01) 195 ast->support_wide_screen = true; 196 else { 197 ast->support_wide_screen = false; 198 if (ast->chip == AST2300 && 199 (scu_rev & 0x300) == 0x0) /* ast1300 */ 200 ast->support_wide_screen = true; 201 if (ast->chip == AST2400 && 202 (scu_rev & 0x300) == 0x100) /* ast1400 */ 203 ast->support_wide_screen = true; 204 if (ast->chip == AST2500 && 205 scu_rev == 0x100) /* ast2510 */ 206 ast->support_wide_screen = true; 207 } 208 break; 209 } 210 211 /* Check 3rd Tx option (digital output afaik) */ 212 ast->tx_chip_type = AST_TX_NONE; 213 214 /* 215 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 216 * enabled, in that case, assume we have a SIL164 TMDS transmitter 217 * 218 * Don't make that assumption if we the chip wasn't enabled and 219 * is at power-on reset, otherwise we'll incorrectly "detect" a 220 * SIL164 when there is none. 221 */ 222 if (!*need_post) { 223 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); 224 if (jreg & 0x80) 225 ast->tx_chip_type = AST_TX_SIL164; 226 } 227 228 if ((ast->chip == AST2300) || (ast->chip == AST2400)) { 229 /* 230 * On AST2300 and 2400, look the configuration set by the SoC in 231 * the SOC scratch register #1 bits 11:8 (interestingly marked 232 * as "reserved" in the spec) 233 */ 234 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 235 switch (jreg) { 236 case 0x04: 237 ast->tx_chip_type = AST_TX_SIL164; 238 break; 239 case 0x08: 240 ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL); 241 if (ast->dp501_fw_addr) { 242 /* backup firmware */ 243 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { 244 drmm_kfree(dev, ast->dp501_fw_addr); 245 ast->dp501_fw_addr = NULL; 246 } 247 } 248 fallthrough; 249 case 0x0c: 250 ast->tx_chip_type = AST_TX_DP501; 251 } 252 } 253 254 /* Print stuff for diagnostic purposes */ 255 switch(ast->tx_chip_type) { 256 case AST_TX_SIL164: 257 drm_info(dev, "Using Sil164 TMDS transmitter\n"); 258 break; 259 case AST_TX_DP501: 260 drm_info(dev, "Using DP501 DisplayPort transmitter\n"); 261 break; 262 default: 263 drm_info(dev, "Analog VGA only\n"); 264 } 265 return 0; 266 } 267 268 static int ast_get_dram_info(struct drm_device *dev) 269 { 270 struct device_node *np = dev->dev->of_node; 271 struct ast_private *ast = to_ast_private(dev); 272 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; 273 uint32_t denum, num, div, ref_pll, dsel; 274 275 switch (ast->config_mode) { 276 case ast_use_dt: 277 /* 278 * If some properties are missing, use reasonable 279 * defaults for AST2400 280 */ 281 if (of_property_read_u32(np, "aspeed,mcr-configuration", 282 &mcr_cfg)) 283 mcr_cfg = 0x00000577; 284 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", 285 &mcr_scu_mpll)) 286 mcr_scu_mpll = 0x000050C0; 287 if (of_property_read_u32(np, "aspeed,mcr-scu-strap", 288 &mcr_scu_strap)) 289 mcr_scu_strap = 0; 290 break; 291 case ast_use_p2a: 292 ast_write32(ast, 0xf004, 0x1e6e0000); 293 ast_write32(ast, 0xf000, 0x1); 294 mcr_cfg = ast_read32(ast, 0x10004); 295 mcr_scu_mpll = ast_read32(ast, 0x10120); 296 mcr_scu_strap = ast_read32(ast, 0x10170); 297 break; 298 case ast_use_defaults: 299 default: 300 ast->dram_bus_width = 16; 301 ast->dram_type = AST_DRAM_1Gx16; 302 if (ast->chip == AST2500) 303 ast->mclk = 800; 304 else 305 ast->mclk = 396; 306 return 0; 307 } 308 309 if (mcr_cfg & 0x40) 310 ast->dram_bus_width = 16; 311 else 312 ast->dram_bus_width = 32; 313 314 if (ast->chip == AST2500) { 315 switch (mcr_cfg & 0x03) { 316 case 0: 317 ast->dram_type = AST_DRAM_1Gx16; 318 break; 319 default: 320 case 1: 321 ast->dram_type = AST_DRAM_2Gx16; 322 break; 323 case 2: 324 ast->dram_type = AST_DRAM_4Gx16; 325 break; 326 case 3: 327 ast->dram_type = AST_DRAM_8Gx16; 328 break; 329 } 330 } else if (ast->chip == AST2300 || ast->chip == AST2400) { 331 switch (mcr_cfg & 0x03) { 332 case 0: 333 ast->dram_type = AST_DRAM_512Mx16; 334 break; 335 default: 336 case 1: 337 ast->dram_type = AST_DRAM_1Gx16; 338 break; 339 case 2: 340 ast->dram_type = AST_DRAM_2Gx16; 341 break; 342 case 3: 343 ast->dram_type = AST_DRAM_4Gx16; 344 break; 345 } 346 } else { 347 switch (mcr_cfg & 0x0c) { 348 case 0: 349 case 4: 350 ast->dram_type = AST_DRAM_512Mx16; 351 break; 352 case 8: 353 if (mcr_cfg & 0x40) 354 ast->dram_type = AST_DRAM_1Gx16; 355 else 356 ast->dram_type = AST_DRAM_512Mx32; 357 break; 358 case 0xc: 359 ast->dram_type = AST_DRAM_1Gx32; 360 break; 361 } 362 } 363 364 if (mcr_scu_strap & 0x2000) 365 ref_pll = 14318; 366 else 367 ref_pll = 12000; 368 369 denum = mcr_scu_mpll & 0x1f; 370 num = (mcr_scu_mpll & 0x3fe0) >> 5; 371 dsel = (mcr_scu_mpll & 0xc000) >> 14; 372 switch (dsel) { 373 case 3: 374 div = 0x4; 375 break; 376 case 2: 377 case 1: 378 div = 0x2; 379 break; 380 default: 381 div = 0x1; 382 break; 383 } 384 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); 385 return 0; 386 } 387 388 /* 389 * Run this function as part of the HW device cleanup; not 390 * when the DRM device gets released. 391 */ 392 static void ast_device_release(void *data) 393 { 394 struct ast_private *ast = data; 395 396 /* enable standard VGA decode */ 397 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); 398 } 399 400 struct ast_private *ast_device_create(const struct drm_driver *drv, 401 struct pci_dev *pdev, 402 unsigned long flags) 403 { 404 struct drm_device *dev; 405 struct ast_private *ast; 406 bool need_post; 407 int ret = 0; 408 409 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base); 410 if (IS_ERR(ast)) 411 return ast; 412 dev = &ast->base; 413 414 pci_set_drvdata(pdev, dev); 415 416 ast->regs = pcim_iomap(pdev, 1, 0); 417 if (!ast->regs) 418 return ERR_PTR(-EIO); 419 420 /* 421 * If we don't have IO space at all, use MMIO now and 422 * assume the chip has MMIO enabled by default (rev 0x20 423 * and higher). 424 */ 425 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { 426 drm_info(dev, "platform has no IO space, trying MMIO\n"); 427 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 428 } 429 430 /* "map" IO regs if the above hasn't done so already */ 431 if (!ast->ioregs) { 432 ast->ioregs = pcim_iomap(pdev, 2, 0); 433 if (!ast->ioregs) 434 return ERR_PTR(-EIO); 435 } 436 437 ast_detect_chip(dev, &need_post); 438 439 ret = ast_get_dram_info(dev); 440 if (ret) 441 return ERR_PTR(ret); 442 443 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n", 444 ast->mclk, ast->dram_type, ast->dram_bus_width); 445 446 if (need_post) 447 ast_post_gpu(dev); 448 449 ret = ast_mm_init(ast); 450 if (ret) 451 return ERR_PTR(ret); 452 453 /* map reserved buffer */ 454 ast->dp501_fw_buf = NULL; 455 if (dev->vram_mm->vram_size < pci_resource_len(pdev, 0)) { 456 ast->dp501_fw_buf = pci_iomap_range(pdev, 0, dev->vram_mm->vram_size, 0); 457 if (!ast->dp501_fw_buf) 458 drm_info(dev, "failed to map reserved buffer!\n"); 459 } 460 461 ret = ast_mode_config_init(ast); 462 if (ret) 463 return ERR_PTR(ret); 464 465 ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast); 466 if (ret) 467 return ERR_PTR(ret); 468 469 return ast; 470 } 471