1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/pci.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_gem.h> 34 #include <drm/drm_gem_framebuffer_helper.h> 35 #include <drm/drm_gem_vram_helper.h> 36 37 #include "ast_drv.h" 38 39 void ast_set_index_reg_mask(struct ast_private *ast, 40 uint32_t base, uint8_t index, 41 uint8_t mask, uint8_t val) 42 { 43 u8 tmp; 44 ast_io_write8(ast, base, index); 45 tmp = (ast_io_read8(ast, base + 1) & mask) | val; 46 ast_set_index_reg(ast, base, index, tmp); 47 } 48 49 uint8_t ast_get_index_reg(struct ast_private *ast, 50 uint32_t base, uint8_t index) 51 { 52 uint8_t ret; 53 ast_io_write8(ast, base, index); 54 ret = ast_io_read8(ast, base + 1); 55 return ret; 56 } 57 58 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 59 uint32_t base, uint8_t index, uint8_t mask) 60 { 61 uint8_t ret; 62 ast_io_write8(ast, base, index); 63 ret = ast_io_read8(ast, base + 1) & mask; 64 return ret; 65 } 66 67 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) 68 { 69 struct device_node *np = dev->pdev->dev.of_node; 70 struct ast_private *ast = to_ast_private(dev); 71 uint32_t data, jregd0, jregd1; 72 73 /* Defaults */ 74 ast->config_mode = ast_use_defaults; 75 *scu_rev = 0xffffffff; 76 77 /* Check if we have device-tree properties */ 78 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", 79 scu_rev)) { 80 /* We do, disable P2A access */ 81 ast->config_mode = ast_use_dt; 82 drm_info(dev, "Using device-tree for configuration\n"); 83 return; 84 } 85 86 /* Not all families have a P2A bridge */ 87 if (dev->pdev->device != PCI_CHIP_AST2000) 88 return; 89 90 /* 91 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 92 * is disabled. We force using P2A if VGA only mode bit 93 * is set D[7] 94 */ 95 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 96 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 97 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { 98 /* Double check it's actually working */ 99 data = ast_read32(ast, 0xf004); 100 if (data != 0xFFFFFFFF) { 101 /* P2A works, grab silicon revision */ 102 ast->config_mode = ast_use_p2a; 103 104 drm_info(dev, "Using P2A bridge for configuration\n"); 105 106 /* Read SCU7c (silicon revision register) */ 107 ast_write32(ast, 0xf004, 0x1e6e0000); 108 ast_write32(ast, 0xf000, 0x1); 109 *scu_rev = ast_read32(ast, 0x1207c); 110 return; 111 } 112 } 113 114 /* We have a P2A bridge but it's disabled */ 115 drm_info(dev, "P2A bridge disabled, using default configuration\n"); 116 } 117 118 static int ast_detect_chip(struct drm_device *dev, bool *need_post) 119 { 120 struct ast_private *ast = to_ast_private(dev); 121 uint32_t jreg, scu_rev; 122 123 /* 124 * If VGA isn't enabled, we need to enable now or subsequent 125 * access to the scratch registers will fail. We also inform 126 * our caller that it needs to POST the chip 127 * (Assumption: VGA not enabled -> need to POST) 128 */ 129 if (!ast_is_vga_enabled(dev)) { 130 ast_enable_vga(dev); 131 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n"); 132 *need_post = true; 133 } else 134 *need_post = false; 135 136 137 /* Enable extended register access */ 138 ast_open_key(ast); 139 ast_enable_mmio(dev); 140 141 /* Find out whether P2A works or whether to use device-tree */ 142 ast_detect_config_mode(dev, &scu_rev); 143 144 /* Identify chipset */ 145 if (dev->pdev->revision >= 0x40) { 146 ast->chip = AST2500; 147 drm_info(dev, "AST 2500 detected\n"); 148 } else if (dev->pdev->revision >= 0x30) { 149 ast->chip = AST2400; 150 drm_info(dev, "AST 2400 detected\n"); 151 } else if (dev->pdev->revision >= 0x20) { 152 ast->chip = AST2300; 153 drm_info(dev, "AST 2300 detected\n"); 154 } else if (dev->pdev->revision >= 0x10) { 155 switch (scu_rev & 0x0300) { 156 case 0x0200: 157 ast->chip = AST1100; 158 drm_info(dev, "AST 1100 detected\n"); 159 break; 160 case 0x0100: 161 ast->chip = AST2200; 162 drm_info(dev, "AST 2200 detected\n"); 163 break; 164 case 0x0000: 165 ast->chip = AST2150; 166 drm_info(dev, "AST 2150 detected\n"); 167 break; 168 default: 169 ast->chip = AST2100; 170 drm_info(dev, "AST 2100 detected\n"); 171 break; 172 } 173 ast->vga2_clone = false; 174 } else { 175 ast->chip = AST2000; 176 drm_info(dev, "AST 2000 detected\n"); 177 } 178 179 /* Check if we support wide screen */ 180 switch (ast->chip) { 181 case AST2000: 182 ast->support_wide_screen = false; 183 break; 184 default: 185 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 186 if (!(jreg & 0x80)) 187 ast->support_wide_screen = true; 188 else if (jreg & 0x01) 189 ast->support_wide_screen = true; 190 else { 191 ast->support_wide_screen = false; 192 if (ast->chip == AST2300 && 193 (scu_rev & 0x300) == 0x0) /* ast1300 */ 194 ast->support_wide_screen = true; 195 if (ast->chip == AST2400 && 196 (scu_rev & 0x300) == 0x100) /* ast1400 */ 197 ast->support_wide_screen = true; 198 if (ast->chip == AST2500 && 199 scu_rev == 0x100) /* ast2510 */ 200 ast->support_wide_screen = true; 201 } 202 break; 203 } 204 205 /* Check 3rd Tx option (digital output afaik) */ 206 ast->tx_chip_type = AST_TX_NONE; 207 208 /* 209 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 210 * enabled, in that case, assume we have a SIL164 TMDS transmitter 211 * 212 * Don't make that assumption if we the chip wasn't enabled and 213 * is at power-on reset, otherwise we'll incorrectly "detect" a 214 * SIL164 when there is none. 215 */ 216 if (!*need_post) { 217 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); 218 if (jreg & 0x80) 219 ast->tx_chip_type = AST_TX_SIL164; 220 } 221 222 if ((ast->chip == AST2300) || (ast->chip == AST2400)) { 223 /* 224 * On AST2300 and 2400, look the configuration set by the SoC in 225 * the SOC scratch register #1 bits 11:8 (interestingly marked 226 * as "reserved" in the spec) 227 */ 228 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 229 switch (jreg) { 230 case 0x04: 231 ast->tx_chip_type = AST_TX_SIL164; 232 break; 233 case 0x08: 234 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL); 235 if (ast->dp501_fw_addr) { 236 /* backup firmware */ 237 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { 238 kfree(ast->dp501_fw_addr); 239 ast->dp501_fw_addr = NULL; 240 } 241 } 242 /* fallthrough */ 243 case 0x0c: 244 ast->tx_chip_type = AST_TX_DP501; 245 } 246 } 247 248 /* Print stuff for diagnostic purposes */ 249 switch(ast->tx_chip_type) { 250 case AST_TX_SIL164: 251 drm_info(dev, "Using Sil164 TMDS transmitter\n"); 252 break; 253 case AST_TX_DP501: 254 drm_info(dev, "Using DP501 DisplayPort transmitter\n"); 255 break; 256 default: 257 drm_info(dev, "Analog VGA only\n"); 258 } 259 return 0; 260 } 261 262 static int ast_get_dram_info(struct drm_device *dev) 263 { 264 struct device_node *np = dev->pdev->dev.of_node; 265 struct ast_private *ast = to_ast_private(dev); 266 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; 267 uint32_t denum, num, div, ref_pll, dsel; 268 269 switch (ast->config_mode) { 270 case ast_use_dt: 271 /* 272 * If some properties are missing, use reasonable 273 * defaults for AST2400 274 */ 275 if (of_property_read_u32(np, "aspeed,mcr-configuration", 276 &mcr_cfg)) 277 mcr_cfg = 0x00000577; 278 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", 279 &mcr_scu_mpll)) 280 mcr_scu_mpll = 0x000050C0; 281 if (of_property_read_u32(np, "aspeed,mcr-scu-strap", 282 &mcr_scu_strap)) 283 mcr_scu_strap = 0; 284 break; 285 case ast_use_p2a: 286 ast_write32(ast, 0xf004, 0x1e6e0000); 287 ast_write32(ast, 0xf000, 0x1); 288 mcr_cfg = ast_read32(ast, 0x10004); 289 mcr_scu_mpll = ast_read32(ast, 0x10120); 290 mcr_scu_strap = ast_read32(ast, 0x10170); 291 break; 292 case ast_use_defaults: 293 default: 294 ast->dram_bus_width = 16; 295 ast->dram_type = AST_DRAM_1Gx16; 296 if (ast->chip == AST2500) 297 ast->mclk = 800; 298 else 299 ast->mclk = 396; 300 return 0; 301 } 302 303 if (mcr_cfg & 0x40) 304 ast->dram_bus_width = 16; 305 else 306 ast->dram_bus_width = 32; 307 308 if (ast->chip == AST2500) { 309 switch (mcr_cfg & 0x03) { 310 case 0: 311 ast->dram_type = AST_DRAM_1Gx16; 312 break; 313 default: 314 case 1: 315 ast->dram_type = AST_DRAM_2Gx16; 316 break; 317 case 2: 318 ast->dram_type = AST_DRAM_4Gx16; 319 break; 320 case 3: 321 ast->dram_type = AST_DRAM_8Gx16; 322 break; 323 } 324 } else if (ast->chip == AST2300 || ast->chip == AST2400) { 325 switch (mcr_cfg & 0x03) { 326 case 0: 327 ast->dram_type = AST_DRAM_512Mx16; 328 break; 329 default: 330 case 1: 331 ast->dram_type = AST_DRAM_1Gx16; 332 break; 333 case 2: 334 ast->dram_type = AST_DRAM_2Gx16; 335 break; 336 case 3: 337 ast->dram_type = AST_DRAM_4Gx16; 338 break; 339 } 340 } else { 341 switch (mcr_cfg & 0x0c) { 342 case 0: 343 case 4: 344 ast->dram_type = AST_DRAM_512Mx16; 345 break; 346 case 8: 347 if (mcr_cfg & 0x40) 348 ast->dram_type = AST_DRAM_1Gx16; 349 else 350 ast->dram_type = AST_DRAM_512Mx32; 351 break; 352 case 0xc: 353 ast->dram_type = AST_DRAM_1Gx32; 354 break; 355 } 356 } 357 358 if (mcr_scu_strap & 0x2000) 359 ref_pll = 14318; 360 else 361 ref_pll = 12000; 362 363 denum = mcr_scu_mpll & 0x1f; 364 num = (mcr_scu_mpll & 0x3fe0) >> 5; 365 dsel = (mcr_scu_mpll & 0xc000) >> 14; 366 switch (dsel) { 367 case 3: 368 div = 0x4; 369 break; 370 case 2: 371 case 1: 372 div = 0x2; 373 break; 374 default: 375 div = 0x1; 376 break; 377 } 378 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); 379 return 0; 380 } 381 382 static const struct drm_mode_config_funcs ast_mode_funcs = { 383 .fb_create = drm_gem_fb_create, 384 .mode_valid = drm_vram_helper_mode_valid, 385 .atomic_check = drm_atomic_helper_check, 386 .atomic_commit = drm_atomic_helper_commit, 387 }; 388 389 static u32 ast_get_vram_info(struct drm_device *dev) 390 { 391 struct ast_private *ast = to_ast_private(dev); 392 u8 jreg; 393 u32 vram_size; 394 ast_open_key(ast); 395 396 vram_size = AST_VIDMEM_DEFAULT_SIZE; 397 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); 398 switch (jreg & 3) { 399 case 0: vram_size = AST_VIDMEM_SIZE_8M; break; 400 case 1: vram_size = AST_VIDMEM_SIZE_16M; break; 401 case 2: vram_size = AST_VIDMEM_SIZE_32M; break; 402 case 3: vram_size = AST_VIDMEM_SIZE_64M; break; 403 } 404 405 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); 406 switch (jreg & 0x03) { 407 case 1: 408 vram_size -= 0x100000; 409 break; 410 case 2: 411 vram_size -= 0x200000; 412 break; 413 case 3: 414 vram_size -= 0x400000; 415 break; 416 } 417 418 return vram_size; 419 } 420 421 int ast_driver_load(struct drm_device *dev, unsigned long flags) 422 { 423 struct ast_private *ast; 424 bool need_post; 425 int ret = 0; 426 427 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL); 428 if (!ast) 429 return -ENOMEM; 430 431 dev->dev_private = ast; 432 ast->dev = dev; 433 434 ast->regs = pci_iomap(dev->pdev, 1, 0); 435 if (!ast->regs) { 436 ret = -EIO; 437 goto out_free; 438 } 439 440 /* 441 * If we don't have IO space at all, use MMIO now and 442 * assume the chip has MMIO enabled by default (rev 0x20 443 * and higher). 444 */ 445 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) { 446 drm_info(dev, "platform has no IO space, trying MMIO\n"); 447 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 448 } 449 450 /* "map" IO regs if the above hasn't done so already */ 451 if (!ast->ioregs) { 452 ast->ioregs = pci_iomap(dev->pdev, 2, 0); 453 if (!ast->ioregs) { 454 ret = -EIO; 455 goto out_free; 456 } 457 } 458 459 ast_detect_chip(dev, &need_post); 460 461 if (need_post) 462 ast_post_gpu(dev); 463 464 ret = ast_get_dram_info(dev); 465 if (ret) 466 goto out_free; 467 ast->vram_size = ast_get_vram_info(dev); 468 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n", 469 ast->mclk, ast->dram_type, 470 ast->dram_bus_width, ast->vram_size); 471 472 ret = ast_mm_init(ast); 473 if (ret) 474 goto out_free; 475 476 drm_mode_config_init(dev); 477 478 dev->mode_config.funcs = (void *)&ast_mode_funcs; 479 dev->mode_config.min_width = 0; 480 dev->mode_config.min_height = 0; 481 dev->mode_config.preferred_depth = 24; 482 dev->mode_config.prefer_shadow = 1; 483 dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0); 484 485 if (ast->chip == AST2100 || 486 ast->chip == AST2200 || 487 ast->chip == AST2300 || 488 ast->chip == AST2400 || 489 ast->chip == AST2500) { 490 dev->mode_config.max_width = 1920; 491 dev->mode_config.max_height = 2048; 492 } else { 493 dev->mode_config.max_width = 1600; 494 dev->mode_config.max_height = 1200; 495 } 496 497 ret = ast_mode_init(dev); 498 if (ret) 499 goto out_free; 500 501 drm_mode_config_reset(dev); 502 503 return 0; 504 out_free: 505 kfree(ast); 506 dev->dev_private = NULL; 507 return ret; 508 } 509 510 void ast_driver_unload(struct drm_device *dev) 511 { 512 struct ast_private *ast = to_ast_private(dev); 513 514 /* enable standard VGA decode */ 515 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); 516 517 ast_release_firmware(dev); 518 kfree(ast->dp501_fw_addr); 519 ast_mode_fini(dev); 520 drm_mode_config_cleanup(dev); 521 522 ast_mm_fini(ast); 523 kfree(ast); 524 } 525