1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/pci.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_drv.h> 33 #include <drm/drm_gem.h> 34 #include <drm/drm_managed.h> 35 36 #include "ast_drv.h" 37 38 static int ast_init_pci_config(struct pci_dev *pdev) 39 { 40 int err; 41 u16 pcis04; 42 43 err = pci_read_config_word(pdev, PCI_COMMAND, &pcis04); 44 if (err) 45 goto out; 46 47 pcis04 |= PCI_COMMAND_MEMORY | PCI_COMMAND_IO; 48 49 err = pci_write_config_word(pdev, PCI_COMMAND, pcis04); 50 51 out: 52 return pcibios_err_to_errno(err); 53 } 54 55 static bool ast_is_vga_enabled(struct drm_device *dev) 56 { 57 struct ast_device *ast = to_ast_device(dev); 58 u8 ch; 59 60 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); 61 62 return !!(ch & 0x01); 63 } 64 65 static void ast_enable_vga(struct drm_device *dev) 66 { 67 struct ast_device *ast = to_ast_device(dev); 68 69 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); 70 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); 71 } 72 73 /* 74 * Run this function as part of the HW device cleanup; not 75 * when the DRM device gets released. 76 */ 77 static void ast_enable_mmio_release(void *data) 78 { 79 struct ast_device *ast = data; 80 81 /* enable standard VGA decode */ 82 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); 83 } 84 85 static int ast_enable_mmio(struct ast_device *ast) 86 { 87 struct drm_device *dev = &ast->base; 88 89 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); 90 91 return devm_add_action_or_reset(dev->dev, ast_enable_mmio_release, ast); 92 } 93 94 static void ast_open_key(struct ast_device *ast) 95 { 96 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 97 } 98 99 static int ast_device_config_init(struct ast_device *ast) 100 { 101 struct drm_device *dev = &ast->base; 102 struct pci_dev *pdev = to_pci_dev(dev->dev); 103 struct device_node *np = dev->dev->of_node; 104 uint32_t scu_rev = 0xffffffff; 105 u32 data; 106 u8 jregd0, jregd1; 107 108 /* 109 * Find configuration mode and read SCU revision 110 */ 111 112 ast->config_mode = ast_use_defaults; 113 114 /* Check if we have device-tree properties */ 115 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) { 116 /* We do, disable P2A access */ 117 ast->config_mode = ast_use_dt; 118 scu_rev = data; 119 } else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge 120 /* 121 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 122 * is disabled. We force using P2A if VGA only mode bit 123 * is set D[7] 124 */ 125 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 126 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 127 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { 128 129 /* 130 * We have a P2A bridge and it is enabled. 131 */ 132 133 /* Patch AST2500/AST2510 */ 134 if ((pdev->revision & 0xf0) == 0x40) { 135 if (!(jregd0 & AST_VRAM_INIT_STATUS_MASK)) 136 ast_patch_ahb_2500(ast); 137 } 138 139 /* Double check that it's actually working */ 140 data = ast_read32(ast, 0xf004); 141 if ((data != 0xffffffff) && (data != 0x00)) { 142 ast->config_mode = ast_use_p2a; 143 144 /* Read SCU7c (silicon revision register) */ 145 ast_write32(ast, 0xf004, 0x1e6e0000); 146 ast_write32(ast, 0xf000, 0x1); 147 scu_rev = ast_read32(ast, 0x1207c); 148 } 149 } 150 } 151 152 switch (ast->config_mode) { 153 case ast_use_defaults: 154 drm_info(dev, "Using default configuration\n"); 155 break; 156 case ast_use_dt: 157 drm_info(dev, "Using device-tree for configuration\n"); 158 break; 159 case ast_use_p2a: 160 drm_info(dev, "Using P2A bridge for configuration\n"); 161 break; 162 } 163 164 /* 165 * Identify chipset 166 */ 167 168 if (pdev->revision >= 0x50) { 169 ast->chip = AST2600; 170 drm_info(dev, "AST 2600 detected\n"); 171 } else if (pdev->revision >= 0x40) { 172 switch (scu_rev & 0x300) { 173 case 0x0100: 174 ast->chip = AST2510; 175 drm_info(dev, "AST 2510 detected\n"); 176 break; 177 default: 178 ast->chip = AST2500; 179 drm_info(dev, "AST 2500 detected\n"); 180 } 181 } else if (pdev->revision >= 0x30) { 182 switch (scu_rev & 0x300) { 183 case 0x0100: 184 ast->chip = AST1400; 185 drm_info(dev, "AST 1400 detected\n"); 186 break; 187 default: 188 ast->chip = AST2400; 189 drm_info(dev, "AST 2400 detected\n"); 190 } 191 } else if (pdev->revision >= 0x20) { 192 switch (scu_rev & 0x300) { 193 case 0x0000: 194 ast->chip = AST1300; 195 drm_info(dev, "AST 1300 detected\n"); 196 break; 197 default: 198 ast->chip = AST2300; 199 drm_info(dev, "AST 2300 detected\n"); 200 break; 201 } 202 } else if (pdev->revision >= 0x10) { 203 switch (scu_rev & 0x0300) { 204 case 0x0200: 205 ast->chip = AST1100; 206 drm_info(dev, "AST 1100 detected\n"); 207 break; 208 case 0x0100: 209 ast->chip = AST2200; 210 drm_info(dev, "AST 2200 detected\n"); 211 break; 212 case 0x0000: 213 ast->chip = AST2150; 214 drm_info(dev, "AST 2150 detected\n"); 215 break; 216 default: 217 ast->chip = AST2100; 218 drm_info(dev, "AST 2100 detected\n"); 219 break; 220 } 221 } else { 222 ast->chip = AST2000; 223 drm_info(dev, "AST 2000 detected\n"); 224 } 225 226 return 0; 227 } 228 229 static void ast_detect_widescreen(struct ast_device *ast) 230 { 231 u8 jreg; 232 233 /* Check if we support wide screen */ 234 switch (AST_GEN(ast)) { 235 case 1: 236 ast->support_wide_screen = false; 237 break; 238 default: 239 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 240 if (!(jreg & 0x80)) 241 ast->support_wide_screen = true; 242 else if (jreg & 0x01) 243 ast->support_wide_screen = true; 244 else { 245 ast->support_wide_screen = false; 246 if (ast->chip == AST1300) 247 ast->support_wide_screen = true; 248 if (ast->chip == AST1400) 249 ast->support_wide_screen = true; 250 if (ast->chip == AST2510) 251 ast->support_wide_screen = true; 252 if (IS_AST_GEN7(ast)) 253 ast->support_wide_screen = true; 254 } 255 break; 256 } 257 } 258 259 static void ast_detect_tx_chip(struct ast_device *ast, bool need_post) 260 { 261 struct drm_device *dev = &ast->base; 262 u8 jreg; 263 264 /* Check 3rd Tx option (digital output afaik) */ 265 ast->tx_chip_types |= AST_TX_NONE_BIT; 266 267 /* 268 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 269 * enabled, in that case, assume we have a SIL164 TMDS transmitter 270 * 271 * Don't make that assumption if we the chip wasn't enabled and 272 * is at power-on reset, otherwise we'll incorrectly "detect" a 273 * SIL164 when there is none. 274 */ 275 if (!need_post) { 276 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); 277 if (jreg & 0x80) 278 ast->tx_chip_types = AST_TX_SIL164_BIT; 279 } 280 281 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) { 282 /* 283 * On AST GEN4+, look the configuration set by the SoC in 284 * the SOC scratch register #1 bits 11:8 (interestingly marked 285 * as "reserved" in the spec) 286 */ 287 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 288 switch (jreg) { 289 case 0x04: 290 ast->tx_chip_types = AST_TX_SIL164_BIT; 291 break; 292 case 0x08: 293 ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL); 294 if (ast->dp501_fw_addr) { 295 /* backup firmware */ 296 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { 297 drmm_kfree(dev, ast->dp501_fw_addr); 298 ast->dp501_fw_addr = NULL; 299 } 300 } 301 fallthrough; 302 case 0x0c: 303 ast->tx_chip_types = AST_TX_DP501_BIT; 304 } 305 } else if (IS_AST_GEN7(ast)) { 306 if (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, TX_TYPE_MASK) == 307 ASTDP_DPMCU_TX) { 308 ast->tx_chip_types = AST_TX_ASTDP_BIT; 309 ast_dp_launch(&ast->base); 310 } 311 } 312 313 /* Print stuff for diagnostic purposes */ 314 if (ast->tx_chip_types & AST_TX_NONE_BIT) 315 drm_info(dev, "Using analog VGA\n"); 316 if (ast->tx_chip_types & AST_TX_SIL164_BIT) 317 drm_info(dev, "Using Sil164 TMDS transmitter\n"); 318 if (ast->tx_chip_types & AST_TX_DP501_BIT) 319 drm_info(dev, "Using DP501 DisplayPort transmitter\n"); 320 if (ast->tx_chip_types & AST_TX_ASTDP_BIT) 321 drm_info(dev, "Using ASPEED DisplayPort transmitter\n"); 322 } 323 324 static int ast_get_dram_info(struct drm_device *dev) 325 { 326 struct device_node *np = dev->dev->of_node; 327 struct ast_device *ast = to_ast_device(dev); 328 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; 329 uint32_t denum, num, div, ref_pll, dsel; 330 331 switch (ast->config_mode) { 332 case ast_use_dt: 333 /* 334 * If some properties are missing, use reasonable 335 * defaults for GEN5 336 */ 337 if (of_property_read_u32(np, "aspeed,mcr-configuration", 338 &mcr_cfg)) 339 mcr_cfg = 0x00000577; 340 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", 341 &mcr_scu_mpll)) 342 mcr_scu_mpll = 0x000050C0; 343 if (of_property_read_u32(np, "aspeed,mcr-scu-strap", 344 &mcr_scu_strap)) 345 mcr_scu_strap = 0; 346 break; 347 case ast_use_p2a: 348 ast_write32(ast, 0xf004, 0x1e6e0000); 349 ast_write32(ast, 0xf000, 0x1); 350 mcr_cfg = ast_read32(ast, 0x10004); 351 mcr_scu_mpll = ast_read32(ast, 0x10120); 352 mcr_scu_strap = ast_read32(ast, 0x10170); 353 break; 354 case ast_use_defaults: 355 default: 356 ast->dram_bus_width = 16; 357 ast->dram_type = AST_DRAM_1Gx16; 358 if (IS_AST_GEN6(ast)) 359 ast->mclk = 800; 360 else 361 ast->mclk = 396; 362 return 0; 363 } 364 365 if (mcr_cfg & 0x40) 366 ast->dram_bus_width = 16; 367 else 368 ast->dram_bus_width = 32; 369 370 if (IS_AST_GEN6(ast)) { 371 switch (mcr_cfg & 0x03) { 372 case 0: 373 ast->dram_type = AST_DRAM_1Gx16; 374 break; 375 default: 376 case 1: 377 ast->dram_type = AST_DRAM_2Gx16; 378 break; 379 case 2: 380 ast->dram_type = AST_DRAM_4Gx16; 381 break; 382 case 3: 383 ast->dram_type = AST_DRAM_8Gx16; 384 break; 385 } 386 } else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast)) { 387 switch (mcr_cfg & 0x03) { 388 case 0: 389 ast->dram_type = AST_DRAM_512Mx16; 390 break; 391 default: 392 case 1: 393 ast->dram_type = AST_DRAM_1Gx16; 394 break; 395 case 2: 396 ast->dram_type = AST_DRAM_2Gx16; 397 break; 398 case 3: 399 ast->dram_type = AST_DRAM_4Gx16; 400 break; 401 } 402 } else { 403 switch (mcr_cfg & 0x0c) { 404 case 0: 405 case 4: 406 ast->dram_type = AST_DRAM_512Mx16; 407 break; 408 case 8: 409 if (mcr_cfg & 0x40) 410 ast->dram_type = AST_DRAM_1Gx16; 411 else 412 ast->dram_type = AST_DRAM_512Mx32; 413 break; 414 case 0xc: 415 ast->dram_type = AST_DRAM_1Gx32; 416 break; 417 } 418 } 419 420 if (mcr_scu_strap & 0x2000) 421 ref_pll = 14318; 422 else 423 ref_pll = 12000; 424 425 denum = mcr_scu_mpll & 0x1f; 426 num = (mcr_scu_mpll & 0x3fe0) >> 5; 427 dsel = (mcr_scu_mpll & 0xc000) >> 14; 428 switch (dsel) { 429 case 3: 430 div = 0x4; 431 break; 432 case 2: 433 case 1: 434 div = 0x2; 435 break; 436 default: 437 div = 0x1; 438 break; 439 } 440 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); 441 return 0; 442 } 443 444 struct ast_device *ast_device_create(const struct drm_driver *drv, 445 struct pci_dev *pdev, 446 unsigned long flags) 447 { 448 struct drm_device *dev; 449 struct ast_device *ast; 450 bool need_post = false; 451 int ret = 0; 452 453 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base); 454 if (IS_ERR(ast)) 455 return ast; 456 dev = &ast->base; 457 458 pci_set_drvdata(pdev, dev); 459 460 ret = drmm_mutex_init(dev, &ast->ioregs_lock); 461 if (ret) 462 return ERR_PTR(ret); 463 464 ast->regs = pcim_iomap(pdev, 1, 0); 465 if (!ast->regs) 466 return ERR_PTR(-EIO); 467 468 /* 469 * After AST2500, MMIO is enabled by default, and it should be adopted 470 * to be compatible with Arm. 471 */ 472 if (pdev->revision >= 0x40) { 473 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 474 } else if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { 475 drm_info(dev, "platform has no IO space, trying MMIO\n"); 476 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 477 } 478 479 /* "map" IO regs if the above hasn't done so already */ 480 if (!ast->ioregs) { 481 ast->ioregs = pcim_iomap(pdev, 2, 0); 482 if (!ast->ioregs) 483 return ERR_PTR(-EIO); 484 } 485 486 ret = ast_init_pci_config(pdev); 487 if (ret) 488 return ERR_PTR(ret); 489 490 if (!ast_is_vga_enabled(dev)) { 491 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n"); 492 need_post = true; 493 } 494 495 /* 496 * If VGA isn't enabled, we need to enable now or subsequent 497 * access to the scratch registers will fail. 498 */ 499 if (need_post) 500 ast_enable_vga(dev); 501 502 /* Enable extended register access */ 503 ast_open_key(ast); 504 ret = ast_enable_mmio(ast); 505 if (ret) 506 return ERR_PTR(ret); 507 508 ret = ast_device_config_init(ast); 509 if (ret) 510 return ERR_PTR(ret); 511 512 ast_detect_widescreen(ast); 513 ast_detect_tx_chip(ast, need_post); 514 515 ret = ast_get_dram_info(dev); 516 if (ret) 517 return ERR_PTR(ret); 518 519 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n", 520 ast->mclk, ast->dram_type, ast->dram_bus_width); 521 522 if (need_post) 523 ast_post_gpu(dev); 524 525 ret = ast_mm_init(ast); 526 if (ret) 527 return ERR_PTR(ret); 528 529 /* map reserved buffer */ 530 ast->dp501_fw_buf = NULL; 531 if (ast->vram_size < pci_resource_len(pdev, 0)) { 532 ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0); 533 if (!ast->dp501_fw_buf) 534 drm_info(dev, "failed to map reserved buffer!\n"); 535 } 536 537 ret = ast_mode_config_init(ast); 538 if (ret) 539 return ERR_PTR(ret); 540 541 return ast; 542 } 543