1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <drm/drm_encoder.h> 32 #include <drm/drm_fb_helper.h> 33 34 #include <drm/drm_gem.h> 35 #include <drm/drm_gem_vram_helper.h> 36 37 #include <drm/drm_vram_mm_helper.h> 38 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 42 #define DRIVER_AUTHOR "Dave Airlie" 43 44 #define DRIVER_NAME "ast" 45 #define DRIVER_DESC "AST" 46 #define DRIVER_DATE "20120228" 47 48 #define DRIVER_MAJOR 0 49 #define DRIVER_MINOR 1 50 #define DRIVER_PATCHLEVEL 0 51 52 #define PCI_CHIP_AST2000 0x2000 53 #define PCI_CHIP_AST2100 0x2010 54 #define PCI_CHIP_AST1180 0x1180 55 56 57 enum ast_chip { 58 AST2000, 59 AST2100, 60 AST1100, 61 AST2200, 62 AST2150, 63 AST2300, 64 AST2400, 65 AST2500, 66 AST1180, 67 }; 68 69 enum ast_tx_chip { 70 AST_TX_NONE, 71 AST_TX_SIL164, 72 AST_TX_ITE66121, 73 AST_TX_DP501, 74 }; 75 76 #define AST_DRAM_512Mx16 0 77 #define AST_DRAM_1Gx16 1 78 #define AST_DRAM_512Mx32 2 79 #define AST_DRAM_1Gx32 3 80 #define AST_DRAM_2Gx16 6 81 #define AST_DRAM_4Gx16 7 82 #define AST_DRAM_8Gx16 8 83 84 struct ast_fbdev; 85 86 struct ast_private { 87 struct drm_device *dev; 88 89 void __iomem *regs; 90 void __iomem *ioregs; 91 92 enum ast_chip chip; 93 bool vga2_clone; 94 uint32_t dram_bus_width; 95 uint32_t dram_type; 96 uint32_t mclk; 97 uint32_t vram_size; 98 99 struct ast_fbdev *fbdev; 100 101 int fb_mtrr; 102 103 struct drm_gem_object *cursor_cache; 104 uint64_t cursor_cache_gpu_addr; 105 /* Acces to this cache is protected by the crtc->mutex of the only crtc 106 * we have. */ 107 struct ttm_bo_kmap_obj cache_kmap; 108 int next_cursor; 109 bool support_wide_screen; 110 enum { 111 ast_use_p2a, 112 ast_use_dt, 113 ast_use_defaults 114 } config_mode; 115 116 enum ast_tx_chip tx_chip_type; 117 u8 dp501_maxclk; 118 u8 *dp501_fw_addr; 119 const struct firmware *dp501_fw; /* dp501 fw */ 120 }; 121 122 int ast_driver_load(struct drm_device *dev, unsigned long flags); 123 void ast_driver_unload(struct drm_device *dev); 124 125 struct ast_gem_object; 126 127 #define AST_IO_AR_PORT_WRITE (0x40) 128 #define AST_IO_MISC_PORT_WRITE (0x42) 129 #define AST_IO_VGA_ENABLE_PORT (0x43) 130 #define AST_IO_SEQ_PORT (0x44) 131 #define AST_IO_DAC_INDEX_READ (0x47) 132 #define AST_IO_DAC_INDEX_WRITE (0x48) 133 #define AST_IO_DAC_DATA (0x49) 134 #define AST_IO_GR_PORT (0x4E) 135 #define AST_IO_CRTC_PORT (0x54) 136 #define AST_IO_INPUT_STATUS1_READ (0x5A) 137 #define AST_IO_MISC_PORT_READ (0x4C) 138 139 #define AST_IO_MM_OFFSET (0x380) 140 141 #define __ast_read(x) \ 142 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 143 u##x val = 0;\ 144 val = ioread##x(ast->regs + reg); \ 145 return val;\ 146 } 147 148 __ast_read(8); 149 __ast_read(16); 150 __ast_read(32) 151 152 #define __ast_io_read(x) \ 153 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ 154 u##x val = 0;\ 155 val = ioread##x(ast->ioregs + reg); \ 156 return val;\ 157 } 158 159 __ast_io_read(8); 160 __ast_io_read(16); 161 __ast_io_read(32); 162 163 #define __ast_write(x) \ 164 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 165 iowrite##x(val, ast->regs + reg);\ 166 } 167 168 __ast_write(8); 169 __ast_write(16); 170 __ast_write(32); 171 172 #define __ast_io_write(x) \ 173 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 174 iowrite##x(val, ast->ioregs + reg);\ 175 } 176 177 __ast_io_write(8); 178 __ast_io_write(16); 179 #undef __ast_io_write 180 181 static inline void ast_set_index_reg(struct ast_private *ast, 182 uint32_t base, uint8_t index, 183 uint8_t val) 184 { 185 ast_io_write16(ast, base, ((u16)val << 8) | index); 186 } 187 188 void ast_set_index_reg_mask(struct ast_private *ast, 189 uint32_t base, uint8_t index, 190 uint8_t mask, uint8_t val); 191 uint8_t ast_get_index_reg(struct ast_private *ast, 192 uint32_t base, uint8_t index); 193 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 194 uint32_t base, uint8_t index, uint8_t mask); 195 196 static inline void ast_open_key(struct ast_private *ast) 197 { 198 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 199 } 200 201 #define AST_VIDMEM_SIZE_8M 0x00800000 202 #define AST_VIDMEM_SIZE_16M 0x01000000 203 #define AST_VIDMEM_SIZE_32M 0x02000000 204 #define AST_VIDMEM_SIZE_64M 0x04000000 205 #define AST_VIDMEM_SIZE_128M 0x08000000 206 207 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 208 209 #define AST_MAX_HWC_WIDTH 64 210 #define AST_MAX_HWC_HEIGHT 64 211 212 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2) 213 #define AST_HWC_SIGNATURE_SIZE 32 214 215 #define AST_DEFAULT_HWC_NUM 2 216 /* define for signature structure */ 217 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 218 #define AST_HWC_SIGNATURE_SizeX 0x04 219 #define AST_HWC_SIGNATURE_SizeY 0x08 220 #define AST_HWC_SIGNATURE_X 0x0C 221 #define AST_HWC_SIGNATURE_Y 0x10 222 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 223 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 224 225 226 struct ast_i2c_chan { 227 struct i2c_adapter adapter; 228 struct drm_device *dev; 229 struct i2c_algo_bit_data bit; 230 }; 231 232 struct ast_connector { 233 struct drm_connector base; 234 struct ast_i2c_chan *i2c; 235 }; 236 237 struct ast_crtc { 238 struct drm_crtc base; 239 struct drm_gem_object *cursor_bo; 240 uint64_t cursor_addr; 241 int cursor_width, cursor_height; 242 u8 offset_x, offset_y; 243 }; 244 245 struct ast_encoder { 246 struct drm_encoder base; 247 }; 248 249 struct ast_framebuffer { 250 struct drm_framebuffer base; 251 struct drm_gem_object *obj; 252 }; 253 254 struct ast_fbdev { 255 struct drm_fb_helper helper; /* must be first */ 256 struct ast_framebuffer afb; 257 void *sysram; 258 int size; 259 int x1, y1, x2, y2; /* dirty rect */ 260 spinlock_t dirty_lock; 261 }; 262 263 #define to_ast_crtc(x) container_of(x, struct ast_crtc, base) 264 #define to_ast_connector(x) container_of(x, struct ast_connector, base) 265 #define to_ast_encoder(x) container_of(x, struct ast_encoder, base) 266 #define to_ast_framebuffer(x) container_of(x, struct ast_framebuffer, base) 267 268 struct ast_vbios_stdtable { 269 u8 misc; 270 u8 seq[4]; 271 u8 crtc[25]; 272 u8 ar[20]; 273 u8 gr[9]; 274 }; 275 276 struct ast_vbios_enhtable { 277 u32 ht; 278 u32 hde; 279 u32 hfp; 280 u32 hsync; 281 u32 vt; 282 u32 vde; 283 u32 vfp; 284 u32 vsync; 285 u32 dclk_index; 286 u32 flags; 287 u32 refresh_rate; 288 u32 refresh_rate_index; 289 u32 mode_id; 290 }; 291 292 struct ast_vbios_dclk_info { 293 u8 param1; 294 u8 param2; 295 u8 param3; 296 }; 297 298 struct ast_vbios_mode_info { 299 const struct ast_vbios_stdtable *std_table; 300 const struct ast_vbios_enhtable *enh_table; 301 }; 302 303 extern int ast_mode_init(struct drm_device *dev); 304 extern void ast_mode_fini(struct drm_device *dev); 305 306 int ast_framebuffer_init(struct drm_device *dev, 307 struct ast_framebuffer *ast_fb, 308 const struct drm_mode_fb_cmd2 *mode_cmd, 309 struct drm_gem_object *obj); 310 311 int ast_fbdev_init(struct drm_device *dev); 312 void ast_fbdev_fini(struct drm_device *dev); 313 void ast_fbdev_set_suspend(struct drm_device *dev, int state); 314 void ast_fbdev_set_base(struct ast_private *ast, unsigned long gpu_addr); 315 316 #define AST_MM_ALIGN_SHIFT 4 317 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 318 319 int ast_mm_init(struct ast_private *ast); 320 void ast_mm_fini(struct ast_private *ast); 321 322 int ast_gem_create(struct drm_device *dev, 323 u32 size, bool iskernel, 324 struct drm_gem_object **obj); 325 326 /* ast post */ 327 void ast_enable_vga(struct drm_device *dev); 328 void ast_enable_mmio(struct drm_device *dev); 329 bool ast_is_vga_enabled(struct drm_device *dev); 330 void ast_post_gpu(struct drm_device *dev); 331 u32 ast_mindwm(struct ast_private *ast, u32 r); 332 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); 333 /* ast dp501 */ 334 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 335 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 336 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 337 u8 ast_get_dp501_max_clk(struct drm_device *dev); 338 void ast_init_3rdtx(struct drm_device *dev); 339 void ast_release_firmware(struct drm_device *dev); 340 #endif 341