1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <linux/i2c.h> 32 #include <linux/i2c-algo-bit.h> 33 #include <linux/io.h> 34 #include <linux/types.h> 35 36 #include <drm/drm_connector.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_mode.h> 40 #include <drm/drm_framebuffer.h> 41 #include <drm/drm_fb_helper.h> 42 43 #define DRIVER_AUTHOR "Dave Airlie" 44 45 #define DRIVER_NAME "ast" 46 #define DRIVER_DESC "AST" 47 #define DRIVER_DATE "20120228" 48 49 #define DRIVER_MAJOR 0 50 #define DRIVER_MINOR 1 51 #define DRIVER_PATCHLEVEL 0 52 53 #define PCI_CHIP_AST2000 0x2000 54 #define PCI_CHIP_AST2100 0x2010 55 56 57 enum ast_chip { 58 AST2000, 59 AST2100, 60 AST1100, 61 AST2200, 62 AST2150, 63 AST2300, 64 AST2400, 65 AST2500, 66 AST2600, 67 }; 68 69 enum ast_tx_chip { 70 AST_TX_NONE, 71 AST_TX_SIL164, 72 AST_TX_DP501, 73 AST_TX_ASTDP, 74 }; 75 76 #define AST_TX_NONE_BIT BIT(AST_TX_NONE) 77 #define AST_TX_SIL164_BIT BIT(AST_TX_SIL164) 78 #define AST_TX_DP501_BIT BIT(AST_TX_DP501) 79 #define AST_TX_ASTDP_BIT BIT(AST_TX_ASTDP) 80 81 #define AST_DRAM_512Mx16 0 82 #define AST_DRAM_1Gx16 1 83 #define AST_DRAM_512Mx32 2 84 #define AST_DRAM_1Gx32 3 85 #define AST_DRAM_2Gx16 6 86 #define AST_DRAM_4Gx16 7 87 #define AST_DRAM_8Gx16 8 88 89 /* 90 * Hardware cursor 91 */ 92 93 #define AST_MAX_HWC_WIDTH 64 94 #define AST_MAX_HWC_HEIGHT 64 95 96 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) 97 #define AST_HWC_SIGNATURE_SIZE 32 98 99 /* define for signature structure */ 100 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 101 #define AST_HWC_SIGNATURE_SizeX 0x04 102 #define AST_HWC_SIGNATURE_SizeY 0x08 103 #define AST_HWC_SIGNATURE_X 0x0C 104 #define AST_HWC_SIGNATURE_Y 0x10 105 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 106 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 107 108 /* 109 * Planes 110 */ 111 112 struct ast_plane { 113 struct drm_plane base; 114 115 void __iomem *vaddr; 116 u64 offset; 117 unsigned long size; 118 }; 119 120 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane) 121 { 122 return container_of(plane, struct ast_plane, base); 123 } 124 125 /* 126 * Connector with i2c channel 127 */ 128 129 struct ast_i2c_chan { 130 struct i2c_adapter adapter; 131 struct drm_device *dev; 132 struct i2c_algo_bit_data bit; 133 }; 134 135 struct ast_vga_connector { 136 struct drm_connector base; 137 struct ast_i2c_chan *i2c; 138 }; 139 140 static inline struct ast_vga_connector * 141 to_ast_vga_connector(struct drm_connector *connector) 142 { 143 return container_of(connector, struct ast_vga_connector, base); 144 } 145 146 struct ast_sil164_connector { 147 struct drm_connector base; 148 struct ast_i2c_chan *i2c; 149 }; 150 151 static inline struct ast_sil164_connector * 152 to_ast_sil164_connector(struct drm_connector *connector) 153 { 154 return container_of(connector, struct ast_sil164_connector, base); 155 } 156 157 /* 158 * Device 159 */ 160 161 struct ast_private { 162 struct drm_device base; 163 164 struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */ 165 void __iomem *regs; 166 void __iomem *ioregs; 167 void __iomem *dp501_fw_buf; 168 169 enum ast_chip chip; 170 bool vga2_clone; 171 uint32_t dram_bus_width; 172 uint32_t dram_type; 173 uint32_t mclk; 174 175 void __iomem *vram; 176 unsigned long vram_base; 177 unsigned long vram_size; 178 unsigned long vram_fb_available; 179 180 struct ast_plane primary_plane; 181 struct ast_plane cursor_plane; 182 struct drm_crtc crtc; 183 struct { 184 struct { 185 struct drm_encoder encoder; 186 struct ast_vga_connector vga_connector; 187 } vga; 188 struct { 189 struct drm_encoder encoder; 190 struct ast_sil164_connector sil164_connector; 191 } sil164; 192 struct { 193 struct drm_encoder encoder; 194 struct drm_connector connector; 195 } dp501; 196 struct { 197 struct drm_encoder encoder; 198 struct drm_connector connector; 199 } astdp; 200 } output; 201 202 bool support_wide_screen; 203 enum { 204 ast_use_p2a, 205 ast_use_dt, 206 ast_use_defaults 207 } config_mode; 208 209 unsigned long tx_chip_types; /* bitfield of enum ast_chip_type */ 210 u8 *dp501_fw_addr; 211 const struct firmware *dp501_fw; /* dp501 fw */ 212 }; 213 214 static inline struct ast_private *to_ast_private(struct drm_device *dev) 215 { 216 return container_of(dev, struct ast_private, base); 217 } 218 219 struct ast_private *ast_device_create(const struct drm_driver *drv, 220 struct pci_dev *pdev, 221 unsigned long flags); 222 223 #define AST_IO_AR_PORT_WRITE (0x40) 224 #define AST_IO_MISC_PORT_WRITE (0x42) 225 #define AST_IO_VGA_ENABLE_PORT (0x43) 226 #define AST_IO_SEQ_PORT (0x44) 227 #define AST_IO_DAC_INDEX_READ (0x47) 228 #define AST_IO_DAC_INDEX_WRITE (0x48) 229 #define AST_IO_DAC_DATA (0x49) 230 #define AST_IO_GR_PORT (0x4E) 231 #define AST_IO_CRTC_PORT (0x54) 232 #define AST_IO_INPUT_STATUS1_READ (0x5A) 233 #define AST_IO_MISC_PORT_READ (0x4C) 234 235 #define AST_IO_MM_OFFSET (0x380) 236 237 #define AST_IO_VGAIR1_VREFRESH BIT(3) 238 239 #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) 240 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ 241 242 #define __ast_read(x) \ 243 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 244 u##x val = 0;\ 245 val = ioread##x(ast->regs + reg); \ 246 return val;\ 247 } 248 249 __ast_read(8); 250 __ast_read(16); 251 __ast_read(32) 252 253 #define __ast_io_read(x) \ 254 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ 255 u##x val = 0;\ 256 val = ioread##x(ast->ioregs + reg); \ 257 return val;\ 258 } 259 260 __ast_io_read(8); 261 __ast_io_read(16); 262 __ast_io_read(32); 263 264 #define __ast_write(x) \ 265 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 266 iowrite##x(val, ast->regs + reg);\ 267 } 268 269 __ast_write(8); 270 __ast_write(16); 271 __ast_write(32); 272 273 #define __ast_io_write(x) \ 274 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 275 iowrite##x(val, ast->ioregs + reg);\ 276 } 277 278 __ast_io_write(8); 279 __ast_io_write(16); 280 #undef __ast_io_write 281 282 static inline void ast_set_index_reg(struct ast_private *ast, 283 uint32_t base, uint8_t index, 284 uint8_t val) 285 { 286 ast_io_write16(ast, base, ((u16)val << 8) | index); 287 } 288 289 void ast_set_index_reg_mask(struct ast_private *ast, 290 uint32_t base, uint8_t index, 291 uint8_t mask, uint8_t val); 292 uint8_t ast_get_index_reg(struct ast_private *ast, 293 uint32_t base, uint8_t index); 294 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 295 uint32_t base, uint8_t index, uint8_t mask); 296 297 static inline void ast_open_key(struct ast_private *ast) 298 { 299 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 300 } 301 302 #define AST_VIDMEM_SIZE_8M 0x00800000 303 #define AST_VIDMEM_SIZE_16M 0x01000000 304 #define AST_VIDMEM_SIZE_32M 0x02000000 305 #define AST_VIDMEM_SIZE_64M 0x04000000 306 #define AST_VIDMEM_SIZE_128M 0x08000000 307 308 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 309 310 struct ast_vbios_stdtable { 311 u8 misc; 312 u8 seq[4]; 313 u8 crtc[25]; 314 u8 ar[20]; 315 u8 gr[9]; 316 }; 317 318 struct ast_vbios_enhtable { 319 u32 ht; 320 u32 hde; 321 u32 hfp; 322 u32 hsync; 323 u32 vt; 324 u32 vde; 325 u32 vfp; 326 u32 vsync; 327 u32 dclk_index; 328 u32 flags; 329 u32 refresh_rate; 330 u32 refresh_rate_index; 331 u32 mode_id; 332 }; 333 334 struct ast_vbios_dclk_info { 335 u8 param1; 336 u8 param2; 337 u8 param3; 338 }; 339 340 struct ast_vbios_mode_info { 341 const struct ast_vbios_stdtable *std_table; 342 const struct ast_vbios_enhtable *enh_table; 343 }; 344 345 struct ast_crtc_state { 346 struct drm_crtc_state base; 347 348 /* Last known format of primary plane */ 349 const struct drm_format_info *format; 350 351 struct ast_vbios_mode_info vbios_mode_info; 352 }; 353 354 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) 355 356 int ast_mode_config_init(struct ast_private *ast); 357 358 #define AST_MM_ALIGN_SHIFT 4 359 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 360 361 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4) 362 #define AST_DP501_FW_VERSION_1 BIT(4) 363 #define AST_DP501_PNP_CONNECTED BIT(1) 364 365 #define AST_DP501_DEFAULT_DCLK 65 366 367 #define AST_DP501_GBL_VERSION 0xf000 368 #define AST_DP501_PNPMONITOR 0xf010 369 #define AST_DP501_LINKRATE 0xf014 370 #define AST_DP501_EDID_DATA 0xf020 371 372 /* Define for Soc scratched reg */ 373 #define COPROCESSOR_LAUNCH BIT(5) 374 375 /* 376 * Display Transmitter Type: 377 */ 378 #define TX_TYPE_MASK GENMASK(3, 1) 379 #define NO_TX (0 << 1) 380 #define ITE66121_VBIOS_TX (1 << 1) 381 #define SI164_VBIOS_TX (2 << 1) 382 #define CH7003_VBIOS_TX (3 << 1) 383 #define DP501_VBIOS_TX (4 << 1) 384 #define ANX9807_VBIOS_TX (5 << 1) 385 #define TX_FW_EMBEDDED_FW_TX (6 << 1) 386 #define ASTDP_DPMCU_TX (7 << 1) 387 388 #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6) 389 //#define AST_VRAM_INIT_BY_BMC BIT(7) 390 //#define AST_VRAM_INIT_READY BIT(6) 391 392 /* Define for Soc scratched reg used on ASTDP */ 393 #define AST_DP_PHY_SLEEP BIT(4) 394 #define AST_DP_VIDEO_ENABLE BIT(0) 395 396 #define AST_DP_POWER_ON true 397 #define AST_DP_POWER_OFF false 398 399 /* 400 * CRD1[b5]: DP MCU FW is executing 401 * CRDC[b0]: DP link success 402 * CRDF[b0]: DP HPD 403 * CRE5[b0]: Host reading EDID process is done 404 */ 405 #define ASTDP_MCU_FW_EXECUTING BIT(5) 406 #define ASTDP_LINK_SUCCESS BIT(0) 407 #define ASTDP_HPD BIT(0) 408 #define ASTDP_HOST_EDID_READ_DONE BIT(0) 409 #define ASTDP_HOST_EDID_READ_DONE_MASK GENMASK(0, 0) 410 411 /* 412 * CRB8[b1]: Enable VSYNC off 413 * CRB8[b0]: Enable HSYNC off 414 */ 415 #define AST_DPMS_VSYNC_OFF BIT(1) 416 #define AST_DPMS_HSYNC_OFF BIT(0) 417 418 /* 419 * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE 420 * Precondition: A. ~AST_DP_PHY_SLEEP && 421 * B. DP_HPD && 422 * C. DP_LINK_SUCCESS 423 */ 424 #define ASTDP_MIRROR_VIDEO_ENABLE BIT(4) 425 426 #define ASTDP_EDID_READ_POINTER_MASK GENMASK(7, 0) 427 #define ASTDP_EDID_VALID_FLAG_MASK GENMASK(0, 0) 428 #define ASTDP_EDID_READ_DATA_MASK GENMASK(7, 0) 429 430 /* 431 * ASTDP setmode registers: 432 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) 433 * CRE1[7:0]: MISC1 (default: 0x00) 434 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) 435 */ 436 #define ASTDP_MISC0_24bpp BIT(5) 437 #define ASTDP_MISC1 0 438 #define ASTDP_AND_CLEAR_MASK 0x00 439 440 /* 441 * ASTDP resoultion table: 442 * EX: ASTDP_A_B_C: 443 * A: Resolution 444 * B: Refresh Rate 445 * C: Misc information, such as CVT, Reduce Blanked 446 */ 447 #define ASTDP_640x480_60 0x00 448 #define ASTDP_640x480_72 0x01 449 #define ASTDP_640x480_75 0x02 450 #define ASTDP_640x480_85 0x03 451 #define ASTDP_800x600_56 0x04 452 #define ASTDP_800x600_60 0x05 453 #define ASTDP_800x600_72 0x06 454 #define ASTDP_800x600_75 0x07 455 #define ASTDP_800x600_85 0x08 456 #define ASTDP_1024x768_60 0x09 457 #define ASTDP_1024x768_70 0x0A 458 #define ASTDP_1024x768_75 0x0B 459 #define ASTDP_1024x768_85 0x0C 460 #define ASTDP_1280x1024_60 0x0D 461 #define ASTDP_1280x1024_75 0x0E 462 #define ASTDP_1280x1024_85 0x0F 463 #define ASTDP_1600x1200_60 0x10 464 #define ASTDP_320x240_60 0x11 465 #define ASTDP_400x300_60 0x12 466 #define ASTDP_512x384_60 0x13 467 #define ASTDP_1920x1200_60 0x14 468 #define ASTDP_1920x1080_60 0x15 469 #define ASTDP_1280x800_60 0x16 470 #define ASTDP_1280x800_60_RB 0x17 471 #define ASTDP_1440x900_60 0x18 472 #define ASTDP_1440x900_60_RB 0x19 473 #define ASTDP_1680x1050_60 0x1A 474 #define ASTDP_1680x1050_60_RB 0x1B 475 #define ASTDP_1600x900_60 0x1C 476 #define ASTDP_1600x900_60_RB 0x1D 477 #define ASTDP_1366x768_60 0x1E 478 #define ASTDP_1152x864_75 0x1F 479 480 int ast_mm_init(struct ast_private *ast); 481 482 /* ast post */ 483 void ast_enable_vga(struct drm_device *dev); 484 void ast_enable_mmio(struct drm_device *dev); 485 bool ast_is_vga_enabled(struct drm_device *dev); 486 void ast_post_gpu(struct drm_device *dev); 487 u32 ast_mindwm(struct ast_private *ast, u32 r); 488 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); 489 void ast_patch_ahb_2500(struct ast_private *ast); 490 /* ast dp501 */ 491 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 492 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 493 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 494 u8 ast_get_dp501_max_clk(struct drm_device *dev); 495 void ast_init_3rdtx(struct drm_device *dev); 496 497 /* ast_i2c.c */ 498 struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 499 500 /* aspeed DP */ 501 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata); 502 void ast_dp_launch(struct drm_device *dev, u8 bPower); 503 void ast_dp_power_on_off(struct drm_device *dev, bool no); 504 void ast_dp_set_on_off(struct drm_device *dev, bool no); 505 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode); 506 507 #endif 508