1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <linux/i2c.h> 32 #include <linux/i2c-algo-bit.h> 33 #include <linux/io.h> 34 #include <linux/types.h> 35 36 #include <drm/drm_connector.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_mode.h> 40 #include <drm/drm_framebuffer.h> 41 #include <drm/drm_fb_helper.h> 42 43 #define DRIVER_AUTHOR "Dave Airlie" 44 45 #define DRIVER_NAME "ast" 46 #define DRIVER_DESC "AST" 47 #define DRIVER_DATE "20120228" 48 49 #define DRIVER_MAJOR 0 50 #define DRIVER_MINOR 1 51 #define DRIVER_PATCHLEVEL 0 52 53 #define PCI_CHIP_AST2000 0x2000 54 #define PCI_CHIP_AST2100 0x2010 55 56 57 enum ast_chip { 58 AST2000, 59 AST2100, 60 AST1100, 61 AST2200, 62 AST2150, 63 AST2300, 64 AST2400, 65 AST2500, 66 AST2600, 67 }; 68 69 enum ast_tx_chip { 70 AST_TX_NONE, 71 AST_TX_SIL164, 72 AST_TX_DP501, 73 AST_TX_ASTDP, 74 }; 75 76 #define AST_DRAM_512Mx16 0 77 #define AST_DRAM_1Gx16 1 78 #define AST_DRAM_512Mx32 2 79 #define AST_DRAM_1Gx32 3 80 #define AST_DRAM_2Gx16 6 81 #define AST_DRAM_4Gx16 7 82 #define AST_DRAM_8Gx16 8 83 84 /* 85 * Cursor plane 86 */ 87 88 #define AST_MAX_HWC_WIDTH 64 89 #define AST_MAX_HWC_HEIGHT 64 90 91 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) 92 #define AST_HWC_SIGNATURE_SIZE 32 93 94 #define AST_DEFAULT_HWC_NUM 2 95 96 /* define for signature structure */ 97 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 98 #define AST_HWC_SIGNATURE_SizeX 0x04 99 #define AST_HWC_SIGNATURE_SizeY 0x08 100 #define AST_HWC_SIGNATURE_X 0x0C 101 #define AST_HWC_SIGNATURE_Y 0x10 102 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 103 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 104 105 struct ast_cursor_plane { 106 struct drm_plane base; 107 108 struct { 109 struct drm_gem_vram_object *gbo; 110 struct iosys_map map; 111 u64 off; 112 } hwc[AST_DEFAULT_HWC_NUM]; 113 114 unsigned int next_hwc_index; 115 }; 116 117 static inline struct ast_cursor_plane * 118 to_ast_cursor_plane(struct drm_plane *plane) 119 { 120 return container_of(plane, struct ast_cursor_plane, base); 121 } 122 123 /* 124 * Connector with i2c channel 125 */ 126 127 struct ast_i2c_chan { 128 struct i2c_adapter adapter; 129 struct drm_device *dev; 130 struct i2c_algo_bit_data bit; 131 }; 132 133 struct ast_vga_connector { 134 struct drm_connector base; 135 struct ast_i2c_chan *i2c; 136 }; 137 138 static inline struct ast_vga_connector * 139 to_ast_vga_connector(struct drm_connector *connector) 140 { 141 return container_of(connector, struct ast_vga_connector, base); 142 } 143 144 struct ast_sil164_connector { 145 struct drm_connector base; 146 struct ast_i2c_chan *i2c; 147 }; 148 149 static inline struct ast_sil164_connector * 150 to_ast_sil164_connector(struct drm_connector *connector) 151 { 152 return container_of(connector, struct ast_sil164_connector, base); 153 } 154 155 /* 156 * Device 157 */ 158 159 struct ast_private { 160 struct drm_device base; 161 162 struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */ 163 void __iomem *regs; 164 void __iomem *ioregs; 165 void __iomem *dp501_fw_buf; 166 167 enum ast_chip chip; 168 bool vga2_clone; 169 uint32_t dram_bus_width; 170 uint32_t dram_type; 171 uint32_t mclk; 172 173 struct drm_plane primary_plane; 174 struct ast_cursor_plane cursor_plane; 175 struct drm_crtc crtc; 176 union { 177 struct { 178 struct drm_encoder encoder; 179 struct ast_vga_connector vga_connector; 180 } vga; 181 struct { 182 struct drm_encoder encoder; 183 struct ast_sil164_connector sil164_connector; 184 } sil164; 185 struct { 186 struct drm_encoder encoder; 187 struct drm_connector connector; 188 } dp501; 189 struct { 190 struct drm_encoder encoder; 191 struct drm_connector connector; 192 } astdp; 193 } output; 194 195 bool support_wide_screen; 196 enum { 197 ast_use_p2a, 198 ast_use_dt, 199 ast_use_defaults 200 } config_mode; 201 202 enum ast_tx_chip tx_chip_type; 203 u8 *dp501_fw_addr; 204 const struct firmware *dp501_fw; /* dp501 fw */ 205 }; 206 207 static inline struct ast_private *to_ast_private(struct drm_device *dev) 208 { 209 return container_of(dev, struct ast_private, base); 210 } 211 212 struct ast_private *ast_device_create(const struct drm_driver *drv, 213 struct pci_dev *pdev, 214 unsigned long flags); 215 216 #define AST_IO_AR_PORT_WRITE (0x40) 217 #define AST_IO_MISC_PORT_WRITE (0x42) 218 #define AST_IO_VGA_ENABLE_PORT (0x43) 219 #define AST_IO_SEQ_PORT (0x44) 220 #define AST_IO_DAC_INDEX_READ (0x47) 221 #define AST_IO_DAC_INDEX_WRITE (0x48) 222 #define AST_IO_DAC_DATA (0x49) 223 #define AST_IO_GR_PORT (0x4E) 224 #define AST_IO_CRTC_PORT (0x54) 225 #define AST_IO_INPUT_STATUS1_READ (0x5A) 226 #define AST_IO_MISC_PORT_READ (0x4C) 227 228 #define AST_IO_MM_OFFSET (0x380) 229 230 #define AST_IO_VGAIR1_VREFRESH BIT(3) 231 232 #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) 233 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ 234 235 #define __ast_read(x) \ 236 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 237 u##x val = 0;\ 238 val = ioread##x(ast->regs + reg); \ 239 return val;\ 240 } 241 242 __ast_read(8); 243 __ast_read(16); 244 __ast_read(32) 245 246 #define __ast_io_read(x) \ 247 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ 248 u##x val = 0;\ 249 val = ioread##x(ast->ioregs + reg); \ 250 return val;\ 251 } 252 253 __ast_io_read(8); 254 __ast_io_read(16); 255 __ast_io_read(32); 256 257 #define __ast_write(x) \ 258 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 259 iowrite##x(val, ast->regs + reg);\ 260 } 261 262 __ast_write(8); 263 __ast_write(16); 264 __ast_write(32); 265 266 #define __ast_io_write(x) \ 267 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 268 iowrite##x(val, ast->ioregs + reg);\ 269 } 270 271 __ast_io_write(8); 272 __ast_io_write(16); 273 #undef __ast_io_write 274 275 static inline void ast_set_index_reg(struct ast_private *ast, 276 uint32_t base, uint8_t index, 277 uint8_t val) 278 { 279 ast_io_write16(ast, base, ((u16)val << 8) | index); 280 } 281 282 void ast_set_index_reg_mask(struct ast_private *ast, 283 uint32_t base, uint8_t index, 284 uint8_t mask, uint8_t val); 285 uint8_t ast_get_index_reg(struct ast_private *ast, 286 uint32_t base, uint8_t index); 287 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 288 uint32_t base, uint8_t index, uint8_t mask); 289 290 static inline void ast_open_key(struct ast_private *ast) 291 { 292 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 293 } 294 295 #define AST_VIDMEM_SIZE_8M 0x00800000 296 #define AST_VIDMEM_SIZE_16M 0x01000000 297 #define AST_VIDMEM_SIZE_32M 0x02000000 298 #define AST_VIDMEM_SIZE_64M 0x04000000 299 #define AST_VIDMEM_SIZE_128M 0x08000000 300 301 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 302 303 struct ast_vbios_stdtable { 304 u8 misc; 305 u8 seq[4]; 306 u8 crtc[25]; 307 u8 ar[20]; 308 u8 gr[9]; 309 }; 310 311 struct ast_vbios_enhtable { 312 u32 ht; 313 u32 hde; 314 u32 hfp; 315 u32 hsync; 316 u32 vt; 317 u32 vde; 318 u32 vfp; 319 u32 vsync; 320 u32 dclk_index; 321 u32 flags; 322 u32 refresh_rate; 323 u32 refresh_rate_index; 324 u32 mode_id; 325 }; 326 327 struct ast_vbios_dclk_info { 328 u8 param1; 329 u8 param2; 330 u8 param3; 331 }; 332 333 struct ast_vbios_mode_info { 334 const struct ast_vbios_stdtable *std_table; 335 const struct ast_vbios_enhtable *enh_table; 336 }; 337 338 struct ast_crtc_state { 339 struct drm_crtc_state base; 340 341 /* Last known format of primary plane */ 342 const struct drm_format_info *format; 343 344 struct ast_vbios_mode_info vbios_mode_info; 345 }; 346 347 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) 348 349 int ast_mode_config_init(struct ast_private *ast); 350 351 #define AST_MM_ALIGN_SHIFT 4 352 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 353 354 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4) 355 #define AST_DP501_FW_VERSION_1 BIT(4) 356 #define AST_DP501_PNP_CONNECTED BIT(1) 357 358 #define AST_DP501_DEFAULT_DCLK 65 359 360 #define AST_DP501_GBL_VERSION 0xf000 361 #define AST_DP501_PNPMONITOR 0xf010 362 #define AST_DP501_LINKRATE 0xf014 363 #define AST_DP501_EDID_DATA 0xf020 364 365 /* Define for Soc scratched reg */ 366 #define COPROCESSOR_LAUNCH BIT(5) 367 368 /* 369 * Display Transmitter Type: 370 */ 371 #define TX_TYPE_MASK GENMASK(3, 1) 372 #define NO_TX (0 << 1) 373 #define ITE66121_VBIOS_TX (1 << 1) 374 #define SI164_VBIOS_TX (2 << 1) 375 #define CH7003_VBIOS_TX (3 << 1) 376 #define DP501_VBIOS_TX (4 << 1) 377 #define ANX9807_VBIOS_TX (5 << 1) 378 #define TX_FW_EMBEDDED_FW_TX (6 << 1) 379 #define ASTDP_DPMCU_TX (7 << 1) 380 381 #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6) 382 //#define AST_VRAM_INIT_BY_BMC BIT(7) 383 //#define AST_VRAM_INIT_READY BIT(6) 384 385 /* Define for Soc scratched reg used on ASTDP */ 386 #define AST_DP_PHY_SLEEP BIT(4) 387 #define AST_DP_VIDEO_ENABLE BIT(0) 388 389 #define AST_DP_POWER_ON true 390 #define AST_DP_POWER_OFF false 391 392 /* 393 * CRD1[b5]: DP MCU FW is executing 394 * CRDC[b0]: DP link success 395 * CRDF[b0]: DP HPD 396 * CRE5[b0]: Host reading EDID process is done 397 */ 398 #define ASTDP_MCU_FW_EXECUTING BIT(5) 399 #define ASTDP_LINK_SUCCESS BIT(0) 400 #define ASTDP_HPD BIT(0) 401 #define ASTDP_HOST_EDID_READ_DONE BIT(0) 402 #define ASTDP_HOST_EDID_READ_DONE_MASK GENMASK(0, 0) 403 404 /* 405 * CRB8[b1]: Enable VSYNC off 406 * CRB8[b0]: Enable HSYNC off 407 */ 408 #define AST_DPMS_VSYNC_OFF BIT(1) 409 #define AST_DPMS_HSYNC_OFF BIT(0) 410 411 /* 412 * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE 413 * Precondition: A. ~AST_DP_PHY_SLEEP && 414 * B. DP_HPD && 415 * C. DP_LINK_SUCCESS 416 */ 417 #define ASTDP_MIRROR_VIDEO_ENABLE BIT(4) 418 419 #define ASTDP_EDID_READ_POINTER_MASK GENMASK(7, 0) 420 #define ASTDP_EDID_VALID_FLAG_MASK GENMASK(0, 0) 421 #define ASTDP_EDID_READ_DATA_MASK GENMASK(7, 0) 422 423 /* 424 * ASTDP setmode registers: 425 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) 426 * CRE1[7:0]: MISC1 (default: 0x00) 427 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) 428 */ 429 #define ASTDP_MISC0_24bpp BIT(5) 430 #define ASTDP_MISC1 0 431 #define ASTDP_CLEAR_MASK GENMASK(7, 0) 432 433 /* 434 * ASTDP resoultion table: 435 * EX: ASTDP_A_B_C: 436 * A: Resolution 437 * B: Refresh Rate 438 * C: Misc information, such as CVT, Reduce Blanked 439 */ 440 #define ASTDP_640x480_60 0x00 441 #define ASTDP_640x480_72 0x01 442 #define ASTDP_640x480_75 0x02 443 #define ASTDP_640x480_85 0x03 444 #define ASTDP_800x600_56 0x04 445 #define ASTDP_800x600_60 0x05 446 #define ASTDP_800x600_72 0x06 447 #define ASTDP_800x600_75 0x07 448 #define ASTDP_800x600_85 0x08 449 #define ASTDP_1024x768_60 0x09 450 #define ASTDP_1024x768_70 0x0A 451 #define ASTDP_1024x768_75 0x0B 452 #define ASTDP_1024x768_85 0x0C 453 #define ASTDP_1280x1024_60 0x0D 454 #define ASTDP_1280x1024_75 0x0E 455 #define ASTDP_1280x1024_85 0x0F 456 #define ASTDP_1600x1200_60 0x10 457 #define ASTDP_320x240_60 0x11 458 #define ASTDP_400x300_60 0x12 459 #define ASTDP_512x384_60 0x13 460 #define ASTDP_1920x1200_60 0x14 461 #define ASTDP_1920x1080_60 0x15 462 #define ASTDP_1280x800_60 0x16 463 #define ASTDP_1280x800_60_RB 0x17 464 #define ASTDP_1440x900_60 0x18 465 #define ASTDP_1440x900_60_RB 0x19 466 #define ASTDP_1680x1050_60 0x1A 467 #define ASTDP_1680x1050_60_RB 0x1B 468 #define ASTDP_1600x900_60 0x1C 469 #define ASTDP_1600x900_60_RB 0x1D 470 #define ASTDP_1366x768_60 0x1E 471 #define ASTDP_1152x864_75 0x1F 472 473 int ast_mm_init(struct ast_private *ast); 474 475 /* ast post */ 476 void ast_enable_vga(struct drm_device *dev); 477 void ast_enable_mmio(struct drm_device *dev); 478 bool ast_is_vga_enabled(struct drm_device *dev); 479 void ast_post_gpu(struct drm_device *dev); 480 u32 ast_mindwm(struct ast_private *ast, u32 r); 481 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); 482 void ast_patch_ahb_2500(struct ast_private *ast); 483 /* ast dp501 */ 484 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 485 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 486 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 487 u8 ast_get_dp501_max_clk(struct drm_device *dev); 488 void ast_init_3rdtx(struct drm_device *dev); 489 490 /* ast_i2c.c */ 491 struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 492 493 /* aspeed DP */ 494 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata); 495 void ast_dp_launch(struct drm_device *dev, u8 bPower); 496 void ast_dp_power_on_off(struct drm_device *dev, bool no); 497 void ast_dp_set_on_off(struct drm_device *dev, bool no); 498 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode); 499 500 #endif 501