1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <linux/dma-buf-map.h> 32 #include <linux/i2c.h> 33 #include <linux/i2c-algo-bit.h> 34 #include <linux/io.h> 35 #include <linux/types.h> 36 37 #include <drm/drm_connector.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_encoder.h> 40 #include <drm/drm_mode.h> 41 #include <drm/drm_framebuffer.h> 42 #include <drm/drm_fb_helper.h> 43 44 #define DRIVER_AUTHOR "Dave Airlie" 45 46 #define DRIVER_NAME "ast" 47 #define DRIVER_DESC "AST" 48 #define DRIVER_DATE "20120228" 49 50 #define DRIVER_MAJOR 0 51 #define DRIVER_MINOR 1 52 #define DRIVER_PATCHLEVEL 0 53 54 #define PCI_CHIP_AST2000 0x2000 55 #define PCI_CHIP_AST2100 0x2010 56 57 58 enum ast_chip { 59 AST2000, 60 AST2100, 61 AST1100, 62 AST2200, 63 AST2150, 64 AST2300, 65 AST2400, 66 AST2500, 67 AST2600, 68 }; 69 70 enum ast_tx_chip { 71 AST_TX_NONE, 72 AST_TX_SIL164, 73 AST_TX_ITE66121, 74 AST_TX_DP501, 75 }; 76 77 #define AST_DRAM_512Mx16 0 78 #define AST_DRAM_1Gx16 1 79 #define AST_DRAM_512Mx32 2 80 #define AST_DRAM_1Gx32 3 81 #define AST_DRAM_2Gx16 6 82 #define AST_DRAM_4Gx16 7 83 #define AST_DRAM_8Gx16 8 84 85 86 #define AST_MAX_HWC_WIDTH 64 87 #define AST_MAX_HWC_HEIGHT 64 88 89 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) 90 #define AST_HWC_SIGNATURE_SIZE 32 91 92 #define AST_DEFAULT_HWC_NUM 2 93 94 /* define for signature structure */ 95 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 96 #define AST_HWC_SIGNATURE_SizeX 0x04 97 #define AST_HWC_SIGNATURE_SizeY 0x08 98 #define AST_HWC_SIGNATURE_X 0x0C 99 #define AST_HWC_SIGNATURE_Y 0x10 100 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 101 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 102 103 struct ast_i2c_chan { 104 struct i2c_adapter adapter; 105 struct drm_device *dev; 106 struct i2c_algo_bit_data bit; 107 }; 108 109 struct ast_connector { 110 struct drm_connector base; 111 struct ast_i2c_chan *i2c; 112 }; 113 114 static inline struct ast_connector * 115 to_ast_connector(struct drm_connector *connector) 116 { 117 return container_of(connector, struct ast_connector, base); 118 } 119 120 struct ast_private { 121 struct drm_device base; 122 123 void __iomem *regs; 124 void __iomem *ioregs; 125 126 enum ast_chip chip; 127 bool vga2_clone; 128 uint32_t dram_bus_width; 129 uint32_t dram_type; 130 uint32_t mclk; 131 132 int fb_mtrr; 133 134 struct { 135 struct drm_gem_vram_object *gbo[AST_DEFAULT_HWC_NUM]; 136 struct dma_buf_map map[AST_DEFAULT_HWC_NUM]; 137 unsigned int next_index; 138 } cursor; 139 140 struct drm_plane primary_plane; 141 struct drm_plane cursor_plane; 142 struct drm_crtc crtc; 143 struct drm_encoder encoder; 144 struct ast_connector connector; 145 146 bool support_wide_screen; 147 enum { 148 ast_use_p2a, 149 ast_use_dt, 150 ast_use_defaults 151 } config_mode; 152 153 enum ast_tx_chip tx_chip_type; 154 u8 dp501_maxclk; 155 u8 *dp501_fw_addr; 156 const struct firmware *dp501_fw; /* dp501 fw */ 157 }; 158 159 static inline struct ast_private *to_ast_private(struct drm_device *dev) 160 { 161 return container_of(dev, struct ast_private, base); 162 } 163 164 struct ast_private *ast_device_create(const struct drm_driver *drv, 165 struct pci_dev *pdev, 166 unsigned long flags); 167 168 #define AST_IO_AR_PORT_WRITE (0x40) 169 #define AST_IO_MISC_PORT_WRITE (0x42) 170 #define AST_IO_VGA_ENABLE_PORT (0x43) 171 #define AST_IO_SEQ_PORT (0x44) 172 #define AST_IO_DAC_INDEX_READ (0x47) 173 #define AST_IO_DAC_INDEX_WRITE (0x48) 174 #define AST_IO_DAC_DATA (0x49) 175 #define AST_IO_GR_PORT (0x4E) 176 #define AST_IO_CRTC_PORT (0x54) 177 #define AST_IO_INPUT_STATUS1_READ (0x5A) 178 #define AST_IO_MISC_PORT_READ (0x4C) 179 180 #define AST_IO_MM_OFFSET (0x380) 181 182 #define AST_IO_VGAIR1_VREFRESH BIT(3) 183 184 #define __ast_read(x) \ 185 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 186 u##x val = 0;\ 187 val = ioread##x(ast->regs + reg); \ 188 return val;\ 189 } 190 191 __ast_read(8); 192 __ast_read(16); 193 __ast_read(32) 194 195 #define __ast_io_read(x) \ 196 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ 197 u##x val = 0;\ 198 val = ioread##x(ast->ioregs + reg); \ 199 return val;\ 200 } 201 202 __ast_io_read(8); 203 __ast_io_read(16); 204 __ast_io_read(32); 205 206 #define __ast_write(x) \ 207 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 208 iowrite##x(val, ast->regs + reg);\ 209 } 210 211 __ast_write(8); 212 __ast_write(16); 213 __ast_write(32); 214 215 #define __ast_io_write(x) \ 216 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 217 iowrite##x(val, ast->ioregs + reg);\ 218 } 219 220 __ast_io_write(8); 221 __ast_io_write(16); 222 #undef __ast_io_write 223 224 static inline void ast_set_index_reg(struct ast_private *ast, 225 uint32_t base, uint8_t index, 226 uint8_t val) 227 { 228 ast_io_write16(ast, base, ((u16)val << 8) | index); 229 } 230 231 void ast_set_index_reg_mask(struct ast_private *ast, 232 uint32_t base, uint8_t index, 233 uint8_t mask, uint8_t val); 234 uint8_t ast_get_index_reg(struct ast_private *ast, 235 uint32_t base, uint8_t index); 236 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 237 uint32_t base, uint8_t index, uint8_t mask); 238 239 static inline void ast_open_key(struct ast_private *ast) 240 { 241 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 242 } 243 244 #define AST_VIDMEM_SIZE_8M 0x00800000 245 #define AST_VIDMEM_SIZE_16M 0x01000000 246 #define AST_VIDMEM_SIZE_32M 0x02000000 247 #define AST_VIDMEM_SIZE_64M 0x04000000 248 #define AST_VIDMEM_SIZE_128M 0x08000000 249 250 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 251 252 struct ast_vbios_stdtable { 253 u8 misc; 254 u8 seq[4]; 255 u8 crtc[25]; 256 u8 ar[20]; 257 u8 gr[9]; 258 }; 259 260 struct ast_vbios_enhtable { 261 u32 ht; 262 u32 hde; 263 u32 hfp; 264 u32 hsync; 265 u32 vt; 266 u32 vde; 267 u32 vfp; 268 u32 vsync; 269 u32 dclk_index; 270 u32 flags; 271 u32 refresh_rate; 272 u32 refresh_rate_index; 273 u32 mode_id; 274 }; 275 276 struct ast_vbios_dclk_info { 277 u8 param1; 278 u8 param2; 279 u8 param3; 280 }; 281 282 struct ast_vbios_mode_info { 283 const struct ast_vbios_stdtable *std_table; 284 const struct ast_vbios_enhtable *enh_table; 285 }; 286 287 struct ast_crtc_state { 288 struct drm_crtc_state base; 289 290 /* Last known format of primary plane */ 291 const struct drm_format_info *format; 292 293 struct ast_vbios_mode_info vbios_mode_info; 294 }; 295 296 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) 297 298 int ast_mode_config_init(struct ast_private *ast); 299 300 #define AST_MM_ALIGN_SHIFT 4 301 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 302 303 int ast_mm_init(struct ast_private *ast); 304 305 /* ast post */ 306 void ast_enable_vga(struct drm_device *dev); 307 void ast_enable_mmio(struct drm_device *dev); 308 bool ast_is_vga_enabled(struct drm_device *dev); 309 void ast_post_gpu(struct drm_device *dev); 310 u32 ast_mindwm(struct ast_private *ast, u32 r); 311 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); 312 /* ast dp501 */ 313 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 314 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 315 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 316 u8 ast_get_dp501_max_clk(struct drm_device *dev); 317 void ast_init_3rdtx(struct drm_device *dev); 318 319 /* ast_cursor.c */ 320 int ast_cursor_init(struct ast_private *ast); 321 int ast_cursor_blit(struct ast_private *ast, struct drm_framebuffer *fb); 322 void ast_cursor_page_flip(struct ast_private *ast); 323 void ast_cursor_show(struct ast_private *ast, int x, int y, 324 unsigned int offset_x, unsigned int offset_y); 325 void ast_cursor_hide(struct ast_private *ast); 326 327 #endif 328