1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <linux/i2c.h> 32 #include <linux/i2c-algo-bit.h> 33 #include <linux/io.h> 34 #include <linux/types.h> 35 36 #include <drm/drm_connector.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_mode.h> 40 #include <drm/drm_framebuffer.h> 41 #include <drm/drm_fb_helper.h> 42 43 #define DRIVER_AUTHOR "Dave Airlie" 44 45 #define DRIVER_NAME "ast" 46 #define DRIVER_DESC "AST" 47 #define DRIVER_DATE "20120228" 48 49 #define DRIVER_MAJOR 0 50 #define DRIVER_MINOR 1 51 #define DRIVER_PATCHLEVEL 0 52 53 #define PCI_CHIP_AST2000 0x2000 54 #define PCI_CHIP_AST2100 0x2010 55 56 57 enum ast_chip { 58 AST2000, 59 AST2100, 60 AST1100, 61 AST2200, 62 AST2150, 63 AST2300, 64 AST2400, 65 AST2500, 66 AST2600, 67 }; 68 69 enum ast_tx_chip { 70 AST_TX_NONE, 71 AST_TX_SIL164, 72 AST_TX_DP501, 73 }; 74 75 #define AST_DRAM_512Mx16 0 76 #define AST_DRAM_1Gx16 1 77 #define AST_DRAM_512Mx32 2 78 #define AST_DRAM_1Gx32 3 79 #define AST_DRAM_2Gx16 6 80 #define AST_DRAM_4Gx16 7 81 #define AST_DRAM_8Gx16 8 82 83 /* 84 * Cursor plane 85 */ 86 87 #define AST_MAX_HWC_WIDTH 64 88 #define AST_MAX_HWC_HEIGHT 64 89 90 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) 91 #define AST_HWC_SIGNATURE_SIZE 32 92 93 #define AST_DEFAULT_HWC_NUM 2 94 95 /* define for signature structure */ 96 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 97 #define AST_HWC_SIGNATURE_SizeX 0x04 98 #define AST_HWC_SIGNATURE_SizeY 0x08 99 #define AST_HWC_SIGNATURE_X 0x0C 100 #define AST_HWC_SIGNATURE_Y 0x10 101 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 102 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 103 104 struct ast_cursor_plane { 105 struct drm_plane base; 106 107 struct { 108 struct drm_gem_vram_object *gbo; 109 struct iosys_map map; 110 u64 off; 111 } hwc[AST_DEFAULT_HWC_NUM]; 112 113 unsigned int next_hwc_index; 114 }; 115 116 static inline struct ast_cursor_plane * 117 to_ast_cursor_plane(struct drm_plane *plane) 118 { 119 return container_of(plane, struct ast_cursor_plane, base); 120 } 121 122 /* 123 * Connector with i2c channel 124 */ 125 126 struct ast_i2c_chan { 127 struct i2c_adapter adapter; 128 struct drm_device *dev; 129 struct i2c_algo_bit_data bit; 130 }; 131 132 struct ast_vga_connector { 133 struct drm_connector base; 134 struct ast_i2c_chan *i2c; 135 }; 136 137 static inline struct ast_vga_connector * 138 to_ast_vga_connector(struct drm_connector *connector) 139 { 140 return container_of(connector, struct ast_vga_connector, base); 141 } 142 143 struct ast_sil164_connector { 144 struct drm_connector base; 145 struct ast_i2c_chan *i2c; 146 }; 147 148 static inline struct ast_sil164_connector * 149 to_ast_sil164_connector(struct drm_connector *connector) 150 { 151 return container_of(connector, struct ast_sil164_connector, base); 152 } 153 154 /* 155 * Device 156 */ 157 158 struct ast_private { 159 struct drm_device base; 160 161 void __iomem *regs; 162 void __iomem *ioregs; 163 void __iomem *dp501_fw_buf; 164 165 enum ast_chip chip; 166 bool vga2_clone; 167 uint32_t dram_bus_width; 168 uint32_t dram_type; 169 uint32_t mclk; 170 171 struct drm_plane primary_plane; 172 struct ast_cursor_plane cursor_plane; 173 struct drm_crtc crtc; 174 union { 175 struct { 176 struct drm_encoder encoder; 177 struct ast_vga_connector vga_connector; 178 } vga; 179 struct { 180 struct drm_encoder encoder; 181 struct ast_sil164_connector sil164_connector; 182 } sil164; 183 struct { 184 struct drm_encoder encoder; 185 struct drm_connector connector; 186 } dp501; 187 } output; 188 189 bool support_wide_screen; 190 enum { 191 ast_use_p2a, 192 ast_use_dt, 193 ast_use_defaults 194 } config_mode; 195 196 enum ast_tx_chip tx_chip_type; 197 u8 *dp501_fw_addr; 198 const struct firmware *dp501_fw; /* dp501 fw */ 199 }; 200 201 static inline struct ast_private *to_ast_private(struct drm_device *dev) 202 { 203 return container_of(dev, struct ast_private, base); 204 } 205 206 struct ast_private *ast_device_create(const struct drm_driver *drv, 207 struct pci_dev *pdev, 208 unsigned long flags); 209 210 #define AST_IO_AR_PORT_WRITE (0x40) 211 #define AST_IO_MISC_PORT_WRITE (0x42) 212 #define AST_IO_VGA_ENABLE_PORT (0x43) 213 #define AST_IO_SEQ_PORT (0x44) 214 #define AST_IO_DAC_INDEX_READ (0x47) 215 #define AST_IO_DAC_INDEX_WRITE (0x48) 216 #define AST_IO_DAC_DATA (0x49) 217 #define AST_IO_GR_PORT (0x4E) 218 #define AST_IO_CRTC_PORT (0x54) 219 #define AST_IO_INPUT_STATUS1_READ (0x5A) 220 #define AST_IO_MISC_PORT_READ (0x4C) 221 222 #define AST_IO_MM_OFFSET (0x380) 223 224 #define AST_IO_VGAIR1_VREFRESH BIT(3) 225 226 #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) 227 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ 228 229 #define __ast_read(x) \ 230 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 231 u##x val = 0;\ 232 val = ioread##x(ast->regs + reg); \ 233 return val;\ 234 } 235 236 __ast_read(8); 237 __ast_read(16); 238 __ast_read(32) 239 240 #define __ast_io_read(x) \ 241 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ 242 u##x val = 0;\ 243 val = ioread##x(ast->ioregs + reg); \ 244 return val;\ 245 } 246 247 __ast_io_read(8); 248 __ast_io_read(16); 249 __ast_io_read(32); 250 251 #define __ast_write(x) \ 252 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 253 iowrite##x(val, ast->regs + reg);\ 254 } 255 256 __ast_write(8); 257 __ast_write(16); 258 __ast_write(32); 259 260 #define __ast_io_write(x) \ 261 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 262 iowrite##x(val, ast->ioregs + reg);\ 263 } 264 265 __ast_io_write(8); 266 __ast_io_write(16); 267 #undef __ast_io_write 268 269 static inline void ast_set_index_reg(struct ast_private *ast, 270 uint32_t base, uint8_t index, 271 uint8_t val) 272 { 273 ast_io_write16(ast, base, ((u16)val << 8) | index); 274 } 275 276 void ast_set_index_reg_mask(struct ast_private *ast, 277 uint32_t base, uint8_t index, 278 uint8_t mask, uint8_t val); 279 uint8_t ast_get_index_reg(struct ast_private *ast, 280 uint32_t base, uint8_t index); 281 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 282 uint32_t base, uint8_t index, uint8_t mask); 283 284 static inline void ast_open_key(struct ast_private *ast) 285 { 286 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 287 } 288 289 #define AST_VIDMEM_SIZE_8M 0x00800000 290 #define AST_VIDMEM_SIZE_16M 0x01000000 291 #define AST_VIDMEM_SIZE_32M 0x02000000 292 #define AST_VIDMEM_SIZE_64M 0x04000000 293 #define AST_VIDMEM_SIZE_128M 0x08000000 294 295 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 296 297 struct ast_vbios_stdtable { 298 u8 misc; 299 u8 seq[4]; 300 u8 crtc[25]; 301 u8 ar[20]; 302 u8 gr[9]; 303 }; 304 305 struct ast_vbios_enhtable { 306 u32 ht; 307 u32 hde; 308 u32 hfp; 309 u32 hsync; 310 u32 vt; 311 u32 vde; 312 u32 vfp; 313 u32 vsync; 314 u32 dclk_index; 315 u32 flags; 316 u32 refresh_rate; 317 u32 refresh_rate_index; 318 u32 mode_id; 319 }; 320 321 struct ast_vbios_dclk_info { 322 u8 param1; 323 u8 param2; 324 u8 param3; 325 }; 326 327 struct ast_vbios_mode_info { 328 const struct ast_vbios_stdtable *std_table; 329 const struct ast_vbios_enhtable *enh_table; 330 }; 331 332 struct ast_crtc_state { 333 struct drm_crtc_state base; 334 335 /* Last known format of primary plane */ 336 const struct drm_format_info *format; 337 338 struct ast_vbios_mode_info vbios_mode_info; 339 }; 340 341 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) 342 343 int ast_mode_config_init(struct ast_private *ast); 344 345 #define AST_MM_ALIGN_SHIFT 4 346 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 347 348 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4) 349 #define AST_DP501_FW_VERSION_1 BIT(4) 350 #define AST_DP501_PNP_CONNECTED BIT(1) 351 352 #define AST_DP501_DEFAULT_DCLK 65 353 354 #define AST_DP501_GBL_VERSION 0xf000 355 #define AST_DP501_PNPMONITOR 0xf010 356 #define AST_DP501_LINKRATE 0xf014 357 #define AST_DP501_EDID_DATA 0xf020 358 359 /* Define for Soc scratched reg */ 360 #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6) 361 //#define AST_VRAM_INIT_BY_BMC BIT(7) 362 //#define AST_VRAM_INIT_READY BIT(6) 363 364 int ast_mm_init(struct ast_private *ast); 365 366 /* ast post */ 367 void ast_enable_vga(struct drm_device *dev); 368 void ast_enable_mmio(struct drm_device *dev); 369 bool ast_is_vga_enabled(struct drm_device *dev); 370 void ast_post_gpu(struct drm_device *dev); 371 u32 ast_mindwm(struct ast_private *ast, u32 r); 372 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); 373 void ast_patch_ahb_2500(struct ast_private *ast); 374 /* ast dp501 */ 375 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 376 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 377 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 378 u8 ast_get_dp501_max_clk(struct drm_device *dev); 379 void ast_init_3rdtx(struct drm_device *dev); 380 381 /* ast_i2c.c */ 382 struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 383 384 #endif 385