1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <linux/types.h> 32 #include <linux/io.h> 33 #include <linux/i2c.h> 34 #include <linux/i2c-algo-bit.h> 35 36 #include <drm/drm_connector.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_mode.h> 40 #include <drm/drm_framebuffer.h> 41 #include <drm/drm_fb_helper.h> 42 43 #define DRIVER_AUTHOR "Dave Airlie" 44 45 #define DRIVER_NAME "ast" 46 #define DRIVER_DESC "AST" 47 #define DRIVER_DATE "20120228" 48 49 #define DRIVER_MAJOR 0 50 #define DRIVER_MINOR 1 51 #define DRIVER_PATCHLEVEL 0 52 53 #define PCI_CHIP_AST2000 0x2000 54 #define PCI_CHIP_AST2100 0x2010 55 56 57 enum ast_chip { 58 AST2000, 59 AST2100, 60 AST1100, 61 AST2200, 62 AST2150, 63 AST2300, 64 AST2400, 65 AST2500, 66 }; 67 68 enum ast_tx_chip { 69 AST_TX_NONE, 70 AST_TX_SIL164, 71 AST_TX_ITE66121, 72 AST_TX_DP501, 73 }; 74 75 #define AST_DRAM_512Mx16 0 76 #define AST_DRAM_1Gx16 1 77 #define AST_DRAM_512Mx32 2 78 #define AST_DRAM_1Gx32 3 79 #define AST_DRAM_2Gx16 6 80 #define AST_DRAM_4Gx16 7 81 #define AST_DRAM_8Gx16 8 82 83 84 #define AST_MAX_HWC_WIDTH 64 85 #define AST_MAX_HWC_HEIGHT 64 86 87 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) 88 #define AST_HWC_SIGNATURE_SIZE 32 89 90 #define AST_DEFAULT_HWC_NUM 2 91 92 /* define for signature structure */ 93 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 94 #define AST_HWC_SIGNATURE_SizeX 0x04 95 #define AST_HWC_SIGNATURE_SizeY 0x08 96 #define AST_HWC_SIGNATURE_X 0x0C 97 #define AST_HWC_SIGNATURE_Y 0x10 98 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 99 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 100 101 102 struct ast_private { 103 struct drm_device *dev; 104 105 void __iomem *regs; 106 void __iomem *ioregs; 107 108 enum ast_chip chip; 109 bool vga2_clone; 110 uint32_t dram_bus_width; 111 uint32_t dram_type; 112 uint32_t mclk; 113 uint32_t vram_size; 114 115 int fb_mtrr; 116 117 struct { 118 struct drm_gem_vram_object *gbo[AST_DEFAULT_HWC_NUM]; 119 unsigned int next_index; 120 } cursor; 121 122 struct drm_encoder encoder; 123 struct drm_plane primary_plane; 124 struct drm_plane cursor_plane; 125 126 bool support_wide_screen; 127 enum { 128 ast_use_p2a, 129 ast_use_dt, 130 ast_use_defaults 131 } config_mode; 132 133 enum ast_tx_chip tx_chip_type; 134 u8 dp501_maxclk; 135 u8 *dp501_fw_addr; 136 const struct firmware *dp501_fw; /* dp501 fw */ 137 }; 138 139 static inline struct ast_private *to_ast_private(struct drm_device *dev) 140 { 141 return dev->dev_private; 142 } 143 144 int ast_driver_load(struct drm_device *dev, unsigned long flags); 145 void ast_driver_unload(struct drm_device *dev); 146 147 #define AST_IO_AR_PORT_WRITE (0x40) 148 #define AST_IO_MISC_PORT_WRITE (0x42) 149 #define AST_IO_VGA_ENABLE_PORT (0x43) 150 #define AST_IO_SEQ_PORT (0x44) 151 #define AST_IO_DAC_INDEX_READ (0x47) 152 #define AST_IO_DAC_INDEX_WRITE (0x48) 153 #define AST_IO_DAC_DATA (0x49) 154 #define AST_IO_GR_PORT (0x4E) 155 #define AST_IO_CRTC_PORT (0x54) 156 #define AST_IO_INPUT_STATUS1_READ (0x5A) 157 #define AST_IO_MISC_PORT_READ (0x4C) 158 159 #define AST_IO_MM_OFFSET (0x380) 160 161 #define __ast_read(x) \ 162 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 163 u##x val = 0;\ 164 val = ioread##x(ast->regs + reg); \ 165 return val;\ 166 } 167 168 __ast_read(8); 169 __ast_read(16); 170 __ast_read(32) 171 172 #define __ast_io_read(x) \ 173 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ 174 u##x val = 0;\ 175 val = ioread##x(ast->ioregs + reg); \ 176 return val;\ 177 } 178 179 __ast_io_read(8); 180 __ast_io_read(16); 181 __ast_io_read(32); 182 183 #define __ast_write(x) \ 184 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 185 iowrite##x(val, ast->regs + reg);\ 186 } 187 188 __ast_write(8); 189 __ast_write(16); 190 __ast_write(32); 191 192 #define __ast_io_write(x) \ 193 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 194 iowrite##x(val, ast->ioregs + reg);\ 195 } 196 197 __ast_io_write(8); 198 __ast_io_write(16); 199 #undef __ast_io_write 200 201 static inline void ast_set_index_reg(struct ast_private *ast, 202 uint32_t base, uint8_t index, 203 uint8_t val) 204 { 205 ast_io_write16(ast, base, ((u16)val << 8) | index); 206 } 207 208 void ast_set_index_reg_mask(struct ast_private *ast, 209 uint32_t base, uint8_t index, 210 uint8_t mask, uint8_t val); 211 uint8_t ast_get_index_reg(struct ast_private *ast, 212 uint32_t base, uint8_t index); 213 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 214 uint32_t base, uint8_t index, uint8_t mask); 215 216 static inline void ast_open_key(struct ast_private *ast) 217 { 218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 219 } 220 221 #define AST_VIDMEM_SIZE_8M 0x00800000 222 #define AST_VIDMEM_SIZE_16M 0x01000000 223 #define AST_VIDMEM_SIZE_32M 0x02000000 224 #define AST_VIDMEM_SIZE_64M 0x04000000 225 #define AST_VIDMEM_SIZE_128M 0x08000000 226 227 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 228 229 struct ast_i2c_chan { 230 struct i2c_adapter adapter; 231 struct drm_device *dev; 232 struct i2c_algo_bit_data bit; 233 }; 234 235 struct ast_connector { 236 struct drm_connector base; 237 struct ast_i2c_chan *i2c; 238 }; 239 240 struct ast_crtc { 241 struct drm_crtc base; 242 u8 offset_x, offset_y; 243 }; 244 245 #define to_ast_crtc(x) container_of(x, struct ast_crtc, base) 246 #define to_ast_connector(x) container_of(x, struct ast_connector, base) 247 248 struct ast_vbios_stdtable { 249 u8 misc; 250 u8 seq[4]; 251 u8 crtc[25]; 252 u8 ar[20]; 253 u8 gr[9]; 254 }; 255 256 struct ast_vbios_enhtable { 257 u32 ht; 258 u32 hde; 259 u32 hfp; 260 u32 hsync; 261 u32 vt; 262 u32 vde; 263 u32 vfp; 264 u32 vsync; 265 u32 dclk_index; 266 u32 flags; 267 u32 refresh_rate; 268 u32 refresh_rate_index; 269 u32 mode_id; 270 }; 271 272 struct ast_vbios_dclk_info { 273 u8 param1; 274 u8 param2; 275 u8 param3; 276 }; 277 278 struct ast_vbios_mode_info { 279 const struct ast_vbios_stdtable *std_table; 280 const struct ast_vbios_enhtable *enh_table; 281 }; 282 283 struct ast_crtc_state { 284 struct drm_crtc_state base; 285 286 /* Last known format of primary plane */ 287 const struct drm_format_info *format; 288 289 struct ast_vbios_mode_info vbios_mode_info; 290 }; 291 292 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) 293 294 extern int ast_mode_init(struct drm_device *dev); 295 extern void ast_mode_fini(struct drm_device *dev); 296 297 #define AST_MM_ALIGN_SHIFT 4 298 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 299 300 int ast_mm_init(struct ast_private *ast); 301 void ast_mm_fini(struct ast_private *ast); 302 303 /* ast post */ 304 void ast_enable_vga(struct drm_device *dev); 305 void ast_enable_mmio(struct drm_device *dev); 306 bool ast_is_vga_enabled(struct drm_device *dev); 307 void ast_post_gpu(struct drm_device *dev); 308 u32 ast_mindwm(struct ast_private *ast, u32 r); 309 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); 310 /* ast dp501 */ 311 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 312 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 313 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 314 u8 ast_get_dp501_max_clk(struct drm_device *dev); 315 void ast_init_3rdtx(struct drm_device *dev); 316 void ast_release_firmware(struct drm_device *dev); 317 #endif 318