1 2 #include <linux/firmware.h> 3 #include <drm/drmP.h> 4 #include "ast_drv.h" 5 MODULE_FIRMWARE("ast_dp501_fw.bin"); 6 7 static int ast_load_dp501_microcode(struct drm_device *dev) 8 { 9 struct ast_private *ast = dev->dev_private; 10 11 return request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); 12 } 13 14 static void send_ack(struct ast_private *ast) 15 { 16 u8 sendack; 17 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); 18 sendack |= 0x80; 19 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); 20 } 21 22 static void send_nack(struct ast_private *ast) 23 { 24 u8 sendack; 25 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); 26 sendack &= ~0x80; 27 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); 28 } 29 30 static bool wait_ack(struct ast_private *ast) 31 { 32 u8 waitack; 33 u32 retry = 0; 34 do { 35 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); 36 waitack &= 0x80; 37 udelay(100); 38 } while ((!waitack) && (retry++ < 1000)); 39 40 if (retry < 1000) 41 return true; 42 else 43 return false; 44 } 45 46 static bool wait_nack(struct ast_private *ast) 47 { 48 u8 waitack; 49 u32 retry = 0; 50 do { 51 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); 52 waitack &= 0x80; 53 udelay(100); 54 } while ((waitack) && (retry++ < 1000)); 55 56 if (retry < 1000) 57 return true; 58 else 59 return false; 60 } 61 62 static void set_cmd_trigger(struct ast_private *ast) 63 { 64 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40); 65 } 66 67 static void clear_cmd_trigger(struct ast_private *ast) 68 { 69 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00); 70 } 71 72 #if 0 73 static bool wait_fw_ready(struct ast_private *ast) 74 { 75 u8 waitready; 76 u32 retry = 0; 77 do { 78 waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); 79 waitready &= 0x40; 80 udelay(100); 81 } while ((!waitready) && (retry++ < 1000)); 82 83 if (retry < 1000) 84 return true; 85 else 86 return false; 87 } 88 #endif 89 90 static bool ast_write_cmd(struct drm_device *dev, u8 data) 91 { 92 struct ast_private *ast = dev->dev_private; 93 int retry = 0; 94 if (wait_nack(ast)) { 95 send_nack(ast); 96 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); 97 send_ack(ast); 98 set_cmd_trigger(ast); 99 do { 100 if (wait_ack(ast)) { 101 clear_cmd_trigger(ast); 102 send_nack(ast); 103 return true; 104 } 105 } while (retry++ < 100); 106 } 107 clear_cmd_trigger(ast); 108 send_nack(ast); 109 return false; 110 } 111 112 static bool ast_write_data(struct drm_device *dev, u8 data) 113 { 114 struct ast_private *ast = dev->dev_private; 115 116 if (wait_nack(ast)) { 117 send_nack(ast); 118 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); 119 send_ack(ast); 120 if (wait_ack(ast)) { 121 send_nack(ast); 122 return true; 123 } 124 } 125 send_nack(ast); 126 return false; 127 } 128 129 #if 0 130 static bool ast_read_data(struct drm_device *dev, u8 *data) 131 { 132 struct ast_private *ast = dev->dev_private; 133 u8 tmp; 134 135 *data = 0; 136 137 if (wait_ack(ast) == false) 138 return false; 139 tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff); 140 *data = tmp; 141 if (wait_nack(ast) == false) { 142 send_nack(ast); 143 return false; 144 } 145 send_nack(ast); 146 return true; 147 } 148 149 static void clear_cmd(struct ast_private *ast) 150 { 151 send_nack(ast); 152 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00); 153 } 154 #endif 155 156 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode) 157 { 158 ast_write_cmd(dev, 0x40); 159 ast_write_data(dev, mode); 160 161 msleep(10); 162 } 163 164 static u32 get_fw_base(struct ast_private *ast) 165 { 166 return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff; 167 } 168 169 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size) 170 { 171 struct ast_private *ast = dev->dev_private; 172 u32 i, data; 173 u32 boot_address; 174 175 data = ast_mindwm(ast, 0x1e6e2100) & 0x01; 176 if (data) { 177 boot_address = get_fw_base(ast); 178 for (i = 0; i < size; i += 4) 179 *(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i); 180 return true; 181 } 182 return false; 183 } 184 185 static bool ast_launch_m68k(struct drm_device *dev) 186 { 187 struct ast_private *ast = dev->dev_private; 188 u32 i, data, len = 0; 189 u32 boot_address; 190 u8 *fw_addr = NULL; 191 u8 jreg; 192 193 data = ast_mindwm(ast, 0x1e6e2100) & 0x01; 194 if (!data) { 195 196 if (ast->dp501_fw_addr) { 197 fw_addr = ast->dp501_fw_addr; 198 len = 32*1024; 199 } else { 200 if (!ast->dp501_fw && 201 ast_load_dp501_microcode(dev) < 0) 202 return false; 203 204 fw_addr = (u8 *)ast->dp501_fw->data; 205 len = ast->dp501_fw->size; 206 } 207 /* Get BootAddress */ 208 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); 209 data = ast_mindwm(ast, 0x1e6e0004); 210 switch (data & 0x03) { 211 case 0: 212 boot_address = 0x44000000; 213 break; 214 default: 215 case 1: 216 boot_address = 0x48000000; 217 break; 218 case 2: 219 boot_address = 0x50000000; 220 break; 221 case 3: 222 boot_address = 0x60000000; 223 break; 224 } 225 boot_address -= 0x200000; /* -2MB */ 226 227 /* copy image to buffer */ 228 for (i = 0; i < len; i += 4) { 229 data = *(u32 *)(fw_addr + i); 230 ast_moutdwm(ast, boot_address + i, data); 231 } 232 233 /* Init SCU */ 234 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); 235 236 /* Launch FW */ 237 ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address); 238 ast_moutdwm(ast, 0x1e6e2100, 1); 239 240 /* Update Scratch */ 241 data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */ 242 data |= 0x800; 243 ast_moutdwm(ast, 0x1e6e2040, data); 244 245 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */ 246 jreg |= 0x02; 247 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg); 248 } 249 return true; 250 } 251 252 u8 ast_get_dp501_max_clk(struct drm_device *dev) 253 { 254 struct ast_private *ast = dev->dev_private; 255 u32 boot_address, offset, data; 256 u8 linkcap[4], linkrate, linklanes, maxclk = 0xff; 257 258 boot_address = get_fw_base(ast); 259 260 /* validate FW version */ 261 offset = 0xf000; 262 data = ast_mindwm(ast, boot_address + offset); 263 if ((data & 0xf0) != 0x10) /* version: 1x */ 264 return maxclk; 265 266 /* Read Link Capability */ 267 offset = 0xf014; 268 *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset); 269 if (linkcap[2] == 0) { 270 linkrate = linkcap[0]; 271 linklanes = linkcap[1]; 272 data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes); 273 if (data > 0xff) 274 data = 0xff; 275 maxclk = (u8)data; 276 } 277 return maxclk; 278 } 279 280 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata) 281 { 282 struct ast_private *ast = dev->dev_private; 283 u32 i, boot_address, offset, data; 284 285 boot_address = get_fw_base(ast); 286 287 /* validate FW version */ 288 offset = 0xf000; 289 data = ast_mindwm(ast, boot_address + offset); 290 if ((data & 0xf0) != 0x10) 291 return false; 292 293 /* validate PnP Monitor */ 294 offset = 0xf010; 295 data = ast_mindwm(ast, boot_address + offset); 296 if (!(data & 0x01)) 297 return false; 298 299 /* Read EDID */ 300 offset = 0xf020; 301 for (i = 0; i < 128; i += 4) { 302 data = ast_mindwm(ast, boot_address + offset + i); 303 *(u32 *)(ediddata + i) = data; 304 } 305 306 return true; 307 } 308 309 static bool ast_init_dvo(struct drm_device *dev) 310 { 311 struct ast_private *ast = dev->dev_private; 312 u8 jreg; 313 u32 data; 314 ast_write32(ast, 0xf004, 0x1e6e0000); 315 ast_write32(ast, 0xf000, 0x1); 316 ast_write32(ast, 0x12000, 0x1688a8a8); 317 318 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 319 if (!(jreg & 0x80)) { 320 /* Init SCU DVO Settings */ 321 data = ast_read32(ast, 0x12008); 322 /* delay phase */ 323 data &= 0xfffff8ff; 324 data |= 0x00000500; 325 ast_write32(ast, 0x12008, data); 326 327 if (ast->chip == AST2300) { 328 data = ast_read32(ast, 0x12084); 329 /* multi-pins for DVO single-edge */ 330 data |= 0xfffe0000; 331 ast_write32(ast, 0x12084, data); 332 333 data = ast_read32(ast, 0x12088); 334 /* multi-pins for DVO single-edge */ 335 data |= 0x000fffff; 336 ast_write32(ast, 0x12088, data); 337 338 data = ast_read32(ast, 0x12090); 339 /* multi-pins for DVO single-edge */ 340 data &= 0xffffffcf; 341 data |= 0x00000020; 342 ast_write32(ast, 0x12090, data); 343 } else { /* AST2400 */ 344 data = ast_read32(ast, 0x12088); 345 /* multi-pins for DVO single-edge */ 346 data |= 0x30000000; 347 ast_write32(ast, 0x12088, data); 348 349 data = ast_read32(ast, 0x1208c); 350 /* multi-pins for DVO single-edge */ 351 data |= 0x000000cf; 352 ast_write32(ast, 0x1208c, data); 353 354 data = ast_read32(ast, 0x120a4); 355 /* multi-pins for DVO single-edge */ 356 data |= 0xffff0000; 357 ast_write32(ast, 0x120a4, data); 358 359 data = ast_read32(ast, 0x120a8); 360 /* multi-pins for DVO single-edge */ 361 data |= 0x0000000f; 362 ast_write32(ast, 0x120a8, data); 363 364 data = ast_read32(ast, 0x12094); 365 /* multi-pins for DVO single-edge */ 366 data |= 0x00000002; 367 ast_write32(ast, 0x12094, data); 368 } 369 } 370 371 /* Force to DVO */ 372 data = ast_read32(ast, 0x1202c); 373 data &= 0xfffbffff; 374 ast_write32(ast, 0x1202c, data); 375 376 /* Init VGA DVO Settings */ 377 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); 378 return true; 379 } 380 381 382 static void ast_init_analog(struct drm_device *dev) 383 { 384 struct ast_private *ast = dev->dev_private; 385 u32 data; 386 387 /* 388 * Set DAC source to VGA mode in SCU2C via the P2A 389 * bridge. First configure the P2U to target the SCU 390 * in case it isn't at this stage. 391 */ 392 ast_write32(ast, 0xf004, 0x1e6e0000); 393 ast_write32(ast, 0xf000, 0x1); 394 395 /* Then unlock the SCU with the magic password */ 396 ast_write32(ast, 0x12000, 0x1688a8a8); 397 ast_write32(ast, 0x12000, 0x1688a8a8); 398 ast_write32(ast, 0x12000, 0x1688a8a8); 399 400 /* Finally, clear bits [17:16] of SCU2c */ 401 data = ast_read32(ast, 0x1202c); 402 data &= 0xfffcffff; 403 ast_write32(ast, 0, data); 404 405 /* Disable DVO */ 406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00); 407 } 408 409 void ast_init_3rdtx(struct drm_device *dev) 410 { 411 struct ast_private *ast = dev->dev_private; 412 u8 jreg; 413 414 if (ast->chip == AST2300 || ast->chip == AST2400) { 415 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 416 switch (jreg & 0x0e) { 417 case 0x04: 418 ast_init_dvo(dev); 419 break; 420 case 0x08: 421 ast_launch_m68k(dev); 422 break; 423 case 0x0c: 424 ast_init_dvo(dev); 425 break; 426 default: 427 if (ast->tx_chip_type == AST_TX_SIL164) 428 ast_init_dvo(dev); 429 else 430 ast_init_analog(dev); 431 } 432 } 433 } 434 435 void ast_release_firmware(struct drm_device *dev) 436 { 437 struct ast_private *ast = dev->dev_private; 438 439 release_firmware(ast->dp501_fw); 440 ast->dp501_fw = NULL; 441 } 442