1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2d40af7b1SRussell King /*
3d40af7b1SRussell King * Copyright (C) 2012 Russell King
4d40af7b1SRussell King * Rewritten from the dovefb driver, and Armada510 manuals.
5d40af7b1SRussell King */
625e28ef2SSam Ravnborg
7d40af7b1SRussell King #include <drm/drm_atomic.h>
8d40af7b1SRussell King #include <drm/drm_atomic_helper.h>
925e28ef2SSam Ravnborg #include <drm/drm_fourcc.h>
10d40af7b1SRussell King #include <drm/drm_plane_helper.h>
1125e28ef2SSam Ravnborg
12d40af7b1SRussell King #include "armada_crtc.h"
13d40af7b1SRussell King #include "armada_drm.h"
14d40af7b1SRussell King #include "armada_fb.h"
15d40af7b1SRussell King #include "armada_gem.h"
16d40af7b1SRussell King #include "armada_hw.h"
17d40af7b1SRussell King #include "armada_plane.h"
18d40af7b1SRussell King #include "armada_trace.h"
19d40af7b1SRussell King
20d40af7b1SRussell King static const uint32_t armada_primary_formats[] = {
21d40af7b1SRussell King DRM_FORMAT_UYVY,
22d40af7b1SRussell King DRM_FORMAT_YUYV,
23d40af7b1SRussell King DRM_FORMAT_VYUY,
24d40af7b1SRussell King DRM_FORMAT_YVYU,
25d40af7b1SRussell King DRM_FORMAT_ARGB8888,
26d40af7b1SRussell King DRM_FORMAT_ABGR8888,
27d40af7b1SRussell King DRM_FORMAT_XRGB8888,
28d40af7b1SRussell King DRM_FORMAT_XBGR8888,
29d40af7b1SRussell King DRM_FORMAT_RGB888,
30d40af7b1SRussell King DRM_FORMAT_BGR888,
31d40af7b1SRussell King DRM_FORMAT_ARGB1555,
32d40af7b1SRussell King DRM_FORMAT_ABGR1555,
33d40af7b1SRussell King DRM_FORMAT_RGB565,
34d40af7b1SRussell King DRM_FORMAT_BGR565,
35d40af7b1SRussell King };
36d40af7b1SRussell King
armada_drm_plane_calc(struct drm_plane_state * state,u32 addrs[2][3],u16 pitches[3],bool interlaced)37b5bae71aSRussell King void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3],
38b5bae71aSRussell King u16 pitches[3], bool interlaced)
39d40af7b1SRussell King {
40b4df3ba0SRussell King struct drm_framebuffer *fb = state->fb;
41d40af7b1SRussell King const struct drm_format_info *format = fb->format;
42d40af7b1SRussell King unsigned int num_planes = format->num_planes;
43b4df3ba0SRussell King unsigned int x = state->src.x1 >> 16;
44b4df3ba0SRussell King unsigned int y = state->src.y1 >> 16;
45d40af7b1SRussell King u32 addr = drm_fb_obj(fb)->dev_addr;
46d40af7b1SRussell King int i;
47d40af7b1SRussell King
48b4df3ba0SRussell King DRM_DEBUG_KMS("pitch %u x %d y %d bpp %d\n",
49b4df3ba0SRussell King fb->pitches[0], x, y, format->cpp[0] * 8);
50b4df3ba0SRussell King
51d40af7b1SRussell King if (num_planes > 3)
52d40af7b1SRussell King num_planes = 3;
53d40af7b1SRussell King
54b5bae71aSRussell King addrs[0][0] = addr + fb->offsets[0] + y * fb->pitches[0] +
55d40af7b1SRussell King x * format->cpp[0];
564aafe00eSRussell King pitches[0] = fb->pitches[0];
57d40af7b1SRussell King
58d40af7b1SRussell King y /= format->vsub;
59d40af7b1SRussell King x /= format->hsub;
60d40af7b1SRussell King
614aafe00eSRussell King for (i = 1; i < num_planes; i++) {
62b5bae71aSRussell King addrs[0][i] = addr + fb->offsets[i] + y * fb->pitches[i] +
63d40af7b1SRussell King x * format->cpp[i];
644aafe00eSRussell King pitches[i] = fb->pitches[i];
654aafe00eSRussell King }
664aafe00eSRussell King for (; i < 3; i++) {
67b5bae71aSRussell King addrs[0][i] = 0;
684aafe00eSRussell King pitches[i] = 0;
694aafe00eSRussell King }
70b5bae71aSRussell King if (interlaced) {
71b5bae71aSRussell King for (i = 0; i < 3; i++) {
72b5bae71aSRussell King addrs[1][i] = addrs[0][i] + pitches[i];
73b5bae71aSRussell King pitches[i] *= 2;
74b5bae71aSRussell King }
75b5bae71aSRussell King } else {
76b5bae71aSRussell King for (i = 0; i < 3; i++)
77b5bae71aSRussell King addrs[1][i] = addrs[0][i];
78b5bae71aSRussell King }
79d40af7b1SRussell King }
80d40af7b1SRussell King
armada_drm_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)81d40af7b1SRussell King int armada_drm_plane_atomic_check(struct drm_plane *plane,
827c11b99aSMaxime Ripard struct drm_atomic_state *state)
83d40af7b1SRussell King {
847c11b99aSMaxime Ripard struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
857c11b99aSMaxime Ripard plane);
86ba5c1649SMaxime Ripard struct armada_plane_state *st = to_armada_plane_state(new_plane_state);
87ba5c1649SMaxime Ripard struct drm_crtc *crtc = new_plane_state->crtc;
88d40af7b1SRussell King struct drm_crtc_state *crtc_state;
891d1547ecSRussell King bool interlace;
901d1547ecSRussell King int ret;
911d1547ecSRussell King
92ba5c1649SMaxime Ripard if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc)) {
93ba5c1649SMaxime Ripard new_plane_state->visible = false;
941d1547ecSRussell King return 0;
951d1547ecSRussell King }
96d40af7b1SRussell King
97dec92020SMaxime Ripard if (state)
98dec92020SMaxime Ripard crtc_state = drm_atomic_get_existing_crtc_state(state,
99ba5c1649SMaxime Ripard crtc);
100d40af7b1SRussell King else
101d40af7b1SRussell King crtc_state = crtc->state;
1021d1547ecSRussell King
103ba5c1649SMaxime Ripard ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
104ba5c1649SMaxime Ripard 0,
1051d1547ecSRussell King INT_MAX, true, false);
1061d1547ecSRussell King if (ret)
1071d1547ecSRussell King return ret;
1081d1547ecSRussell King
1091d1547ecSRussell King interlace = crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE;
1101d1547ecSRussell King if (interlace) {
111ba5c1649SMaxime Ripard if ((new_plane_state->dst.y1 | new_plane_state->dst.y2) & 1)
1121d1547ecSRussell King return -EINVAL;
113ba5c1649SMaxime Ripard st->src_hw = drm_rect_height(&new_plane_state->src) >> 17;
114ba5c1649SMaxime Ripard st->dst_yx = new_plane_state->dst.y1 >> 1;
115ba5c1649SMaxime Ripard st->dst_hw = drm_rect_height(&new_plane_state->dst) >> 1;
116d40af7b1SRussell King } else {
117ba5c1649SMaxime Ripard st->src_hw = drm_rect_height(&new_plane_state->src) >> 16;
118ba5c1649SMaxime Ripard st->dst_yx = new_plane_state->dst.y1;
119ba5c1649SMaxime Ripard st->dst_hw = drm_rect_height(&new_plane_state->dst);
120d40af7b1SRussell King }
1211d1547ecSRussell King
1221d1547ecSRussell King st->src_hw <<= 16;
123ba5c1649SMaxime Ripard st->src_hw |= drm_rect_width(&new_plane_state->src) >> 16;
1241d1547ecSRussell King st->dst_yx <<= 16;
125ba5c1649SMaxime Ripard st->dst_yx |= new_plane_state->dst.x1 & 0x0000ffff;
1261d1547ecSRussell King st->dst_hw <<= 16;
127ba5c1649SMaxime Ripard st->dst_hw |= drm_rect_width(&new_plane_state->dst) & 0x0000ffff;
1281d1547ecSRussell King
129ba5c1649SMaxime Ripard armada_drm_plane_calc(new_plane_state, st->addrs, st->pitches,
130ba5c1649SMaxime Ripard interlace);
1317d62237dSRussell King st->interlace = interlace;
1327d62237dSRussell King
133d40af7b1SRussell King return 0;
134d40af7b1SRussell King }
135d40af7b1SRussell King
armada_drm_primary_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)136d40af7b1SRussell King static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
137977697e2SMaxime Ripard struct drm_atomic_state *state)
138d40af7b1SRussell King {
139977697e2SMaxime Ripard struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
140977697e2SMaxime Ripard plane);
14137418bf1SMaxime Ripard struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
14237418bf1SMaxime Ripard plane);
143d40af7b1SRussell King struct armada_crtc *dcrtc;
144d40af7b1SRussell King struct armada_regs *regs;
145d40af7b1SRussell King u32 cfg, cfg_mask, val;
146d40af7b1SRussell King unsigned int idx;
147d40af7b1SRussell King
148d40af7b1SRussell King DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
149d40af7b1SRussell King
15041016fe1SMaxime Ripard if (!new_state->fb || WARN_ON(!new_state->crtc))
151d40af7b1SRussell King return;
152d40af7b1SRussell King
153d40af7b1SRussell King DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
154d40af7b1SRussell King plane->base.id, plane->name,
15541016fe1SMaxime Ripard new_state->crtc->base.id, new_state->crtc->name,
15641016fe1SMaxime Ripard new_state->fb->base.id,
15741016fe1SMaxime Ripard old_state->visible, new_state->visible);
158d40af7b1SRussell King
15941016fe1SMaxime Ripard dcrtc = drm_to_armada_crtc(new_state->crtc);
160d40af7b1SRussell King regs = dcrtc->regs + dcrtc->regs_idx;
161d40af7b1SRussell King
162d40af7b1SRussell King idx = 0;
16341016fe1SMaxime Ripard if (!old_state->visible && new_state->visible) {
164d40af7b1SRussell King val = CFG_PDWN64x66;
16541016fe1SMaxime Ripard if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)
166d40af7b1SRussell King val |= CFG_PDWN256x24;
167d40af7b1SRussell King armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
168d40af7b1SRussell King }
16941016fe1SMaxime Ripard val = armada_src_hw(new_state);
1709184ae8dSRussell King if (armada_src_hw(old_state) != val)
171d40af7b1SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
17241016fe1SMaxime Ripard val = armada_dst_yx(new_state);
1739184ae8dSRussell King if (armada_dst_yx(old_state) != val)
174d40af7b1SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
17541016fe1SMaxime Ripard val = armada_dst_hw(new_state);
1769184ae8dSRussell King if (armada_dst_hw(old_state) != val)
177d40af7b1SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
17841016fe1SMaxime Ripard if (old_state->src.x1 != new_state->src.x1 ||
17941016fe1SMaxime Ripard old_state->src.y1 != new_state->src.y1 ||
18041016fe1SMaxime Ripard old_state->fb != new_state->fb ||
18141016fe1SMaxime Ripard new_state->crtc->state->mode_changed) {
18241016fe1SMaxime Ripard armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
1837d62237dSRussell King LCD_CFG_GRA_START_ADDR0);
18441016fe1SMaxime Ripard armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
1857d62237dSRussell King LCD_CFG_GRA_START_ADDR1);
18641016fe1SMaxime Ripard armada_reg_queue_mod(regs, idx, armada_pitch(new_state, 0),
18741016fe1SMaxime Ripard 0xffff,
1887d62237dSRussell King LCD_CFG_GRA_PITCH);
189d40af7b1SRussell King }
19041016fe1SMaxime Ripard if (old_state->fb != new_state->fb ||
19141016fe1SMaxime Ripard new_state->crtc->state->mode_changed) {
19241016fe1SMaxime Ripard cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
19341016fe1SMaxime Ripard CFG_GRA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod);
19441016fe1SMaxime Ripard if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)
195d40af7b1SRussell King cfg |= CFG_PALETTE_ENA;
19641016fe1SMaxime Ripard if (new_state->visible)
197d40af7b1SRussell King cfg |= CFG_GRA_ENA;
19841016fe1SMaxime Ripard if (to_armada_plane_state(new_state)->interlace)
199d40af7b1SRussell King cfg |= CFG_GRA_FTOGGLE;
200d40af7b1SRussell King cfg_mask = CFG_GRAFORMAT |
201d40af7b1SRussell King CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
202d40af7b1SRussell King CFG_SWAPYU | CFG_YUV2RGB) |
203d40af7b1SRussell King CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
204d40af7b1SRussell King CFG_GRA_ENA;
20541016fe1SMaxime Ripard } else if (old_state->visible != new_state->visible) {
20641016fe1SMaxime Ripard cfg = new_state->visible ? CFG_GRA_ENA : 0;
207d40af7b1SRussell King cfg_mask = CFG_GRA_ENA;
208d40af7b1SRussell King } else {
209d40af7b1SRussell King cfg = cfg_mask = 0;
210d40af7b1SRussell King }
21141016fe1SMaxime Ripard if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
21241016fe1SMaxime Ripard drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
213d40af7b1SRussell King cfg_mask |= CFG_GRA_HSMOOTH;
21441016fe1SMaxime Ripard if (drm_rect_width(&new_state->src) >> 16 !=
21541016fe1SMaxime Ripard drm_rect_width(&new_state->dst))
216d40af7b1SRussell King cfg |= CFG_GRA_HSMOOTH;
217d40af7b1SRussell King }
218d40af7b1SRussell King
219d40af7b1SRussell King if (cfg_mask)
220d40af7b1SRussell King armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
221d40af7b1SRussell King LCD_SPU_DMA_CTRL0);
222d40af7b1SRussell King
223d40af7b1SRussell King dcrtc->regs_idx += idx;
224d40af7b1SRussell King }
225d40af7b1SRussell King
armada_drm_primary_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)226d40af7b1SRussell King static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane,
227977697e2SMaxime Ripard struct drm_atomic_state *state)
228d40af7b1SRussell King {
229977697e2SMaxime Ripard struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
230977697e2SMaxime Ripard plane);
231d40af7b1SRussell King struct armada_crtc *dcrtc;
232d40af7b1SRussell King struct armada_regs *regs;
233d40af7b1SRussell King unsigned int idx = 0;
234d40af7b1SRussell King
235d40af7b1SRussell King DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
236d40af7b1SRussell King
237d40af7b1SRussell King if (!old_state->crtc)
238d40af7b1SRussell King return;
239d40af7b1SRussell King
240d40af7b1SRussell King DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
241d40af7b1SRussell King plane->base.id, plane->name,
242d40af7b1SRussell King old_state->crtc->base.id, old_state->crtc->name,
243d40af7b1SRussell King old_state->fb->base.id);
244d40af7b1SRussell King
245d40af7b1SRussell King dcrtc = drm_to_armada_crtc(old_state->crtc);
246d40af7b1SRussell King regs = dcrtc->regs + dcrtc->regs_idx;
247d40af7b1SRussell King
248d40af7b1SRussell King /* Disable plane and power down most RAMs and FIFOs */
249d40af7b1SRussell King armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
250d40af7b1SRussell King armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |
251d0d765deSRussell King CFG_PDWN32x32 | CFG_PDWN64x66,
252d40af7b1SRussell King 0, LCD_SPU_SRAM_PARA1);
253d40af7b1SRussell King
254d40af7b1SRussell King dcrtc->regs_idx += idx;
255d40af7b1SRussell King }
256d40af7b1SRussell King
257d40af7b1SRussell King static const struct drm_plane_helper_funcs armada_primary_plane_helper_funcs = {
258d40af7b1SRussell King .atomic_check = armada_drm_plane_atomic_check,
259d40af7b1SRussell King .atomic_update = armada_drm_primary_plane_atomic_update,
260d40af7b1SRussell King .atomic_disable = armada_drm_primary_plane_atomic_disable,
261d40af7b1SRussell King };
262d40af7b1SRussell King
armada_plane_reset(struct drm_plane * plane)2631d1547ecSRussell King void armada_plane_reset(struct drm_plane *plane)
2641d1547ecSRussell King {
2651d1547ecSRussell King struct armada_plane_state *st;
2661d1547ecSRussell King if (plane->state)
2671d1547ecSRussell King __drm_atomic_helper_plane_destroy_state(plane->state);
2681d1547ecSRussell King kfree(plane->state);
2691d1547ecSRussell King st = kzalloc(sizeof(*st), GFP_KERNEL);
2701d1547ecSRussell King if (st)
2711d1547ecSRussell King __drm_atomic_helper_plane_reset(plane, &st->base);
2721d1547ecSRussell King }
2731d1547ecSRussell King
armada_plane_duplicate_state(struct drm_plane * plane)2741d1547ecSRussell King struct drm_plane_state *armada_plane_duplicate_state(struct drm_plane *plane)
2751d1547ecSRussell King {
2761d1547ecSRussell King struct armada_plane_state *st;
2771d1547ecSRussell King
2781d1547ecSRussell King if (WARN_ON(!plane->state))
2791d1547ecSRussell King return NULL;
2801d1547ecSRussell King
2811d1547ecSRussell King st = kmemdup(plane->state, sizeof(*st), GFP_KERNEL);
2821d1547ecSRussell King if (st)
2831d1547ecSRussell King __drm_atomic_helper_plane_duplicate_state(plane, &st->base);
2841d1547ecSRussell King
2851d1547ecSRussell King return &st->base;
2861d1547ecSRussell King }
2871d1547ecSRussell King
288d40af7b1SRussell King static const struct drm_plane_funcs armada_primary_plane_funcs = {
28913c94d53SRussell King .update_plane = drm_atomic_helper_update_plane,
29013c94d53SRussell King .disable_plane = drm_atomic_helper_disable_plane,
291*30c63715SThomas Zimmermann .destroy = drm_plane_helper_destroy,
2921d1547ecSRussell King .reset = armada_plane_reset,
2931d1547ecSRussell King .atomic_duplicate_state = armada_plane_duplicate_state,
294d40af7b1SRussell King .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
295d40af7b1SRussell King };
296d40af7b1SRussell King
armada_drm_primary_plane_init(struct drm_device * drm,struct drm_plane * primary)297d40af7b1SRussell King int armada_drm_primary_plane_init(struct drm_device *drm,
29882c702cbSRussell King struct drm_plane *primary)
299d40af7b1SRussell King {
300d40af7b1SRussell King int ret;
301d40af7b1SRussell King
30282c702cbSRussell King drm_plane_helper_add(primary, &armada_primary_plane_helper_funcs);
303d40af7b1SRussell King
30482c702cbSRussell King ret = drm_universal_plane_init(drm, primary, 0,
305d40af7b1SRussell King &armada_primary_plane_funcs,
306d40af7b1SRussell King armada_primary_formats,
307d40af7b1SRussell King ARRAY_SIZE(armada_primary_formats),
308d40af7b1SRussell King NULL,
309d40af7b1SRussell King DRM_PLANE_TYPE_PRIMARY, NULL);
310d40af7b1SRussell King
311d40af7b1SRussell King return ret;
312d40af7b1SRussell King }
313