1 /* 2 * Copyright (C) 2012 Russell King 3 * Rewritten from the dovefb driver, and Armada510 manuals. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 #include <drm/drmP.h> 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_atomic_helper.h> 12 #include <drm/drm_plane_helper.h> 13 #include <drm/armada_drm.h> 14 #include "armada_crtc.h" 15 #include "armada_drm.h" 16 #include "armada_fb.h" 17 #include "armada_gem.h" 18 #include "armada_hw.h" 19 #include "armada_ioctlP.h" 20 #include "armada_plane.h" 21 #include "armada_trace.h" 22 23 #define DEFAULT_BRIGHTNESS 0 24 #define DEFAULT_CONTRAST 0x4000 25 #define DEFAULT_SATURATION 0x4000 26 27 struct armada_ovl_plane { 28 struct armada_plane base; 29 struct armada_plane_work works[2]; 30 bool next_work; 31 bool wait_vblank; 32 }; 33 #define drm_to_armada_ovl_plane(p) \ 34 container_of(p, struct armada_ovl_plane, base.base) 35 36 struct armada_overlay_state { 37 struct drm_plane_state base; 38 u32 colorkey_yr; 39 u32 colorkey_ug; 40 u32 colorkey_vb; 41 u32 colorkey_mode; 42 u32 colorkey_enable; 43 s16 brightness; 44 u16 contrast; 45 u16 saturation; 46 }; 47 #define drm_to_overlay_state(s) \ 48 container_of(s, struct armada_overlay_state, base) 49 50 static inline u32 armada_spu_contrast(struct drm_plane_state *state) 51 { 52 return drm_to_overlay_state(state)->brightness << 16 | 53 drm_to_overlay_state(state)->contrast; 54 } 55 56 static inline u32 armada_spu_saturation(struct drm_plane_state *state) 57 { 58 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */ 59 return drm_to_overlay_state(state)->saturation << 16; 60 } 61 62 /* === Plane support === */ 63 static void armada_ovl_plane_work(struct armada_crtc *dcrtc, 64 struct armada_plane_work *work) 65 { 66 unsigned long flags; 67 68 trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane); 69 70 spin_lock_irqsave(&dcrtc->irq_lock, flags); 71 armada_drm_crtc_update_regs(dcrtc, work->regs); 72 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); 73 } 74 75 static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, 76 struct drm_plane_state *old_state) 77 { 78 struct drm_plane_state *state = plane->state; 79 struct armada_crtc *dcrtc; 80 struct armada_regs *regs; 81 unsigned int idx; 82 u32 cfg, cfg_mask, val; 83 84 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 85 86 if (!state->fb || WARN_ON(!state->crtc)) 87 return; 88 89 DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n", 90 plane->base.id, plane->name, 91 state->crtc->base.id, state->crtc->name, 92 state->fb->base.id, 93 old_state->visible, state->visible); 94 95 dcrtc = drm_to_armada_crtc(state->crtc); 96 regs = dcrtc->regs + dcrtc->regs_idx; 97 98 drm_to_armada_ovl_plane(plane)->wait_vblank = false; 99 100 idx = 0; 101 if (!old_state->visible && state->visible) 102 armada_reg_queue_mod(regs, idx, 103 0, CFG_PDWN16x66 | CFG_PDWN32x66, 104 LCD_SPU_SRAM_PARA1); 105 val = armada_rect_hw_fp(&state->src); 106 if (armada_rect_hw_fp(&old_state->src) != val) 107 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); 108 val = armada_rect_yx(&state->dst); 109 if (armada_rect_yx(&old_state->dst) != val) 110 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); 111 val = armada_rect_hw(&state->dst); 112 if (armada_rect_hw(&old_state->dst) != val) 113 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); 114 /* FIXME: overlay on an interlaced display */ 115 if (old_state->src.x1 != state->src.x1 || 116 old_state->src.y1 != state->src.y1 || 117 old_state->fb != state->fb) { 118 const struct drm_format_info *format; 119 u16 src_x = state->src.x1 >> 16; 120 u16 src_y = state->src.y1 >> 16; 121 u32 addrs[3]; 122 123 armada_drm_plane_calc_addrs(addrs, state->fb, src_x, src_y); 124 125 armada_reg_queue_set(regs, idx, addrs[0], 126 LCD_SPU_DMA_START_ADDR_Y0); 127 armada_reg_queue_set(regs, idx, addrs[1], 128 LCD_SPU_DMA_START_ADDR_U0); 129 armada_reg_queue_set(regs, idx, addrs[2], 130 LCD_SPU_DMA_START_ADDR_V0); 131 armada_reg_queue_set(regs, idx, addrs[0], 132 LCD_SPU_DMA_START_ADDR_Y1); 133 armada_reg_queue_set(regs, idx, addrs[1], 134 LCD_SPU_DMA_START_ADDR_U1); 135 armada_reg_queue_set(regs, idx, addrs[2], 136 LCD_SPU_DMA_START_ADDR_V1); 137 138 val = state->fb->pitches[0] << 16 | state->fb->pitches[0]; 139 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); 140 val = state->fb->pitches[1] << 16 | state->fb->pitches[2]; 141 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); 142 143 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) | 144 CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) | 145 CFG_CBSH_ENA; 146 if (state->visible) 147 cfg |= CFG_DMA_ENA; 148 149 /* 150 * Shifting a YUV packed format image by one pixel causes the 151 * U/V planes to swap. Compensate for it by also toggling 152 * the UV swap. 153 */ 154 format = state->fb->format; 155 if (format->num_planes == 1 && src_x & (format->hsub - 1)) 156 cfg ^= CFG_DMA_MOD(CFG_SWAPUV); 157 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT | 158 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | 159 CFG_SWAPYU | CFG_YUV2RGB) | 160 CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE | 161 CFG_DMA_ENA; 162 163 drm_to_armada_ovl_plane(plane)->wait_vblank = true; 164 } else if (old_state->visible != state->visible) { 165 cfg = state->visible ? CFG_DMA_ENA : 0; 166 cfg_mask = CFG_DMA_ENA; 167 } else { 168 cfg = cfg_mask = 0; 169 } 170 if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) || 171 drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) { 172 cfg_mask |= CFG_DMA_HSMOOTH; 173 if (drm_rect_width(&state->src) >> 16 != 174 drm_rect_width(&state->dst)) 175 cfg |= CFG_DMA_HSMOOTH; 176 } 177 178 if (cfg_mask) 179 armada_reg_queue_mod(regs, idx, cfg, cfg_mask, 180 LCD_SPU_DMA_CTRL0); 181 182 val = armada_spu_contrast(state); 183 if ((!old_state->visible && state->visible) || 184 armada_spu_contrast(old_state) != val) 185 armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST); 186 val = armada_spu_saturation(state); 187 if ((!old_state->visible && state->visible) || 188 armada_spu_saturation(old_state) != val) 189 armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION); 190 if (!old_state->visible && state->visible) 191 armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE); 192 val = drm_to_overlay_state(state)->colorkey_yr; 193 if ((!old_state->visible && state->visible) || 194 drm_to_overlay_state(old_state)->colorkey_yr != val) 195 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y); 196 val = drm_to_overlay_state(state)->colorkey_ug; 197 if ((!old_state->visible && state->visible) || 198 drm_to_overlay_state(old_state)->colorkey_ug != val) 199 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U); 200 val = drm_to_overlay_state(state)->colorkey_vb; 201 if ((!old_state->visible && state->visible) || 202 drm_to_overlay_state(old_state)->colorkey_vb != val) 203 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V); 204 val = drm_to_overlay_state(state)->colorkey_mode; 205 if ((!old_state->visible && state->visible) || 206 drm_to_overlay_state(old_state)->colorkey_mode != val) 207 armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK | 208 CFG_ALPHAM_MASK | CFG_ALPHA_MASK, 209 LCD_SPU_DMA_CTRL1); 210 val = drm_to_overlay_state(state)->colorkey_enable; 211 if (((!old_state->visible && state->visible) || 212 drm_to_overlay_state(old_state)->colorkey_enable != val) && 213 dcrtc->variant->has_spu_adv_reg) 214 armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY | 215 ADV_VIDCOLORKEY, LCD_SPU_ADV_REG); 216 217 dcrtc->regs_idx += idx; 218 } 219 220 static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane, 221 struct drm_plane_state *old_state) 222 { 223 struct armada_crtc *dcrtc; 224 struct armada_regs *regs; 225 unsigned int idx = 0; 226 227 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 228 229 if (!old_state->crtc) 230 return; 231 232 DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n", 233 plane->base.id, plane->name, 234 old_state->crtc->base.id, old_state->crtc->name, 235 old_state->fb->base.id); 236 237 dcrtc = drm_to_armada_crtc(old_state->crtc); 238 regs = dcrtc->regs + dcrtc->regs_idx; 239 240 /* Disable plane and power down the YUV FIFOs */ 241 armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0); 242 armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0, 243 LCD_SPU_SRAM_PARA1); 244 245 dcrtc->regs_idx += idx; 246 247 if (dcrtc->plane == plane) 248 dcrtc->plane = NULL; 249 } 250 251 static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = { 252 .prepare_fb = armada_drm_plane_prepare_fb, 253 .cleanup_fb = armada_drm_plane_cleanup_fb, 254 .atomic_check = armada_drm_plane_atomic_check, 255 .atomic_update = armada_drm_overlay_plane_atomic_update, 256 .atomic_disable = armada_drm_overlay_plane_atomic_disable, 257 }; 258 259 static int armada_overlay_commit(struct drm_plane *plane, 260 struct drm_plane_state *state) 261 { 262 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); 263 const struct drm_plane_helper_funcs *plane_funcs; 264 struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc); 265 struct armada_plane_work *work; 266 int ret; 267 268 plane_funcs = plane->helper_private; 269 ret = plane_funcs->atomic_check(plane, state); 270 if (ret) 271 goto put_state; 272 273 work = &dplane->works[dplane->next_work]; 274 275 if (plane->state->fb != state->fb) { 276 /* 277 * Take a reference on the new framebuffer - we want to 278 * hold on to it while the hardware is displaying it. 279 */ 280 drm_framebuffer_reference(state->fb); 281 282 work->old_fb = plane->state->fb; 283 } else { 284 work->old_fb = NULL; 285 } 286 287 /* Point of no return */ 288 swap(plane->state, state); 289 290 /* No CRTC, can't update */ 291 if (!plane->state->crtc) 292 goto put_state; 293 294 dcrtc->regs_idx = 0; 295 dcrtc->regs = work->regs; 296 297 plane_funcs->atomic_update(plane, state); 298 299 /* If nothing was updated, short-circuit */ 300 if (dcrtc->regs_idx == 0) 301 goto put_state; 302 303 armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx); 304 305 /* Wait for pending work to complete */ 306 if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) 307 armada_drm_plane_work_cancel(dcrtc, &dplane->base); 308 309 /* Just updating the position/size? */ 310 if (!dplane->wait_vblank) { 311 armada_ovl_plane_work(dcrtc, work); 312 goto put_state; 313 } 314 315 dcrtc->plane = plane; 316 317 /* Queue it for update on the next interrupt if we are enabled */ 318 ret = armada_drm_plane_work_queue(dcrtc, work); 319 if (ret) { 320 DRM_ERROR("failed to queue plane work: %d\n", ret); 321 ret = 0; 322 } 323 324 dplane->next_work = !dplane->next_work; 325 326 put_state: 327 plane->funcs->atomic_destroy_state(plane, state); 328 return ret; 329 } 330 331 static int 332 armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, 333 struct drm_framebuffer *fb, 334 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, 335 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, 336 struct drm_modeset_acquire_ctx *ctx) 337 { 338 struct drm_plane_state *state; 339 340 trace_armada_ovl_plane_update(plane, crtc, fb, 341 crtc_x, crtc_y, crtc_w, crtc_h, 342 src_x, src_y, src_w, src_h); 343 344 /* Construct new state for the overlay plane */ 345 state = plane->funcs->atomic_duplicate_state(plane); 346 if (!state) 347 return -ENOMEM; 348 349 state->crtc = crtc; 350 drm_atomic_set_fb_for_plane(state, fb); 351 state->crtc_x = crtc_x; 352 state->crtc_y = crtc_y; 353 state->crtc_h = crtc_h; 354 state->crtc_w = crtc_w; 355 state->src_x = src_x; 356 state->src_y = src_y; 357 state->src_h = src_h; 358 state->src_w = src_w; 359 360 return armada_overlay_commit(plane, state); 361 } 362 363 static void armada_ovl_plane_destroy(struct drm_plane *plane) 364 { 365 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); 366 367 drm_plane_cleanup(plane); 368 369 kfree(dplane); 370 } 371 372 static int armada_ovl_plane_set_property(struct drm_plane *plane, 373 struct drm_property *property, uint64_t val) 374 { 375 struct drm_plane_state *state; 376 int ret; 377 378 state = plane->funcs->atomic_duplicate_state(plane); 379 if (!state) 380 return -ENOMEM; 381 382 ret = plane->funcs->atomic_set_property(plane, state, property, val); 383 if (ret) { 384 plane->funcs->atomic_destroy_state(plane, state); 385 return ret; 386 } 387 388 return armada_overlay_commit(plane, state); 389 } 390 391 static void armada_overlay_reset(struct drm_plane *plane) 392 { 393 struct armada_overlay_state *state; 394 395 if (plane->state) 396 __drm_atomic_helper_plane_destroy_state(plane->state); 397 kfree(plane->state); 398 399 state = kzalloc(sizeof(*state), GFP_KERNEL); 400 if (state) { 401 state->base.plane = plane; 402 state->base.rotation = DRM_MODE_ROTATE_0; 403 state->colorkey_yr = 0xfefefe00; 404 state->colorkey_ug = 0x01010100; 405 state->colorkey_vb = 0x01010100; 406 state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) | 407 CFG_ALPHAM_GRA | CFG_ALPHA(0); 408 state->colorkey_enable = ADV_GRACOLORKEY; 409 state->brightness = DEFAULT_BRIGHTNESS; 410 state->contrast = DEFAULT_CONTRAST; 411 state->saturation = DEFAULT_SATURATION; 412 } 413 plane->state = &state->base; 414 } 415 416 struct drm_plane_state * 417 armada_overlay_duplicate_state(struct drm_plane *plane) 418 { 419 struct armada_overlay_state *state; 420 421 if (WARN_ON(!plane->state)) 422 return NULL; 423 424 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL); 425 if (state) 426 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 427 return &state->base; 428 } 429 430 static int armada_overlay_set_property(struct drm_plane *plane, 431 struct drm_plane_state *state, struct drm_property *property, 432 uint64_t val) 433 { 434 struct armada_private *priv = plane->dev->dev_private; 435 436 #define K2R(val) (((val) >> 0) & 0xff) 437 #define K2G(val) (((val) >> 8) & 0xff) 438 #define K2B(val) (((val) >> 16) & 0xff) 439 if (property == priv->colorkey_prop) { 440 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8) 441 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val)); 442 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val)); 443 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val)); 444 #undef CCC 445 } else if (property == priv->colorkey_min_prop) { 446 drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000; 447 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16; 448 drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000; 449 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16; 450 drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000; 451 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16; 452 } else if (property == priv->colorkey_max_prop) { 453 drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000; 454 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24; 455 drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000; 456 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24; 457 drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000; 458 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24; 459 } else if (property == priv->colorkey_val_prop) { 460 drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00; 461 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8; 462 drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00; 463 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8; 464 drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00; 465 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8; 466 } else if (property == priv->colorkey_alpha_prop) { 467 drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff; 468 drm_to_overlay_state(state)->colorkey_yr |= K2R(val); 469 drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff; 470 drm_to_overlay_state(state)->colorkey_ug |= K2G(val); 471 drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff; 472 drm_to_overlay_state(state)->colorkey_vb |= K2B(val); 473 } else if (property == priv->colorkey_mode_prop) { 474 if (val == CKMODE_DISABLE) { 475 drm_to_overlay_state(state)->colorkey_mode = 476 CFG_CKMODE(CKMODE_DISABLE) | 477 CFG_ALPHAM_CFG | CFG_ALPHA(255); 478 drm_to_overlay_state(state)->colorkey_enable = 0; 479 } else { 480 drm_to_overlay_state(state)->colorkey_mode = 481 CFG_CKMODE(val) | 482 CFG_ALPHAM_GRA | CFG_ALPHA(0); 483 drm_to_overlay_state(state)->colorkey_enable = 484 ADV_GRACOLORKEY; 485 } 486 } else if (property == priv->brightness_prop) { 487 drm_to_overlay_state(state)->brightness = val - 256; 488 } else if (property == priv->contrast_prop) { 489 drm_to_overlay_state(state)->contrast = val; 490 } else if (property == priv->saturation_prop) { 491 drm_to_overlay_state(state)->saturation = val; 492 } else { 493 return -EINVAL; 494 } 495 return 0; 496 } 497 498 static int armada_overlay_get_property(struct drm_plane *plane, 499 const struct drm_plane_state *state, struct drm_property *property, 500 uint64_t *val) 501 { 502 struct armada_private *priv = plane->dev->dev_private; 503 504 #define C2K(c,s) (((c) >> (s)) & 0xff) 505 #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16) 506 if (property == priv->colorkey_prop) { 507 /* Do best-efforts here for this property */ 508 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 509 drm_to_overlay_state(state)->colorkey_ug, 510 drm_to_overlay_state(state)->colorkey_vb, 16); 511 /* If min != max, or min != val, error out */ 512 if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 513 drm_to_overlay_state(state)->colorkey_ug, 514 drm_to_overlay_state(state)->colorkey_vb, 24) || 515 *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 516 drm_to_overlay_state(state)->colorkey_ug, 517 drm_to_overlay_state(state)->colorkey_vb, 8)) 518 return -EINVAL; 519 } else if (property == priv->colorkey_min_prop) { 520 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 521 drm_to_overlay_state(state)->colorkey_ug, 522 drm_to_overlay_state(state)->colorkey_vb, 16); 523 } else if (property == priv->colorkey_max_prop) { 524 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 525 drm_to_overlay_state(state)->colorkey_ug, 526 drm_to_overlay_state(state)->colorkey_vb, 24); 527 } else if (property == priv->colorkey_val_prop) { 528 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 529 drm_to_overlay_state(state)->colorkey_ug, 530 drm_to_overlay_state(state)->colorkey_vb, 8); 531 } else if (property == priv->colorkey_alpha_prop) { 532 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 533 drm_to_overlay_state(state)->colorkey_ug, 534 drm_to_overlay_state(state)->colorkey_vb, 0); 535 } else if (property == priv->colorkey_mode_prop) { 536 *val = (drm_to_overlay_state(state)->colorkey_mode & 537 CFG_CKMODE_MASK) >> ffs(CFG_CKMODE_MASK); 538 } else if (property == priv->brightness_prop) { 539 *val = drm_to_overlay_state(state)->brightness + 256; 540 } else if (property == priv->contrast_prop) { 541 *val = drm_to_overlay_state(state)->contrast; 542 } else if (property == priv->saturation_prop) { 543 *val = drm_to_overlay_state(state)->saturation; 544 } else { 545 return -EINVAL; 546 } 547 return 0; 548 } 549 550 static const struct drm_plane_funcs armada_ovl_plane_funcs = { 551 .update_plane = armada_ovl_plane_update, 552 .disable_plane = drm_plane_helper_disable, 553 .destroy = armada_ovl_plane_destroy, 554 .set_property = armada_ovl_plane_set_property, 555 .reset = armada_overlay_reset, 556 .atomic_duplicate_state = armada_overlay_duplicate_state, 557 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 558 .atomic_set_property = armada_overlay_set_property, 559 .atomic_get_property = armada_overlay_get_property, 560 }; 561 562 static const uint32_t armada_ovl_formats[] = { 563 DRM_FORMAT_UYVY, 564 DRM_FORMAT_YUYV, 565 DRM_FORMAT_YUV420, 566 DRM_FORMAT_YVU420, 567 DRM_FORMAT_YUV422, 568 DRM_FORMAT_YVU422, 569 DRM_FORMAT_VYUY, 570 DRM_FORMAT_YVYU, 571 DRM_FORMAT_ARGB8888, 572 DRM_FORMAT_ABGR8888, 573 DRM_FORMAT_XRGB8888, 574 DRM_FORMAT_XBGR8888, 575 DRM_FORMAT_RGB888, 576 DRM_FORMAT_BGR888, 577 DRM_FORMAT_ARGB1555, 578 DRM_FORMAT_ABGR1555, 579 DRM_FORMAT_RGB565, 580 DRM_FORMAT_BGR565, 581 }; 582 583 static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = { 584 { CKMODE_DISABLE, "disabled" }, 585 { CKMODE_Y, "Y component" }, 586 { CKMODE_U, "U component" }, 587 { CKMODE_V, "V component" }, 588 { CKMODE_RGB, "RGB" }, 589 { CKMODE_R, "R component" }, 590 { CKMODE_G, "G component" }, 591 { CKMODE_B, "B component" }, 592 }; 593 594 static int armada_overlay_create_properties(struct drm_device *dev) 595 { 596 struct armada_private *priv = dev->dev_private; 597 598 if (priv->colorkey_prop) 599 return 0; 600 601 priv->colorkey_prop = drm_property_create_range(dev, 0, 602 "colorkey", 0, 0xffffff); 603 priv->colorkey_min_prop = drm_property_create_range(dev, 0, 604 "colorkey_min", 0, 0xffffff); 605 priv->colorkey_max_prop = drm_property_create_range(dev, 0, 606 "colorkey_max", 0, 0xffffff); 607 priv->colorkey_val_prop = drm_property_create_range(dev, 0, 608 "colorkey_val", 0, 0xffffff); 609 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0, 610 "colorkey_alpha", 0, 0xffffff); 611 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0, 612 "colorkey_mode", 613 armada_drm_colorkey_enum_list, 614 ARRAY_SIZE(armada_drm_colorkey_enum_list)); 615 priv->brightness_prop = drm_property_create_range(dev, 0, 616 "brightness", 0, 256 + 255); 617 priv->contrast_prop = drm_property_create_range(dev, 0, 618 "contrast", 0, 0x7fff); 619 priv->saturation_prop = drm_property_create_range(dev, 0, 620 "saturation", 0, 0x7fff); 621 622 if (!priv->colorkey_prop) 623 return -ENOMEM; 624 625 return 0; 626 } 627 628 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) 629 { 630 struct armada_private *priv = dev->dev_private; 631 struct drm_mode_object *mobj; 632 struct armada_ovl_plane *dplane; 633 int ret; 634 635 ret = armada_overlay_create_properties(dev); 636 if (ret) 637 return ret; 638 639 dplane = kzalloc(sizeof(*dplane), GFP_KERNEL); 640 if (!dplane) 641 return -ENOMEM; 642 643 ret = armada_drm_plane_init(&dplane->base); 644 if (ret) { 645 kfree(dplane); 646 return ret; 647 } 648 649 dplane->works[0].plane = &dplane->base.base; 650 dplane->works[0].fn = armada_ovl_plane_work; 651 dplane->works[1].plane = &dplane->base.base; 652 dplane->works[1].fn = armada_ovl_plane_work; 653 654 drm_plane_helper_add(&dplane->base.base, 655 &armada_overlay_plane_helper_funcs); 656 657 ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs, 658 &armada_ovl_plane_funcs, 659 armada_ovl_formats, 660 ARRAY_SIZE(armada_ovl_formats), 661 NULL, 662 DRM_PLANE_TYPE_OVERLAY, NULL); 663 if (ret) { 664 kfree(dplane); 665 return ret; 666 } 667 668 mobj = &dplane->base.base.base; 669 drm_object_attach_property(mobj, priv->colorkey_prop, 670 0x0101fe); 671 drm_object_attach_property(mobj, priv->colorkey_min_prop, 672 0x0101fe); 673 drm_object_attach_property(mobj, priv->colorkey_max_prop, 674 0x0101fe); 675 drm_object_attach_property(mobj, priv->colorkey_val_prop, 676 0x0101fe); 677 drm_object_attach_property(mobj, priv->colorkey_alpha_prop, 678 0x000000); 679 drm_object_attach_property(mobj, priv->colorkey_mode_prop, 680 CKMODE_RGB); 681 drm_object_attach_property(mobj, priv->brightness_prop, 682 256 + DEFAULT_BRIGHTNESS); 683 drm_object_attach_property(mobj, priv->contrast_prop, 684 DEFAULT_CONTRAST); 685 drm_object_attach_property(mobj, priv->saturation_prop, 686 DEFAULT_SATURATION); 687 688 return 0; 689 } 690