1 /* 2 * Copyright (C) 2012 Russell King 3 * Rewritten from the dovefb driver, and Armada510 manuals. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 #include <drm/drmP.h> 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_atomic_helper.h> 12 #include <drm/drm_plane_helper.h> 13 #include <drm/armada_drm.h> 14 #include "armada_crtc.h" 15 #include "armada_drm.h" 16 #include "armada_fb.h" 17 #include "armada_gem.h" 18 #include "armada_hw.h" 19 #include "armada_ioctlP.h" 20 #include "armada_plane.h" 21 #include "armada_trace.h" 22 23 #define DEFAULT_BRIGHTNESS 0 24 #define DEFAULT_CONTRAST 0x4000 25 #define DEFAULT_SATURATION 0x4000 26 #define DEFAULT_ENCODING DRM_COLOR_YCBCR_BT601 27 28 struct armada_ovl_plane { 29 struct armada_plane base; 30 struct armada_plane_work works[2]; 31 bool next_work; 32 bool wait_vblank; 33 }; 34 #define drm_to_armada_ovl_plane(p) \ 35 container_of(p, struct armada_ovl_plane, base.base) 36 37 struct armada_overlay_state { 38 struct drm_plane_state base; 39 u32 colorkey_yr; 40 u32 colorkey_ug; 41 u32 colorkey_vb; 42 u32 colorkey_mode; 43 u32 colorkey_enable; 44 s16 brightness; 45 u16 contrast; 46 u16 saturation; 47 }; 48 #define drm_to_overlay_state(s) \ 49 container_of(s, struct armada_overlay_state, base) 50 51 static inline u32 armada_spu_contrast(struct drm_plane_state *state) 52 { 53 return drm_to_overlay_state(state)->brightness << 16 | 54 drm_to_overlay_state(state)->contrast; 55 } 56 57 static inline u32 armada_spu_saturation(struct drm_plane_state *state) 58 { 59 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */ 60 return drm_to_overlay_state(state)->saturation << 16; 61 } 62 63 static inline u32 armada_csc(struct drm_plane_state *state) 64 { 65 /* 66 * The CFG_CSC_RGB_* settings control the output of the colour space 67 * converter, setting the range of output values it produces. Since 68 * we will be blending with the full-range graphics, we need to 69 * produce full-range RGB output from the conversion. 70 */ 71 return CFG_CSC_RGB_COMPUTER | 72 (state->color_encoding == DRM_COLOR_YCBCR_BT709 ? 73 CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601); 74 } 75 76 /* === Plane support === */ 77 static void armada_ovl_plane_work(struct armada_crtc *dcrtc, 78 struct armada_plane_work *work) 79 { 80 unsigned long flags; 81 82 trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane); 83 84 spin_lock_irqsave(&dcrtc->irq_lock, flags); 85 armada_drm_crtc_update_regs(dcrtc, work->regs); 86 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); 87 } 88 89 static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, 90 struct drm_plane_state *old_state) 91 { 92 struct drm_plane_state *state = plane->state; 93 struct armada_crtc *dcrtc; 94 struct armada_regs *regs; 95 unsigned int idx; 96 u32 cfg, cfg_mask, val; 97 98 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 99 100 if (!state->fb || WARN_ON(!state->crtc)) 101 return; 102 103 DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n", 104 plane->base.id, plane->name, 105 state->crtc->base.id, state->crtc->name, 106 state->fb->base.id, 107 old_state->visible, state->visible); 108 109 dcrtc = drm_to_armada_crtc(state->crtc); 110 regs = dcrtc->regs + dcrtc->regs_idx; 111 112 drm_to_armada_ovl_plane(plane)->wait_vblank = false; 113 114 idx = 0; 115 if (!old_state->visible && state->visible) 116 armada_reg_queue_mod(regs, idx, 117 0, CFG_PDWN16x66 | CFG_PDWN32x66, 118 LCD_SPU_SRAM_PARA1); 119 val = armada_rect_hw_fp(&state->src); 120 if (armada_rect_hw_fp(&old_state->src) != val) 121 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); 122 val = armada_rect_yx(&state->dst); 123 if (armada_rect_yx(&old_state->dst) != val) 124 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); 125 val = armada_rect_hw(&state->dst); 126 if (armada_rect_hw(&old_state->dst) != val) 127 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); 128 /* FIXME: overlay on an interlaced display */ 129 if (old_state->src.x1 != state->src.x1 || 130 old_state->src.y1 != state->src.y1 || 131 old_state->fb != state->fb) { 132 const struct drm_format_info *format; 133 u16 src_x = state->src.x1 >> 16; 134 u16 src_y = state->src.y1 >> 16; 135 u32 addrs[3]; 136 137 armada_drm_plane_calc_addrs(addrs, state->fb, src_x, src_y); 138 139 armada_reg_queue_set(regs, idx, addrs[0], 140 LCD_SPU_DMA_START_ADDR_Y0); 141 armada_reg_queue_set(regs, idx, addrs[1], 142 LCD_SPU_DMA_START_ADDR_U0); 143 armada_reg_queue_set(regs, idx, addrs[2], 144 LCD_SPU_DMA_START_ADDR_V0); 145 armada_reg_queue_set(regs, idx, addrs[0], 146 LCD_SPU_DMA_START_ADDR_Y1); 147 armada_reg_queue_set(regs, idx, addrs[1], 148 LCD_SPU_DMA_START_ADDR_U1); 149 armada_reg_queue_set(regs, idx, addrs[2], 150 LCD_SPU_DMA_START_ADDR_V1); 151 152 val = state->fb->pitches[0] << 16 | state->fb->pitches[0]; 153 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); 154 val = state->fb->pitches[1] << 16 | state->fb->pitches[2]; 155 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); 156 157 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) | 158 CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) | 159 CFG_CBSH_ENA; 160 if (state->visible) 161 cfg |= CFG_DMA_ENA; 162 163 /* 164 * Shifting a YUV packed format image by one pixel causes the 165 * U/V planes to swap. Compensate for it by also toggling 166 * the UV swap. 167 */ 168 format = state->fb->format; 169 if (format->num_planes == 1 && src_x & (format->hsub - 1)) 170 cfg ^= CFG_DMA_MOD(CFG_SWAPUV); 171 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT | 172 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | 173 CFG_SWAPYU | CFG_YUV2RGB) | 174 CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE | 175 CFG_DMA_ENA; 176 177 drm_to_armada_ovl_plane(plane)->wait_vblank = true; 178 } else if (old_state->visible != state->visible) { 179 cfg = state->visible ? CFG_DMA_ENA : 0; 180 cfg_mask = CFG_DMA_ENA; 181 } else { 182 cfg = cfg_mask = 0; 183 } 184 if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) || 185 drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) { 186 cfg_mask |= CFG_DMA_HSMOOTH; 187 if (drm_rect_width(&state->src) >> 16 != 188 drm_rect_width(&state->dst)) 189 cfg |= CFG_DMA_HSMOOTH; 190 } 191 192 if (cfg_mask) 193 armada_reg_queue_mod(regs, idx, cfg, cfg_mask, 194 LCD_SPU_DMA_CTRL0); 195 196 val = armada_spu_contrast(state); 197 if ((!old_state->visible && state->visible) || 198 armada_spu_contrast(old_state) != val) 199 armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST); 200 val = armada_spu_saturation(state); 201 if ((!old_state->visible && state->visible) || 202 armada_spu_saturation(old_state) != val) 203 armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION); 204 if (!old_state->visible && state->visible) 205 armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE); 206 val = armada_csc(state); 207 if ((!old_state->visible && state->visible) || 208 armada_csc(old_state) != val) 209 armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK, 210 LCD_SPU_IOPAD_CONTROL); 211 val = drm_to_overlay_state(state)->colorkey_yr; 212 if ((!old_state->visible && state->visible) || 213 drm_to_overlay_state(old_state)->colorkey_yr != val) 214 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y); 215 val = drm_to_overlay_state(state)->colorkey_ug; 216 if ((!old_state->visible && state->visible) || 217 drm_to_overlay_state(old_state)->colorkey_ug != val) 218 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U); 219 val = drm_to_overlay_state(state)->colorkey_vb; 220 if ((!old_state->visible && state->visible) || 221 drm_to_overlay_state(old_state)->colorkey_vb != val) 222 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V); 223 val = drm_to_overlay_state(state)->colorkey_mode; 224 if ((!old_state->visible && state->visible) || 225 drm_to_overlay_state(old_state)->colorkey_mode != val) 226 armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK | 227 CFG_ALPHAM_MASK | CFG_ALPHA_MASK, 228 LCD_SPU_DMA_CTRL1); 229 val = drm_to_overlay_state(state)->colorkey_enable; 230 if (((!old_state->visible && state->visible) || 231 drm_to_overlay_state(old_state)->colorkey_enable != val) && 232 dcrtc->variant->has_spu_adv_reg) 233 armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY | 234 ADV_VIDCOLORKEY, LCD_SPU_ADV_REG); 235 236 dcrtc->regs_idx += idx; 237 } 238 239 static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane, 240 struct drm_plane_state *old_state) 241 { 242 struct armada_crtc *dcrtc; 243 struct armada_regs *regs; 244 unsigned int idx = 0; 245 246 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 247 248 if (!old_state->crtc) 249 return; 250 251 DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n", 252 plane->base.id, plane->name, 253 old_state->crtc->base.id, old_state->crtc->name, 254 old_state->fb->base.id); 255 256 dcrtc = drm_to_armada_crtc(old_state->crtc); 257 regs = dcrtc->regs + dcrtc->regs_idx; 258 259 /* Disable plane and power down the YUV FIFOs */ 260 armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0); 261 armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0, 262 LCD_SPU_SRAM_PARA1); 263 264 dcrtc->regs_idx += idx; 265 266 if (dcrtc->plane == plane) 267 dcrtc->plane = NULL; 268 } 269 270 static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = { 271 .prepare_fb = armada_drm_plane_prepare_fb, 272 .cleanup_fb = armada_drm_plane_cleanup_fb, 273 .atomic_check = armada_drm_plane_atomic_check, 274 .atomic_update = armada_drm_overlay_plane_atomic_update, 275 .atomic_disable = armada_drm_overlay_plane_atomic_disable, 276 }; 277 278 static int armada_overlay_commit(struct drm_plane *plane, 279 struct drm_plane_state *state) 280 { 281 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); 282 const struct drm_plane_helper_funcs *plane_funcs; 283 struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc); 284 struct armada_plane_work *work; 285 int ret; 286 287 plane_funcs = plane->helper_private; 288 ret = plane_funcs->atomic_check(plane, state); 289 if (ret) 290 goto put_state; 291 292 work = &dplane->works[dplane->next_work]; 293 294 if (plane->state->fb != state->fb) { 295 /* 296 * Take a reference on the new framebuffer - we want to 297 * hold on to it while the hardware is displaying it. 298 */ 299 drm_framebuffer_reference(state->fb); 300 301 work->old_fb = plane->state->fb; 302 } else { 303 work->old_fb = NULL; 304 } 305 306 /* Point of no return */ 307 swap(plane->state, state); 308 309 /* No CRTC, can't update */ 310 if (!plane->state->crtc) 311 goto put_state; 312 313 dcrtc->regs_idx = 0; 314 dcrtc->regs = work->regs; 315 316 plane_funcs->atomic_update(plane, state); 317 318 /* If nothing was updated, short-circuit */ 319 if (dcrtc->regs_idx == 0) 320 goto put_state; 321 322 armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx); 323 324 /* Wait for pending work to complete */ 325 if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) 326 armada_drm_plane_work_cancel(dcrtc, &dplane->base); 327 328 /* Just updating the position/size? */ 329 if (!dplane->wait_vblank) { 330 armada_ovl_plane_work(dcrtc, work); 331 goto put_state; 332 } 333 334 dcrtc->plane = plane; 335 336 /* Queue it for update on the next interrupt if we are enabled */ 337 ret = armada_drm_plane_work_queue(dcrtc, work); 338 if (ret) { 339 DRM_ERROR("failed to queue plane work: %d\n", ret); 340 ret = 0; 341 } 342 343 dplane->next_work = !dplane->next_work; 344 345 put_state: 346 plane->funcs->atomic_destroy_state(plane, state); 347 return ret; 348 } 349 350 static int 351 armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, 352 struct drm_framebuffer *fb, 353 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, 354 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, 355 struct drm_modeset_acquire_ctx *ctx) 356 { 357 struct drm_plane_state *state; 358 359 trace_armada_ovl_plane_update(plane, crtc, fb, 360 crtc_x, crtc_y, crtc_w, crtc_h, 361 src_x, src_y, src_w, src_h); 362 363 /* Construct new state for the overlay plane */ 364 state = plane->funcs->atomic_duplicate_state(plane); 365 if (!state) 366 return -ENOMEM; 367 368 state->crtc = crtc; 369 drm_atomic_set_fb_for_plane(state, fb); 370 state->crtc_x = crtc_x; 371 state->crtc_y = crtc_y; 372 state->crtc_h = crtc_h; 373 state->crtc_w = crtc_w; 374 state->src_x = src_x; 375 state->src_y = src_y; 376 state->src_h = src_h; 377 state->src_w = src_w; 378 379 return armada_overlay_commit(plane, state); 380 } 381 382 static void armada_ovl_plane_destroy(struct drm_plane *plane) 383 { 384 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); 385 386 drm_plane_cleanup(plane); 387 388 kfree(dplane); 389 } 390 391 static int armada_ovl_plane_set_property(struct drm_plane *plane, 392 struct drm_property *property, uint64_t val) 393 { 394 struct drm_plane_state *state; 395 int ret; 396 397 state = plane->funcs->atomic_duplicate_state(plane); 398 if (!state) 399 return -ENOMEM; 400 401 ret = plane->funcs->atomic_set_property(plane, state, property, val); 402 if (ret) { 403 plane->funcs->atomic_destroy_state(plane, state); 404 return ret; 405 } 406 407 return armada_overlay_commit(plane, state); 408 } 409 410 static void armada_overlay_reset(struct drm_plane *plane) 411 { 412 struct armada_overlay_state *state; 413 414 if (plane->state) 415 __drm_atomic_helper_plane_destroy_state(plane->state); 416 kfree(plane->state); 417 418 state = kzalloc(sizeof(*state), GFP_KERNEL); 419 if (state) { 420 state->base.plane = plane; 421 state->base.color_encoding = DEFAULT_ENCODING; 422 state->base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; 423 state->base.rotation = DRM_MODE_ROTATE_0; 424 state->colorkey_yr = 0xfefefe00; 425 state->colorkey_ug = 0x01010100; 426 state->colorkey_vb = 0x01010100; 427 state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) | 428 CFG_ALPHAM_GRA | CFG_ALPHA(0); 429 state->colorkey_enable = ADV_GRACOLORKEY; 430 state->brightness = DEFAULT_BRIGHTNESS; 431 state->contrast = DEFAULT_CONTRAST; 432 state->saturation = DEFAULT_SATURATION; 433 } 434 plane->state = &state->base; 435 } 436 437 struct drm_plane_state * 438 armada_overlay_duplicate_state(struct drm_plane *plane) 439 { 440 struct armada_overlay_state *state; 441 442 if (WARN_ON(!plane->state)) 443 return NULL; 444 445 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL); 446 if (state) 447 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 448 return &state->base; 449 } 450 451 static int armada_overlay_set_property(struct drm_plane *plane, 452 struct drm_plane_state *state, struct drm_property *property, 453 uint64_t val) 454 { 455 struct armada_private *priv = plane->dev->dev_private; 456 457 #define K2R(val) (((val) >> 0) & 0xff) 458 #define K2G(val) (((val) >> 8) & 0xff) 459 #define K2B(val) (((val) >> 16) & 0xff) 460 if (property == priv->colorkey_prop) { 461 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8) 462 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val)); 463 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val)); 464 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val)); 465 #undef CCC 466 } else if (property == priv->colorkey_min_prop) { 467 drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000; 468 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16; 469 drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000; 470 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16; 471 drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000; 472 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16; 473 } else if (property == priv->colorkey_max_prop) { 474 drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000; 475 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24; 476 drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000; 477 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24; 478 drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000; 479 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24; 480 } else if (property == priv->colorkey_val_prop) { 481 drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00; 482 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8; 483 drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00; 484 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8; 485 drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00; 486 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8; 487 } else if (property == priv->colorkey_alpha_prop) { 488 drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff; 489 drm_to_overlay_state(state)->colorkey_yr |= K2R(val); 490 drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff; 491 drm_to_overlay_state(state)->colorkey_ug |= K2G(val); 492 drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff; 493 drm_to_overlay_state(state)->colorkey_vb |= K2B(val); 494 } else if (property == priv->colorkey_mode_prop) { 495 if (val == CKMODE_DISABLE) { 496 drm_to_overlay_state(state)->colorkey_mode = 497 CFG_CKMODE(CKMODE_DISABLE) | 498 CFG_ALPHAM_CFG | CFG_ALPHA(255); 499 drm_to_overlay_state(state)->colorkey_enable = 0; 500 } else { 501 drm_to_overlay_state(state)->colorkey_mode = 502 CFG_CKMODE(val) | 503 CFG_ALPHAM_GRA | CFG_ALPHA(0); 504 drm_to_overlay_state(state)->colorkey_enable = 505 ADV_GRACOLORKEY; 506 } 507 } else if (property == priv->brightness_prop) { 508 drm_to_overlay_state(state)->brightness = val - 256; 509 } else if (property == priv->contrast_prop) { 510 drm_to_overlay_state(state)->contrast = val; 511 } else if (property == priv->saturation_prop) { 512 drm_to_overlay_state(state)->saturation = val; 513 } else if (property == plane->color_encoding_property) { 514 /* transitional only */ 515 state->color_encoding = val; 516 } else { 517 return -EINVAL; 518 } 519 return 0; 520 } 521 522 static int armada_overlay_get_property(struct drm_plane *plane, 523 const struct drm_plane_state *state, struct drm_property *property, 524 uint64_t *val) 525 { 526 struct armada_private *priv = plane->dev->dev_private; 527 528 #define C2K(c,s) (((c) >> (s)) & 0xff) 529 #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16) 530 if (property == priv->colorkey_prop) { 531 /* Do best-efforts here for this property */ 532 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 533 drm_to_overlay_state(state)->colorkey_ug, 534 drm_to_overlay_state(state)->colorkey_vb, 16); 535 /* If min != max, or min != val, error out */ 536 if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 537 drm_to_overlay_state(state)->colorkey_ug, 538 drm_to_overlay_state(state)->colorkey_vb, 24) || 539 *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 540 drm_to_overlay_state(state)->colorkey_ug, 541 drm_to_overlay_state(state)->colorkey_vb, 8)) 542 return -EINVAL; 543 } else if (property == priv->colorkey_min_prop) { 544 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 545 drm_to_overlay_state(state)->colorkey_ug, 546 drm_to_overlay_state(state)->colorkey_vb, 16); 547 } else if (property == priv->colorkey_max_prop) { 548 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 549 drm_to_overlay_state(state)->colorkey_ug, 550 drm_to_overlay_state(state)->colorkey_vb, 24); 551 } else if (property == priv->colorkey_val_prop) { 552 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 553 drm_to_overlay_state(state)->colorkey_ug, 554 drm_to_overlay_state(state)->colorkey_vb, 8); 555 } else if (property == priv->colorkey_alpha_prop) { 556 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 557 drm_to_overlay_state(state)->colorkey_ug, 558 drm_to_overlay_state(state)->colorkey_vb, 0); 559 } else if (property == priv->colorkey_mode_prop) { 560 *val = (drm_to_overlay_state(state)->colorkey_mode & 561 CFG_CKMODE_MASK) >> ffs(CFG_CKMODE_MASK); 562 } else if (property == priv->brightness_prop) { 563 *val = drm_to_overlay_state(state)->brightness + 256; 564 } else if (property == priv->contrast_prop) { 565 *val = drm_to_overlay_state(state)->contrast; 566 } else if (property == priv->saturation_prop) { 567 *val = drm_to_overlay_state(state)->saturation; 568 } else { 569 return -EINVAL; 570 } 571 return 0; 572 } 573 574 static const struct drm_plane_funcs armada_ovl_plane_funcs = { 575 .update_plane = armada_ovl_plane_update, 576 .disable_plane = drm_plane_helper_disable, 577 .destroy = armada_ovl_plane_destroy, 578 .set_property = armada_ovl_plane_set_property, 579 .reset = armada_overlay_reset, 580 .atomic_duplicate_state = armada_overlay_duplicate_state, 581 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 582 .atomic_set_property = armada_overlay_set_property, 583 .atomic_get_property = armada_overlay_get_property, 584 }; 585 586 static const uint32_t armada_ovl_formats[] = { 587 DRM_FORMAT_UYVY, 588 DRM_FORMAT_YUYV, 589 DRM_FORMAT_YUV420, 590 DRM_FORMAT_YVU420, 591 DRM_FORMAT_YUV422, 592 DRM_FORMAT_YVU422, 593 DRM_FORMAT_VYUY, 594 DRM_FORMAT_YVYU, 595 DRM_FORMAT_ARGB8888, 596 DRM_FORMAT_ABGR8888, 597 DRM_FORMAT_XRGB8888, 598 DRM_FORMAT_XBGR8888, 599 DRM_FORMAT_RGB888, 600 DRM_FORMAT_BGR888, 601 DRM_FORMAT_ARGB1555, 602 DRM_FORMAT_ABGR1555, 603 DRM_FORMAT_RGB565, 604 DRM_FORMAT_BGR565, 605 }; 606 607 static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = { 608 { CKMODE_DISABLE, "disabled" }, 609 { CKMODE_Y, "Y component" }, 610 { CKMODE_U, "U component" }, 611 { CKMODE_V, "V component" }, 612 { CKMODE_RGB, "RGB" }, 613 { CKMODE_R, "R component" }, 614 { CKMODE_G, "G component" }, 615 { CKMODE_B, "B component" }, 616 }; 617 618 static int armada_overlay_create_properties(struct drm_device *dev) 619 { 620 struct armada_private *priv = dev->dev_private; 621 622 if (priv->colorkey_prop) 623 return 0; 624 625 priv->colorkey_prop = drm_property_create_range(dev, 0, 626 "colorkey", 0, 0xffffff); 627 priv->colorkey_min_prop = drm_property_create_range(dev, 0, 628 "colorkey_min", 0, 0xffffff); 629 priv->colorkey_max_prop = drm_property_create_range(dev, 0, 630 "colorkey_max", 0, 0xffffff); 631 priv->colorkey_val_prop = drm_property_create_range(dev, 0, 632 "colorkey_val", 0, 0xffffff); 633 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0, 634 "colorkey_alpha", 0, 0xffffff); 635 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0, 636 "colorkey_mode", 637 armada_drm_colorkey_enum_list, 638 ARRAY_SIZE(armada_drm_colorkey_enum_list)); 639 priv->brightness_prop = drm_property_create_range(dev, 0, 640 "brightness", 0, 256 + 255); 641 priv->contrast_prop = drm_property_create_range(dev, 0, 642 "contrast", 0, 0x7fff); 643 priv->saturation_prop = drm_property_create_range(dev, 0, 644 "saturation", 0, 0x7fff); 645 646 if (!priv->colorkey_prop) 647 return -ENOMEM; 648 649 return 0; 650 } 651 652 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) 653 { 654 struct armada_private *priv = dev->dev_private; 655 struct drm_mode_object *mobj; 656 struct armada_ovl_plane *dplane; 657 int ret; 658 659 ret = armada_overlay_create_properties(dev); 660 if (ret) 661 return ret; 662 663 dplane = kzalloc(sizeof(*dplane), GFP_KERNEL); 664 if (!dplane) 665 return -ENOMEM; 666 667 ret = armada_drm_plane_init(&dplane->base); 668 if (ret) { 669 kfree(dplane); 670 return ret; 671 } 672 673 dplane->works[0].plane = &dplane->base.base; 674 dplane->works[0].fn = armada_ovl_plane_work; 675 dplane->works[1].plane = &dplane->base.base; 676 dplane->works[1].fn = armada_ovl_plane_work; 677 678 drm_plane_helper_add(&dplane->base.base, 679 &armada_overlay_plane_helper_funcs); 680 681 ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs, 682 &armada_ovl_plane_funcs, 683 armada_ovl_formats, 684 ARRAY_SIZE(armada_ovl_formats), 685 NULL, 686 DRM_PLANE_TYPE_OVERLAY, NULL); 687 if (ret) { 688 kfree(dplane); 689 return ret; 690 } 691 692 mobj = &dplane->base.base.base; 693 drm_object_attach_property(mobj, priv->colorkey_prop, 694 0x0101fe); 695 drm_object_attach_property(mobj, priv->colorkey_min_prop, 696 0x0101fe); 697 drm_object_attach_property(mobj, priv->colorkey_max_prop, 698 0x0101fe); 699 drm_object_attach_property(mobj, priv->colorkey_val_prop, 700 0x0101fe); 701 drm_object_attach_property(mobj, priv->colorkey_alpha_prop, 702 0x000000); 703 drm_object_attach_property(mobj, priv->colorkey_mode_prop, 704 CKMODE_RGB); 705 drm_object_attach_property(mobj, priv->brightness_prop, 706 256 + DEFAULT_BRIGHTNESS); 707 drm_object_attach_property(mobj, priv->contrast_prop, 708 DEFAULT_CONTRAST); 709 drm_object_attach_property(mobj, priv->saturation_prop, 710 DEFAULT_SATURATION); 711 712 ret = drm_plane_create_color_properties(&dplane->base.base, 713 BIT(DRM_COLOR_YCBCR_BT601) | 714 BIT(DRM_COLOR_YCBCR_BT709), 715 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), 716 DEFAULT_ENCODING, 717 DRM_COLOR_YCBCR_LIMITED_RANGE); 718 719 return ret; 720 } 721