1 /* 2 * Copyright (C) 2012 Russell King 3 * Rewritten from the dovefb driver, and Armada510 manuals. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 #include <drm/drmP.h> 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_atomic_uapi.h> 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_plane_helper.h> 14 #include <drm/armada_drm.h> 15 #include "armada_crtc.h" 16 #include "armada_drm.h" 17 #include "armada_fb.h" 18 #include "armada_gem.h" 19 #include "armada_hw.h" 20 #include "armada_ioctlP.h" 21 #include "armada_plane.h" 22 #include "armada_trace.h" 23 24 #define DEFAULT_BRIGHTNESS 0 25 #define DEFAULT_CONTRAST 0x4000 26 #define DEFAULT_SATURATION 0x4000 27 #define DEFAULT_ENCODING DRM_COLOR_YCBCR_BT601 28 29 struct armada_overlay_state { 30 struct armada_plane_state base; 31 u32 colorkey_yr; 32 u32 colorkey_ug; 33 u32 colorkey_vb; 34 u32 colorkey_mode; 35 u32 colorkey_enable; 36 s16 brightness; 37 u16 contrast; 38 u16 saturation; 39 }; 40 #define drm_to_overlay_state(s) \ 41 container_of(s, struct armada_overlay_state, base.base) 42 43 static inline u32 armada_spu_contrast(struct drm_plane_state *state) 44 { 45 return drm_to_overlay_state(state)->brightness << 16 | 46 drm_to_overlay_state(state)->contrast; 47 } 48 49 static inline u32 armada_spu_saturation(struct drm_plane_state *state) 50 { 51 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */ 52 return drm_to_overlay_state(state)->saturation << 16; 53 } 54 55 static inline u32 armada_csc(struct drm_plane_state *state) 56 { 57 /* 58 * The CFG_CSC_RGB_* settings control the output of the colour space 59 * converter, setting the range of output values it produces. Since 60 * we will be blending with the full-range graphics, we need to 61 * produce full-range RGB output from the conversion. 62 */ 63 return CFG_CSC_RGB_COMPUTER | 64 (state->color_encoding == DRM_COLOR_YCBCR_BT709 ? 65 CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601); 66 } 67 68 /* === Plane support === */ 69 static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, 70 struct drm_plane_state *old_state) 71 { 72 struct drm_plane_state *state = plane->state; 73 struct armada_crtc *dcrtc; 74 struct armada_regs *regs; 75 unsigned int idx; 76 u32 cfg, cfg_mask, val; 77 78 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 79 80 if (!state->fb || WARN_ON(!state->crtc)) 81 return; 82 83 DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n", 84 plane->base.id, plane->name, 85 state->crtc->base.id, state->crtc->name, 86 state->fb->base.id, 87 old_state->visible, state->visible); 88 89 dcrtc = drm_to_armada_crtc(state->crtc); 90 regs = dcrtc->regs + dcrtc->regs_idx; 91 92 idx = 0; 93 if (!old_state->visible && state->visible) 94 armada_reg_queue_mod(regs, idx, 95 0, CFG_PDWN16x66 | CFG_PDWN32x66, 96 LCD_SPU_SRAM_PARA1); 97 val = armada_src_hw(state); 98 if (armada_src_hw(old_state) != val) 99 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); 100 val = armada_dst_yx(state); 101 if (armada_dst_yx(old_state) != val) 102 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); 103 val = armada_dst_hw(state); 104 if (armada_dst_hw(old_state) != val) 105 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); 106 /* FIXME: overlay on an interlaced display */ 107 if (old_state->src.x1 != state->src.x1 || 108 old_state->src.y1 != state->src.y1 || 109 old_state->fb != state->fb || 110 state->crtc->state->mode_changed) { 111 const struct drm_format_info *format; 112 u16 src_x; 113 114 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0), 115 LCD_SPU_DMA_START_ADDR_Y0); 116 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1), 117 LCD_SPU_DMA_START_ADDR_U0); 118 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2), 119 LCD_SPU_DMA_START_ADDR_V0); 120 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0), 121 LCD_SPU_DMA_START_ADDR_Y1); 122 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1), 123 LCD_SPU_DMA_START_ADDR_U1); 124 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2), 125 LCD_SPU_DMA_START_ADDR_V1); 126 127 val = armada_pitch(state, 0) << 16 | armada_pitch(state, 0); 128 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); 129 val = armada_pitch(state, 1) << 16 | armada_pitch(state, 2); 130 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); 131 132 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) | 133 CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) | 134 CFG_CBSH_ENA; 135 if (state->visible) 136 cfg |= CFG_DMA_ENA; 137 138 /* 139 * Shifting a YUV packed format image by one pixel causes the 140 * U/V planes to swap. Compensate for it by also toggling 141 * the UV swap. 142 */ 143 format = state->fb->format; 144 src_x = state->src.x1 >> 16; 145 if (format->num_planes == 1 && src_x & (format->hsub - 1)) 146 cfg ^= CFG_DMA_MOD(CFG_SWAPUV); 147 if (to_armada_plane_state(state)->interlace) 148 cfg |= CFG_DMA_FTOGGLE; 149 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT | 150 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | 151 CFG_SWAPYU | CFG_YUV2RGB) | 152 CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE | 153 CFG_DMA_ENA; 154 } else if (old_state->visible != state->visible) { 155 cfg = state->visible ? CFG_DMA_ENA : 0; 156 cfg_mask = CFG_DMA_ENA; 157 } else { 158 cfg = cfg_mask = 0; 159 } 160 if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) || 161 drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) { 162 cfg_mask |= CFG_DMA_HSMOOTH; 163 if (drm_rect_width(&state->src) >> 16 != 164 drm_rect_width(&state->dst)) 165 cfg |= CFG_DMA_HSMOOTH; 166 } 167 168 if (cfg_mask) 169 armada_reg_queue_mod(regs, idx, cfg, cfg_mask, 170 LCD_SPU_DMA_CTRL0); 171 172 val = armada_spu_contrast(state); 173 if ((!old_state->visible && state->visible) || 174 armada_spu_contrast(old_state) != val) 175 armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST); 176 val = armada_spu_saturation(state); 177 if ((!old_state->visible && state->visible) || 178 armada_spu_saturation(old_state) != val) 179 armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION); 180 if (!old_state->visible && state->visible) 181 armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE); 182 val = armada_csc(state); 183 if ((!old_state->visible && state->visible) || 184 armada_csc(old_state) != val) 185 armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK, 186 LCD_SPU_IOPAD_CONTROL); 187 val = drm_to_overlay_state(state)->colorkey_yr; 188 if ((!old_state->visible && state->visible) || 189 drm_to_overlay_state(old_state)->colorkey_yr != val) 190 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y); 191 val = drm_to_overlay_state(state)->colorkey_ug; 192 if ((!old_state->visible && state->visible) || 193 drm_to_overlay_state(old_state)->colorkey_ug != val) 194 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U); 195 val = drm_to_overlay_state(state)->colorkey_vb; 196 if ((!old_state->visible && state->visible) || 197 drm_to_overlay_state(old_state)->colorkey_vb != val) 198 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V); 199 val = drm_to_overlay_state(state)->colorkey_mode; 200 if ((!old_state->visible && state->visible) || 201 drm_to_overlay_state(old_state)->colorkey_mode != val) 202 armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK | 203 CFG_ALPHAM_MASK | CFG_ALPHA_MASK, 204 LCD_SPU_DMA_CTRL1); 205 val = drm_to_overlay_state(state)->colorkey_enable; 206 if (((!old_state->visible && state->visible) || 207 drm_to_overlay_state(old_state)->colorkey_enable != val) && 208 dcrtc->variant->has_spu_adv_reg) 209 armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY | 210 ADV_VIDCOLORKEY, LCD_SPU_ADV_REG); 211 212 dcrtc->regs_idx += idx; 213 } 214 215 static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane, 216 struct drm_plane_state *old_state) 217 { 218 struct armada_crtc *dcrtc; 219 struct armada_regs *regs; 220 unsigned int idx = 0; 221 222 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 223 224 if (!old_state->crtc) 225 return; 226 227 DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n", 228 plane->base.id, plane->name, 229 old_state->crtc->base.id, old_state->crtc->name, 230 old_state->fb->base.id); 231 232 dcrtc = drm_to_armada_crtc(old_state->crtc); 233 regs = dcrtc->regs + dcrtc->regs_idx; 234 235 /* Disable plane and power down the YUV FIFOs */ 236 armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0); 237 armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0, 238 LCD_SPU_SRAM_PARA1); 239 240 dcrtc->regs_idx += idx; 241 } 242 243 static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = { 244 .prepare_fb = armada_drm_plane_prepare_fb, 245 .cleanup_fb = armada_drm_plane_cleanup_fb, 246 .atomic_check = armada_drm_plane_atomic_check, 247 .atomic_update = armada_drm_overlay_plane_atomic_update, 248 .atomic_disable = armada_drm_overlay_plane_atomic_disable, 249 }; 250 251 static int 252 armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, 253 struct drm_framebuffer *fb, 254 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, 255 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, 256 struct drm_modeset_acquire_ctx *ctx) 257 { 258 struct drm_atomic_state *state; 259 struct drm_plane_state *plane_state; 260 int ret = 0; 261 262 trace_armada_ovl_plane_update(plane, crtc, fb, 263 crtc_x, crtc_y, crtc_w, crtc_h, 264 src_x, src_y, src_w, src_h); 265 266 state = drm_atomic_state_alloc(plane->dev); 267 if (!state) 268 return -ENOMEM; 269 270 state->acquire_ctx = ctx; 271 plane_state = drm_atomic_get_plane_state(state, plane); 272 if (IS_ERR(plane_state)) { 273 ret = PTR_ERR(plane_state); 274 goto fail; 275 } 276 277 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); 278 if (ret != 0) 279 goto fail; 280 281 drm_atomic_set_fb_for_plane(plane_state, fb); 282 plane_state->crtc_x = crtc_x; 283 plane_state->crtc_y = crtc_y; 284 plane_state->crtc_h = crtc_h; 285 plane_state->crtc_w = crtc_w; 286 plane_state->src_x = src_x; 287 plane_state->src_y = src_y; 288 plane_state->src_h = src_h; 289 plane_state->src_w = src_w; 290 291 ret = drm_atomic_nonblocking_commit(state); 292 fail: 293 drm_atomic_state_put(state); 294 return ret; 295 } 296 297 static void armada_ovl_plane_destroy(struct drm_plane *plane) 298 { 299 drm_plane_cleanup(plane); 300 kfree(plane); 301 } 302 303 static void armada_overlay_reset(struct drm_plane *plane) 304 { 305 struct armada_overlay_state *state; 306 307 if (plane->state) 308 __drm_atomic_helper_plane_destroy_state(plane->state); 309 kfree(plane->state); 310 plane->state = NULL; 311 312 state = kzalloc(sizeof(*state), GFP_KERNEL); 313 if (state) { 314 state->colorkey_yr = 0xfefefe00; 315 state->colorkey_ug = 0x01010100; 316 state->colorkey_vb = 0x01010100; 317 state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) | 318 CFG_ALPHAM_GRA | CFG_ALPHA(0); 319 state->colorkey_enable = ADV_GRACOLORKEY; 320 state->brightness = DEFAULT_BRIGHTNESS; 321 state->contrast = DEFAULT_CONTRAST; 322 state->saturation = DEFAULT_SATURATION; 323 __drm_atomic_helper_plane_reset(plane, &state->base.base); 324 state->base.base.color_encoding = DEFAULT_ENCODING; 325 state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; 326 } 327 } 328 329 struct drm_plane_state * 330 armada_overlay_duplicate_state(struct drm_plane *plane) 331 { 332 struct armada_overlay_state *state; 333 334 if (WARN_ON(!plane->state)) 335 return NULL; 336 337 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL); 338 if (state) 339 __drm_atomic_helper_plane_duplicate_state(plane, 340 &state->base.base); 341 return &state->base.base; 342 } 343 344 static int armada_overlay_set_property(struct drm_plane *plane, 345 struct drm_plane_state *state, struct drm_property *property, 346 uint64_t val) 347 { 348 struct armada_private *priv = plane->dev->dev_private; 349 350 #define K2R(val) (((val) >> 0) & 0xff) 351 #define K2G(val) (((val) >> 8) & 0xff) 352 #define K2B(val) (((val) >> 16) & 0xff) 353 if (property == priv->colorkey_prop) { 354 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8) 355 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val)); 356 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val)); 357 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val)); 358 #undef CCC 359 } else if (property == priv->colorkey_min_prop) { 360 drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000; 361 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16; 362 drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000; 363 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16; 364 drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000; 365 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16; 366 } else if (property == priv->colorkey_max_prop) { 367 drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000; 368 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24; 369 drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000; 370 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24; 371 drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000; 372 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24; 373 } else if (property == priv->colorkey_val_prop) { 374 drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00; 375 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8; 376 drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00; 377 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8; 378 drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00; 379 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8; 380 } else if (property == priv->colorkey_alpha_prop) { 381 drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff; 382 drm_to_overlay_state(state)->colorkey_yr |= K2R(val); 383 drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff; 384 drm_to_overlay_state(state)->colorkey_ug |= K2G(val); 385 drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff; 386 drm_to_overlay_state(state)->colorkey_vb |= K2B(val); 387 } else if (property == priv->colorkey_mode_prop) { 388 if (val == CKMODE_DISABLE) { 389 drm_to_overlay_state(state)->colorkey_mode = 390 CFG_CKMODE(CKMODE_DISABLE) | 391 CFG_ALPHAM_CFG | CFG_ALPHA(255); 392 drm_to_overlay_state(state)->colorkey_enable = 0; 393 } else { 394 drm_to_overlay_state(state)->colorkey_mode = 395 CFG_CKMODE(val) | 396 CFG_ALPHAM_GRA | CFG_ALPHA(0); 397 drm_to_overlay_state(state)->colorkey_enable = 398 ADV_GRACOLORKEY; 399 } 400 } else if (property == priv->brightness_prop) { 401 drm_to_overlay_state(state)->brightness = val - 256; 402 } else if (property == priv->contrast_prop) { 403 drm_to_overlay_state(state)->contrast = val; 404 } else if (property == priv->saturation_prop) { 405 drm_to_overlay_state(state)->saturation = val; 406 } else { 407 return -EINVAL; 408 } 409 return 0; 410 } 411 412 static int armada_overlay_get_property(struct drm_plane *plane, 413 const struct drm_plane_state *state, struct drm_property *property, 414 uint64_t *val) 415 { 416 struct armada_private *priv = plane->dev->dev_private; 417 418 #define C2K(c,s) (((c) >> (s)) & 0xff) 419 #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16) 420 if (property == priv->colorkey_prop) { 421 /* Do best-efforts here for this property */ 422 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 423 drm_to_overlay_state(state)->colorkey_ug, 424 drm_to_overlay_state(state)->colorkey_vb, 16); 425 /* If min != max, or min != val, error out */ 426 if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 427 drm_to_overlay_state(state)->colorkey_ug, 428 drm_to_overlay_state(state)->colorkey_vb, 24) || 429 *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 430 drm_to_overlay_state(state)->colorkey_ug, 431 drm_to_overlay_state(state)->colorkey_vb, 8)) 432 return -EINVAL; 433 } else if (property == priv->colorkey_min_prop) { 434 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 435 drm_to_overlay_state(state)->colorkey_ug, 436 drm_to_overlay_state(state)->colorkey_vb, 16); 437 } else if (property == priv->colorkey_max_prop) { 438 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 439 drm_to_overlay_state(state)->colorkey_ug, 440 drm_to_overlay_state(state)->colorkey_vb, 24); 441 } else if (property == priv->colorkey_val_prop) { 442 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 443 drm_to_overlay_state(state)->colorkey_ug, 444 drm_to_overlay_state(state)->colorkey_vb, 8); 445 } else if (property == priv->colorkey_alpha_prop) { 446 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 447 drm_to_overlay_state(state)->colorkey_ug, 448 drm_to_overlay_state(state)->colorkey_vb, 0); 449 } else if (property == priv->colorkey_mode_prop) { 450 *val = (drm_to_overlay_state(state)->colorkey_mode & 451 CFG_CKMODE_MASK) >> ffs(CFG_CKMODE_MASK); 452 } else if (property == priv->brightness_prop) { 453 *val = drm_to_overlay_state(state)->brightness + 256; 454 } else if (property == priv->contrast_prop) { 455 *val = drm_to_overlay_state(state)->contrast; 456 } else if (property == priv->saturation_prop) { 457 *val = drm_to_overlay_state(state)->saturation; 458 } else { 459 return -EINVAL; 460 } 461 return 0; 462 } 463 464 static const struct drm_plane_funcs armada_ovl_plane_funcs = { 465 .update_plane = armada_overlay_plane_update, 466 .disable_plane = drm_atomic_helper_disable_plane, 467 .destroy = armada_ovl_plane_destroy, 468 .reset = armada_overlay_reset, 469 .atomic_duplicate_state = armada_overlay_duplicate_state, 470 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 471 .atomic_set_property = armada_overlay_set_property, 472 .atomic_get_property = armada_overlay_get_property, 473 }; 474 475 static const uint32_t armada_ovl_formats[] = { 476 DRM_FORMAT_UYVY, 477 DRM_FORMAT_YUYV, 478 DRM_FORMAT_YUV420, 479 DRM_FORMAT_YVU420, 480 DRM_FORMAT_YUV422, 481 DRM_FORMAT_YVU422, 482 DRM_FORMAT_VYUY, 483 DRM_FORMAT_YVYU, 484 DRM_FORMAT_ARGB8888, 485 DRM_FORMAT_ABGR8888, 486 DRM_FORMAT_XRGB8888, 487 DRM_FORMAT_XBGR8888, 488 DRM_FORMAT_RGB888, 489 DRM_FORMAT_BGR888, 490 DRM_FORMAT_ARGB1555, 491 DRM_FORMAT_ABGR1555, 492 DRM_FORMAT_RGB565, 493 DRM_FORMAT_BGR565, 494 }; 495 496 static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = { 497 { CKMODE_DISABLE, "disabled" }, 498 { CKMODE_Y, "Y component" }, 499 { CKMODE_U, "U component" }, 500 { CKMODE_V, "V component" }, 501 { CKMODE_RGB, "RGB" }, 502 { CKMODE_R, "R component" }, 503 { CKMODE_G, "G component" }, 504 { CKMODE_B, "B component" }, 505 }; 506 507 static int armada_overlay_create_properties(struct drm_device *dev) 508 { 509 struct armada_private *priv = dev->dev_private; 510 511 if (priv->colorkey_prop) 512 return 0; 513 514 priv->colorkey_prop = drm_property_create_range(dev, 0, 515 "colorkey", 0, 0xffffff); 516 priv->colorkey_min_prop = drm_property_create_range(dev, 0, 517 "colorkey_min", 0, 0xffffff); 518 priv->colorkey_max_prop = drm_property_create_range(dev, 0, 519 "colorkey_max", 0, 0xffffff); 520 priv->colorkey_val_prop = drm_property_create_range(dev, 0, 521 "colorkey_val", 0, 0xffffff); 522 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0, 523 "colorkey_alpha", 0, 0xffffff); 524 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0, 525 "colorkey_mode", 526 armada_drm_colorkey_enum_list, 527 ARRAY_SIZE(armada_drm_colorkey_enum_list)); 528 priv->brightness_prop = drm_property_create_range(dev, 0, 529 "brightness", 0, 256 + 255); 530 priv->contrast_prop = drm_property_create_range(dev, 0, 531 "contrast", 0, 0x7fff); 532 priv->saturation_prop = drm_property_create_range(dev, 0, 533 "saturation", 0, 0x7fff); 534 535 if (!priv->colorkey_prop) 536 return -ENOMEM; 537 538 return 0; 539 } 540 541 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) 542 { 543 struct armada_private *priv = dev->dev_private; 544 struct drm_mode_object *mobj; 545 struct drm_plane *overlay; 546 int ret; 547 548 ret = armada_overlay_create_properties(dev); 549 if (ret) 550 return ret; 551 552 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 553 if (!overlay) 554 return -ENOMEM; 555 556 drm_plane_helper_add(overlay, &armada_overlay_plane_helper_funcs); 557 558 ret = drm_universal_plane_init(dev, overlay, crtcs, 559 &armada_ovl_plane_funcs, 560 armada_ovl_formats, 561 ARRAY_SIZE(armada_ovl_formats), 562 NULL, 563 DRM_PLANE_TYPE_OVERLAY, NULL); 564 if (ret) { 565 kfree(overlay); 566 return ret; 567 } 568 569 mobj = &overlay->base; 570 drm_object_attach_property(mobj, priv->colorkey_prop, 571 0x0101fe); 572 drm_object_attach_property(mobj, priv->colorkey_min_prop, 573 0x0101fe); 574 drm_object_attach_property(mobj, priv->colorkey_max_prop, 575 0x0101fe); 576 drm_object_attach_property(mobj, priv->colorkey_val_prop, 577 0x0101fe); 578 drm_object_attach_property(mobj, priv->colorkey_alpha_prop, 579 0x000000); 580 drm_object_attach_property(mobj, priv->colorkey_mode_prop, 581 CKMODE_RGB); 582 drm_object_attach_property(mobj, priv->brightness_prop, 583 256 + DEFAULT_BRIGHTNESS); 584 drm_object_attach_property(mobj, priv->contrast_prop, 585 DEFAULT_CONTRAST); 586 drm_object_attach_property(mobj, priv->saturation_prop, 587 DEFAULT_SATURATION); 588 589 ret = drm_plane_create_color_properties(overlay, 590 BIT(DRM_COLOR_YCBCR_BT601) | 591 BIT(DRM_COLOR_YCBCR_BT709), 592 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), 593 DEFAULT_ENCODING, 594 DRM_COLOR_YCBCR_LIMITED_RANGE); 595 596 return ret; 597 } 598