196f60e37SRussell King /* 296f60e37SRussell King * Copyright (C) 2012 Russell King 396f60e37SRussell King * Rewritten from the dovefb driver, and Armada510 manuals. 496f60e37SRussell King * 596f60e37SRussell King * This program is free software; you can redistribute it and/or modify 696f60e37SRussell King * it under the terms of the GNU General Public License version 2 as 796f60e37SRussell King * published by the Free Software Foundation. 896f60e37SRussell King */ 996f60e37SRussell King #include <drm/drmP.h> 1047dc413bSRussell King #include <drm/drm_atomic.h> 1172fdb40cSDaniel Vetter #include <drm/drm_atomic_uapi.h> 12bcd21a47SDave Airlie #include <drm/drm_atomic_helper.h> 1347dc413bSRussell King #include <drm/drm_plane_helper.h> 14d40af7b1SRussell King #include <drm/armada_drm.h> 1596f60e37SRussell King #include "armada_crtc.h" 1696f60e37SRussell King #include "armada_drm.h" 1796f60e37SRussell King #include "armada_fb.h" 1896f60e37SRussell King #include "armada_gem.h" 1996f60e37SRussell King #include "armada_hw.h" 2096f60e37SRussell King #include "armada_ioctlP.h" 21d40af7b1SRussell King #include "armada_plane.h" 22c8a220c6SRussell King #include "armada_trace.h" 2396f60e37SRussell King 2461ba2527SRussell King #define DEFAULT_BRIGHTNESS 0 2561ba2527SRussell King #define DEFAULT_CONTRAST 0x4000 2661ba2527SRussell King #define DEFAULT_SATURATION 0x4000 27c29277d4SRussell King #define DEFAULT_ENCODING DRM_COLOR_YCBCR_BT601 2861ba2527SRussell King 2961ba2527SRussell King struct armada_overlay_state { 3061ba2527SRussell King struct drm_plane_state base; 31c96103b6SRussell King u32 colorkey_yr; 32c96103b6SRussell King u32 colorkey_ug; 33c96103b6SRussell King u32 colorkey_vb; 34c96103b6SRussell King u32 colorkey_mode; 35c96103b6SRussell King u32 colorkey_enable; 3661ba2527SRussell King s16 brightness; 3761ba2527SRussell King u16 contrast; 3861ba2527SRussell King u16 saturation; 3961ba2527SRussell King }; 4061ba2527SRussell King #define drm_to_overlay_state(s) \ 4161ba2527SRussell King container_of(s, struct armada_overlay_state, base) 4261ba2527SRussell King 4361ba2527SRussell King static inline u32 armada_spu_contrast(struct drm_plane_state *state) 4461ba2527SRussell King { 4561ba2527SRussell King return drm_to_overlay_state(state)->brightness << 16 | 4661ba2527SRussell King drm_to_overlay_state(state)->contrast; 4761ba2527SRussell King } 4861ba2527SRussell King 4961ba2527SRussell King static inline u32 armada_spu_saturation(struct drm_plane_state *state) 5061ba2527SRussell King { 5161ba2527SRussell King /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */ 5261ba2527SRussell King return drm_to_overlay_state(state)->saturation << 16; 5361ba2527SRussell King } 5496f60e37SRussell King 55c29277d4SRussell King static inline u32 armada_csc(struct drm_plane_state *state) 56c29277d4SRussell King { 57c29277d4SRussell King /* 58c29277d4SRussell King * The CFG_CSC_RGB_* settings control the output of the colour space 59c29277d4SRussell King * converter, setting the range of output values it produces. Since 60c29277d4SRussell King * we will be blending with the full-range graphics, we need to 61c29277d4SRussell King * produce full-range RGB output from the conversion. 62c29277d4SRussell King */ 63c29277d4SRussell King return CFG_CSC_RGB_COMPUTER | 64c29277d4SRussell King (state->color_encoding == DRM_COLOR_YCBCR_BT709 ? 65c29277d4SRussell King CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601); 66c29277d4SRussell King } 67c29277d4SRussell King 6896f60e37SRussell King /* === Plane support === */ 6947dc413bSRussell King static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, 7047dc413bSRussell King struct drm_plane_state *old_state) 7147dc413bSRussell King { 7247dc413bSRussell King struct drm_plane_state *state = plane->state; 7347dc413bSRussell King struct armada_crtc *dcrtc; 7447dc413bSRussell King struct armada_regs *regs; 753acea7b9SRussell King unsigned int idx; 763acea7b9SRussell King u32 cfg, cfg_mask, val; 7747dc413bSRussell King 7847dc413bSRussell King DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 7947dc413bSRussell King 8047dc413bSRussell King if (!state->fb || WARN_ON(!state->crtc)) 8147dc413bSRussell King return; 8247dc413bSRussell King 8347dc413bSRussell King DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n", 8447dc413bSRussell King plane->base.id, plane->name, 8547dc413bSRussell King state->crtc->base.id, state->crtc->name, 8647dc413bSRussell King state->fb->base.id, 8747dc413bSRussell King old_state->visible, state->visible); 8847dc413bSRussell King 8947dc413bSRussell King dcrtc = drm_to_armada_crtc(state->crtc); 9047dc413bSRussell King regs = dcrtc->regs + dcrtc->regs_idx; 9147dc413bSRussell King 923acea7b9SRussell King idx = 0; 933acea7b9SRussell King if (!old_state->visible && state->visible) 943acea7b9SRussell King armada_reg_queue_mod(regs, idx, 953acea7b9SRussell King 0, CFG_PDWN16x66 | CFG_PDWN32x66, 963acea7b9SRussell King LCD_SPU_SRAM_PARA1); 973acea7b9SRussell King val = armada_rect_hw_fp(&state->src); 983acea7b9SRussell King if (armada_rect_hw_fp(&old_state->src) != val) 993acea7b9SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); 1003acea7b9SRussell King val = armada_rect_yx(&state->dst); 1013acea7b9SRussell King if (armada_rect_yx(&old_state->dst) != val) 1023acea7b9SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); 1033acea7b9SRussell King val = armada_rect_hw(&state->dst); 1043acea7b9SRussell King if (armada_rect_hw(&old_state->dst) != val) 1053acea7b9SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); 1063acea7b9SRussell King /* FIXME: overlay on an interlaced display */ 1073acea7b9SRussell King if (old_state->src.x1 != state->src.x1 || 1083acea7b9SRussell King old_state->src.y1 != state->src.y1 || 1093acea7b9SRussell King old_state->fb != state->fb) { 1103acea7b9SRussell King const struct drm_format_info *format; 1114aafe00eSRussell King u16 src_x, pitches[3]; 112b5bae71aSRussell King u32 addrs[2][3]; 1133acea7b9SRussell King 114b5bae71aSRussell King armada_drm_plane_calc(state, addrs, pitches, false); 1153acea7b9SRussell King 116b5bae71aSRussell King armada_reg_queue_set(regs, idx, addrs[0][0], 1173acea7b9SRussell King LCD_SPU_DMA_START_ADDR_Y0); 118b5bae71aSRussell King armada_reg_queue_set(regs, idx, addrs[0][1], 1193acea7b9SRussell King LCD_SPU_DMA_START_ADDR_U0); 120b5bae71aSRussell King armada_reg_queue_set(regs, idx, addrs[0][2], 1213acea7b9SRussell King LCD_SPU_DMA_START_ADDR_V0); 122b5bae71aSRussell King armada_reg_queue_set(regs, idx, addrs[1][0], 1233acea7b9SRussell King LCD_SPU_DMA_START_ADDR_Y1); 124b5bae71aSRussell King armada_reg_queue_set(regs, idx, addrs[1][1], 1253acea7b9SRussell King LCD_SPU_DMA_START_ADDR_U1); 126b5bae71aSRussell King armada_reg_queue_set(regs, idx, addrs[1][2], 1273acea7b9SRussell King LCD_SPU_DMA_START_ADDR_V1); 1283acea7b9SRussell King 1294aafe00eSRussell King val = pitches[0] << 16 | pitches[0]; 1303acea7b9SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); 1314aafe00eSRussell King val = pitches[1] << 16 | pitches[2]; 1323acea7b9SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); 1333acea7b9SRussell King 1343acea7b9SRussell King cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) | 1353acea7b9SRussell King CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) | 1363acea7b9SRussell King CFG_CBSH_ENA; 1373acea7b9SRussell King if (state->visible) 1383acea7b9SRussell King cfg |= CFG_DMA_ENA; 1393acea7b9SRussell King 1403acea7b9SRussell King /* 1413acea7b9SRussell King * Shifting a YUV packed format image by one pixel causes the 1423acea7b9SRussell King * U/V planes to swap. Compensate for it by also toggling 1433acea7b9SRussell King * the UV swap. 1443acea7b9SRussell King */ 1453acea7b9SRussell King format = state->fb->format; 146b4df3ba0SRussell King src_x = state->src.x1 >> 16; 1473acea7b9SRussell King if (format->num_planes == 1 && src_x & (format->hsub - 1)) 1483acea7b9SRussell King cfg ^= CFG_DMA_MOD(CFG_SWAPUV); 1493acea7b9SRussell King cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT | 1503acea7b9SRussell King CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | 1513acea7b9SRussell King CFG_SWAPYU | CFG_YUV2RGB) | 1523acea7b9SRussell King CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE | 1533acea7b9SRussell King CFG_DMA_ENA; 1543acea7b9SRussell King } else if (old_state->visible != state->visible) { 1553acea7b9SRussell King cfg = state->visible ? CFG_DMA_ENA : 0; 1563acea7b9SRussell King cfg_mask = CFG_DMA_ENA; 1573acea7b9SRussell King } else { 1583acea7b9SRussell King cfg = cfg_mask = 0; 1593acea7b9SRussell King } 1603acea7b9SRussell King if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) || 1613acea7b9SRussell King drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) { 1623acea7b9SRussell King cfg_mask |= CFG_DMA_HSMOOTH; 1633acea7b9SRussell King if (drm_rect_width(&state->src) >> 16 != 1643acea7b9SRussell King drm_rect_width(&state->dst)) 1653acea7b9SRussell King cfg |= CFG_DMA_HSMOOTH; 1663acea7b9SRussell King } 1673acea7b9SRussell King 1683acea7b9SRussell King if (cfg_mask) 1693acea7b9SRussell King armada_reg_queue_mod(regs, idx, cfg, cfg_mask, 1703acea7b9SRussell King LCD_SPU_DMA_CTRL0); 1713acea7b9SRussell King 17261ba2527SRussell King val = armada_spu_contrast(state); 17361ba2527SRussell King if ((!old_state->visible && state->visible) || 17461ba2527SRussell King armada_spu_contrast(old_state) != val) 17561ba2527SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST); 17661ba2527SRussell King val = armada_spu_saturation(state); 17761ba2527SRussell King if ((!old_state->visible && state->visible) || 17861ba2527SRussell King armada_spu_saturation(old_state) != val) 17961ba2527SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION); 18061ba2527SRussell King if (!old_state->visible && state->visible) 18161ba2527SRussell King armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE); 182c29277d4SRussell King val = armada_csc(state); 183c29277d4SRussell King if ((!old_state->visible && state->visible) || 184c29277d4SRussell King armada_csc(old_state) != val) 185c29277d4SRussell King armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK, 186c29277d4SRussell King LCD_SPU_IOPAD_CONTROL); 187c96103b6SRussell King val = drm_to_overlay_state(state)->colorkey_yr; 188c96103b6SRussell King if ((!old_state->visible && state->visible) || 189c96103b6SRussell King drm_to_overlay_state(old_state)->colorkey_yr != val) 190c96103b6SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y); 191c96103b6SRussell King val = drm_to_overlay_state(state)->colorkey_ug; 192c96103b6SRussell King if ((!old_state->visible && state->visible) || 193c96103b6SRussell King drm_to_overlay_state(old_state)->colorkey_ug != val) 194c96103b6SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U); 195c96103b6SRussell King val = drm_to_overlay_state(state)->colorkey_vb; 196c96103b6SRussell King if ((!old_state->visible && state->visible) || 197c96103b6SRussell King drm_to_overlay_state(old_state)->colorkey_vb != val) 198c96103b6SRussell King armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V); 199c96103b6SRussell King val = drm_to_overlay_state(state)->colorkey_mode; 200c96103b6SRussell King if ((!old_state->visible && state->visible) || 201c96103b6SRussell King drm_to_overlay_state(old_state)->colorkey_mode != val) 202c96103b6SRussell King armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK | 203c96103b6SRussell King CFG_ALPHAM_MASK | CFG_ALPHA_MASK, 204c96103b6SRussell King LCD_SPU_DMA_CTRL1); 205c96103b6SRussell King val = drm_to_overlay_state(state)->colorkey_enable; 206c96103b6SRussell King if (((!old_state->visible && state->visible) || 207c96103b6SRussell King drm_to_overlay_state(old_state)->colorkey_enable != val) && 208c96103b6SRussell King dcrtc->variant->has_spu_adv_reg) 209c96103b6SRussell King armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY | 210c96103b6SRussell King ADV_VIDCOLORKEY, LCD_SPU_ADV_REG); 21161ba2527SRussell King 2123acea7b9SRussell King dcrtc->regs_idx += idx; 21347dc413bSRussell King } 21447dc413bSRussell King 21547dc413bSRussell King static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane, 21647dc413bSRussell King struct drm_plane_state *old_state) 21747dc413bSRussell King { 21847dc413bSRussell King struct armada_crtc *dcrtc; 21947dc413bSRussell King struct armada_regs *regs; 22047dc413bSRussell King unsigned int idx = 0; 22147dc413bSRussell King 22247dc413bSRussell King DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); 22347dc413bSRussell King 22447dc413bSRussell King if (!old_state->crtc) 22547dc413bSRussell King return; 22647dc413bSRussell King 22747dc413bSRussell King DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n", 22847dc413bSRussell King plane->base.id, plane->name, 22947dc413bSRussell King old_state->crtc->base.id, old_state->crtc->name, 23047dc413bSRussell King old_state->fb->base.id); 23147dc413bSRussell King 23247dc413bSRussell King dcrtc = drm_to_armada_crtc(old_state->crtc); 23347dc413bSRussell King regs = dcrtc->regs + dcrtc->regs_idx; 23447dc413bSRussell King 23547dc413bSRussell King /* Disable plane and power down the YUV FIFOs */ 23647dc413bSRussell King armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0); 23747dc413bSRussell King armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0, 23847dc413bSRussell King LCD_SPU_SRAM_PARA1); 23947dc413bSRussell King 24047dc413bSRussell King dcrtc->regs_idx += idx; 24147dc413bSRussell King } 24247dc413bSRussell King 24347dc413bSRussell King static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = { 24447dc413bSRussell King .prepare_fb = armada_drm_plane_prepare_fb, 24547dc413bSRussell King .cleanup_fb = armada_drm_plane_cleanup_fb, 24647dc413bSRussell King .atomic_check = armada_drm_plane_atomic_check, 24747dc413bSRussell King .atomic_update = armada_drm_overlay_plane_atomic_update, 24847dc413bSRussell King .atomic_disable = armada_drm_overlay_plane_atomic_disable, 24947dc413bSRussell King }; 25047dc413bSRussell King 25147dc413bSRussell King static int 252b1ec9ed6SRussell King armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, 25347dc413bSRussell King struct drm_framebuffer *fb, 25447dc413bSRussell King int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, 25547dc413bSRussell King uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, 25647dc413bSRussell King struct drm_modeset_acquire_ctx *ctx) 25747dc413bSRussell King { 258b1ec9ed6SRussell King struct drm_atomic_state *state; 259b1ec9ed6SRussell King struct drm_plane_state *plane_state; 260b1ec9ed6SRussell King int ret = 0; 26147dc413bSRussell King 26247dc413bSRussell King trace_armada_ovl_plane_update(plane, crtc, fb, 26347dc413bSRussell King crtc_x, crtc_y, crtc_w, crtc_h, 26447dc413bSRussell King src_x, src_y, src_w, src_h); 26547dc413bSRussell King 266b1ec9ed6SRussell King state = drm_atomic_state_alloc(plane->dev); 26747dc413bSRussell King if (!state) 26847dc413bSRussell King return -ENOMEM; 26947dc413bSRussell King 270b1ec9ed6SRussell King state->acquire_ctx = ctx; 271b1ec9ed6SRussell King plane_state = drm_atomic_get_plane_state(state, plane); 272b1ec9ed6SRussell King if (IS_ERR(plane_state)) { 273b1ec9ed6SRussell King ret = PTR_ERR(plane_state); 274b1ec9ed6SRussell King goto fail; 275b1ec9ed6SRussell King } 27647dc413bSRussell King 277b1ec9ed6SRussell King ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); 278b1ec9ed6SRussell King if (ret != 0) 279b1ec9ed6SRussell King goto fail; 280b1ec9ed6SRussell King 281b1ec9ed6SRussell King drm_atomic_set_fb_for_plane(plane_state, fb); 282b1ec9ed6SRussell King plane_state->crtc_x = crtc_x; 283b1ec9ed6SRussell King plane_state->crtc_y = crtc_y; 284b1ec9ed6SRussell King plane_state->crtc_h = crtc_h; 285b1ec9ed6SRussell King plane_state->crtc_w = crtc_w; 286b1ec9ed6SRussell King plane_state->src_x = src_x; 287b1ec9ed6SRussell King plane_state->src_y = src_y; 288b1ec9ed6SRussell King plane_state->src_h = src_h; 289b1ec9ed6SRussell King plane_state->src_w = src_w; 290b1ec9ed6SRussell King 291b1ec9ed6SRussell King ret = drm_atomic_nonblocking_commit(state); 292b1ec9ed6SRussell King fail: 293b1ec9ed6SRussell King drm_atomic_state_put(state); 294b1ec9ed6SRussell King return ret; 29596f60e37SRussell King } 29696f60e37SRussell King 29728a2aebeSRussell King static void armada_ovl_plane_destroy(struct drm_plane *plane) 29896f60e37SRussell King { 29941dbb2dbSRussell King drm_plane_cleanup(plane); 300d701278aSRussell King kfree(plane); 30196f60e37SRussell King } 30296f60e37SRussell King 30361ba2527SRussell King static void armada_overlay_reset(struct drm_plane *plane) 30461ba2527SRussell King { 30561ba2527SRussell King struct armada_overlay_state *state; 30661ba2527SRussell King 30761ba2527SRussell King if (plane->state) 30861ba2527SRussell King __drm_atomic_helper_plane_destroy_state(plane->state); 30961ba2527SRussell King kfree(plane->state); 310ad52f53fSRussell King plane->state = NULL; 31161ba2527SRussell King 31261ba2527SRussell King state = kzalloc(sizeof(*state), GFP_KERNEL); 31361ba2527SRussell King if (state) { 314c96103b6SRussell King state->colorkey_yr = 0xfefefe00; 315c96103b6SRussell King state->colorkey_ug = 0x01010100; 316c96103b6SRussell King state->colorkey_vb = 0x01010100; 317c96103b6SRussell King state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) | 318c96103b6SRussell King CFG_ALPHAM_GRA | CFG_ALPHA(0); 319c96103b6SRussell King state->colorkey_enable = ADV_GRACOLORKEY; 32061ba2527SRussell King state->brightness = DEFAULT_BRIGHTNESS; 32161ba2527SRussell King state->contrast = DEFAULT_CONTRAST; 32261ba2527SRussell King state->saturation = DEFAULT_SATURATION; 323ad52f53fSRussell King __drm_atomic_helper_plane_reset(plane, &state->base); 324ad52f53fSRussell King state->base.color_encoding = DEFAULT_ENCODING; 325ad52f53fSRussell King state->base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; 32661ba2527SRussell King } 32761ba2527SRussell King } 32861ba2527SRussell King 32961ba2527SRussell King struct drm_plane_state * 33061ba2527SRussell King armada_overlay_duplicate_state(struct drm_plane *plane) 33161ba2527SRussell King { 33261ba2527SRussell King struct armada_overlay_state *state; 33361ba2527SRussell King 33461ba2527SRussell King if (WARN_ON(!plane->state)) 33561ba2527SRussell King return NULL; 33661ba2527SRussell King 33761ba2527SRussell King state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL); 33861ba2527SRussell King if (state) 33961ba2527SRussell King __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 34061ba2527SRussell King return &state->base; 34161ba2527SRussell King } 34261ba2527SRussell King 34361ba2527SRussell King static int armada_overlay_set_property(struct drm_plane *plane, 34461ba2527SRussell King struct drm_plane_state *state, struct drm_property *property, 34561ba2527SRussell King uint64_t val) 34661ba2527SRussell King { 34761ba2527SRussell King struct armada_private *priv = plane->dev->dev_private; 34861ba2527SRussell King 349c96103b6SRussell King #define K2R(val) (((val) >> 0) & 0xff) 350c96103b6SRussell King #define K2G(val) (((val) >> 8) & 0xff) 351c96103b6SRussell King #define K2B(val) (((val) >> 16) & 0xff) 352c96103b6SRussell King if (property == priv->colorkey_prop) { 353c96103b6SRussell King #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8) 354c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val)); 355c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val)); 356c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val)); 357c96103b6SRussell King #undef CCC 358c96103b6SRussell King } else if (property == priv->colorkey_min_prop) { 359c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000; 360c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16; 361c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000; 362c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16; 363c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000; 364c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16; 365c96103b6SRussell King } else if (property == priv->colorkey_max_prop) { 366c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000; 367c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24; 368c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000; 369c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24; 370c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000; 371c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24; 372c96103b6SRussell King } else if (property == priv->colorkey_val_prop) { 373c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00; 374c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8; 375c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00; 376c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8; 377c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00; 378c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8; 379c96103b6SRussell King } else if (property == priv->colorkey_alpha_prop) { 380c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff; 381c96103b6SRussell King drm_to_overlay_state(state)->colorkey_yr |= K2R(val); 382c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff; 383c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug |= K2G(val); 384c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff; 385c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb |= K2B(val); 386c96103b6SRussell King } else if (property == priv->colorkey_mode_prop) { 387c96103b6SRussell King if (val == CKMODE_DISABLE) { 388c96103b6SRussell King drm_to_overlay_state(state)->colorkey_mode = 389c96103b6SRussell King CFG_CKMODE(CKMODE_DISABLE) | 390c96103b6SRussell King CFG_ALPHAM_CFG | CFG_ALPHA(255); 391c96103b6SRussell King drm_to_overlay_state(state)->colorkey_enable = 0; 392c96103b6SRussell King } else { 393c96103b6SRussell King drm_to_overlay_state(state)->colorkey_mode = 394c96103b6SRussell King CFG_CKMODE(val) | 395c96103b6SRussell King CFG_ALPHAM_GRA | CFG_ALPHA(0); 396c96103b6SRussell King drm_to_overlay_state(state)->colorkey_enable = 397c96103b6SRussell King ADV_GRACOLORKEY; 398c96103b6SRussell King } 399c96103b6SRussell King } else if (property == priv->brightness_prop) { 40061ba2527SRussell King drm_to_overlay_state(state)->brightness = val - 256; 40161ba2527SRussell King } else if (property == priv->contrast_prop) { 40261ba2527SRussell King drm_to_overlay_state(state)->contrast = val; 40361ba2527SRussell King } else if (property == priv->saturation_prop) { 40461ba2527SRussell King drm_to_overlay_state(state)->saturation = val; 40561ba2527SRussell King } else { 40661ba2527SRussell King return -EINVAL; 40761ba2527SRussell King } 40861ba2527SRussell King return 0; 40961ba2527SRussell King } 41061ba2527SRussell King 41161ba2527SRussell King static int armada_overlay_get_property(struct drm_plane *plane, 41261ba2527SRussell King const struct drm_plane_state *state, struct drm_property *property, 41361ba2527SRussell King uint64_t *val) 41461ba2527SRussell King { 41561ba2527SRussell King struct armada_private *priv = plane->dev->dev_private; 41661ba2527SRussell King 417c96103b6SRussell King #define C2K(c,s) (((c) >> (s)) & 0xff) 418c96103b6SRussell King #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16) 419c96103b6SRussell King if (property == priv->colorkey_prop) { 420c96103b6SRussell King /* Do best-efforts here for this property */ 421c96103b6SRussell King *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 422c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug, 423c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb, 16); 424c96103b6SRussell King /* If min != max, or min != val, error out */ 425c96103b6SRussell King if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 426c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug, 427c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb, 24) || 428c96103b6SRussell King *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr, 429c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug, 430c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb, 8)) 431c96103b6SRussell King return -EINVAL; 432c96103b6SRussell King } else if (property == priv->colorkey_min_prop) { 433c96103b6SRussell King *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 434c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug, 435c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb, 16); 436c96103b6SRussell King } else if (property == priv->colorkey_max_prop) { 437c96103b6SRussell King *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 438c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug, 439c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb, 24); 440c96103b6SRussell King } else if (property == priv->colorkey_val_prop) { 441c96103b6SRussell King *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 442c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug, 443c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb, 8); 444c96103b6SRussell King } else if (property == priv->colorkey_alpha_prop) { 445c96103b6SRussell King *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr, 446c96103b6SRussell King drm_to_overlay_state(state)->colorkey_ug, 447c96103b6SRussell King drm_to_overlay_state(state)->colorkey_vb, 0); 448c96103b6SRussell King } else if (property == priv->colorkey_mode_prop) { 449c96103b6SRussell King *val = (drm_to_overlay_state(state)->colorkey_mode & 450c96103b6SRussell King CFG_CKMODE_MASK) >> ffs(CFG_CKMODE_MASK); 451c96103b6SRussell King } else if (property == priv->brightness_prop) { 45261ba2527SRussell King *val = drm_to_overlay_state(state)->brightness + 256; 45361ba2527SRussell King } else if (property == priv->contrast_prop) { 45461ba2527SRussell King *val = drm_to_overlay_state(state)->contrast; 45561ba2527SRussell King } else if (property == priv->saturation_prop) { 45661ba2527SRussell King *val = drm_to_overlay_state(state)->saturation; 45761ba2527SRussell King } else { 45861ba2527SRussell King return -EINVAL; 45961ba2527SRussell King } 46061ba2527SRussell King return 0; 46161ba2527SRussell King } 46261ba2527SRussell King 46328a2aebeSRussell King static const struct drm_plane_funcs armada_ovl_plane_funcs = { 464b1ec9ed6SRussell King .update_plane = armada_overlay_plane_update, 465b1ec9ed6SRussell King .disable_plane = drm_atomic_helper_disable_plane, 46628a2aebeSRussell King .destroy = armada_ovl_plane_destroy, 46761ba2527SRussell King .reset = armada_overlay_reset, 46861ba2527SRussell King .atomic_duplicate_state = armada_overlay_duplicate_state, 46961ba2527SRussell King .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 47061ba2527SRussell King .atomic_set_property = armada_overlay_set_property, 47161ba2527SRussell King .atomic_get_property = armada_overlay_get_property, 47296f60e37SRussell King }; 47396f60e37SRussell King 47428a2aebeSRussell King static const uint32_t armada_ovl_formats[] = { 47596f60e37SRussell King DRM_FORMAT_UYVY, 47696f60e37SRussell King DRM_FORMAT_YUYV, 47796f60e37SRussell King DRM_FORMAT_YUV420, 47896f60e37SRussell King DRM_FORMAT_YVU420, 47996f60e37SRussell King DRM_FORMAT_YUV422, 48096f60e37SRussell King DRM_FORMAT_YVU422, 48196f60e37SRussell King DRM_FORMAT_VYUY, 48296f60e37SRussell King DRM_FORMAT_YVYU, 48396f60e37SRussell King DRM_FORMAT_ARGB8888, 48496f60e37SRussell King DRM_FORMAT_ABGR8888, 48596f60e37SRussell King DRM_FORMAT_XRGB8888, 48696f60e37SRussell King DRM_FORMAT_XBGR8888, 48796f60e37SRussell King DRM_FORMAT_RGB888, 48896f60e37SRussell King DRM_FORMAT_BGR888, 48996f60e37SRussell King DRM_FORMAT_ARGB1555, 49096f60e37SRussell King DRM_FORMAT_ABGR1555, 49196f60e37SRussell King DRM_FORMAT_RGB565, 49296f60e37SRussell King DRM_FORMAT_BGR565, 49396f60e37SRussell King }; 49496f60e37SRussell King 4958a63ca58SArvind Yadav static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = { 49696f60e37SRussell King { CKMODE_DISABLE, "disabled" }, 49796f60e37SRussell King { CKMODE_Y, "Y component" }, 49896f60e37SRussell King { CKMODE_U, "U component" }, 49996f60e37SRussell King { CKMODE_V, "V component" }, 50096f60e37SRussell King { CKMODE_RGB, "RGB" }, 50196f60e37SRussell King { CKMODE_R, "R component" }, 50296f60e37SRussell King { CKMODE_G, "G component" }, 50396f60e37SRussell King { CKMODE_B, "B component" }, 50496f60e37SRussell King }; 50596f60e37SRussell King 50696f60e37SRussell King static int armada_overlay_create_properties(struct drm_device *dev) 50796f60e37SRussell King { 50896f60e37SRussell King struct armada_private *priv = dev->dev_private; 50996f60e37SRussell King 51096f60e37SRussell King if (priv->colorkey_prop) 51196f60e37SRussell King return 0; 51296f60e37SRussell King 51396f60e37SRussell King priv->colorkey_prop = drm_property_create_range(dev, 0, 51496f60e37SRussell King "colorkey", 0, 0xffffff); 51596f60e37SRussell King priv->colorkey_min_prop = drm_property_create_range(dev, 0, 51696f60e37SRussell King "colorkey_min", 0, 0xffffff); 51796f60e37SRussell King priv->colorkey_max_prop = drm_property_create_range(dev, 0, 51896f60e37SRussell King "colorkey_max", 0, 0xffffff); 51996f60e37SRussell King priv->colorkey_val_prop = drm_property_create_range(dev, 0, 52096f60e37SRussell King "colorkey_val", 0, 0xffffff); 52196f60e37SRussell King priv->colorkey_alpha_prop = drm_property_create_range(dev, 0, 52296f60e37SRussell King "colorkey_alpha", 0, 0xffffff); 52396f60e37SRussell King priv->colorkey_mode_prop = drm_property_create_enum(dev, 0, 52496f60e37SRussell King "colorkey_mode", 52596f60e37SRussell King armada_drm_colorkey_enum_list, 52696f60e37SRussell King ARRAY_SIZE(armada_drm_colorkey_enum_list)); 52796f60e37SRussell King priv->brightness_prop = drm_property_create_range(dev, 0, 52896f60e37SRussell King "brightness", 0, 256 + 255); 52996f60e37SRussell King priv->contrast_prop = drm_property_create_range(dev, 0, 53096f60e37SRussell King "contrast", 0, 0x7fff); 53196f60e37SRussell King priv->saturation_prop = drm_property_create_range(dev, 0, 53296f60e37SRussell King "saturation", 0, 0x7fff); 53396f60e37SRussell King 53496f60e37SRussell King if (!priv->colorkey_prop) 53596f60e37SRussell King return -ENOMEM; 53696f60e37SRussell King 53796f60e37SRussell King return 0; 53896f60e37SRussell King } 53996f60e37SRussell King 54096f60e37SRussell King int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) 54196f60e37SRussell King { 54296f60e37SRussell King struct armada_private *priv = dev->dev_private; 54396f60e37SRussell King struct drm_mode_object *mobj; 544d701278aSRussell King struct drm_plane *overlay; 54596f60e37SRussell King int ret; 54696f60e37SRussell King 54796f60e37SRussell King ret = armada_overlay_create_properties(dev); 54896f60e37SRussell King if (ret) 54996f60e37SRussell King return ret; 55096f60e37SRussell King 551d701278aSRussell King overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 552d701278aSRussell King if (!overlay) 55396f60e37SRussell King return -ENOMEM; 55496f60e37SRussell King 555d701278aSRussell King drm_plane_helper_add(overlay, &armada_overlay_plane_helper_funcs); 5565740d27fSRussell King 557d701278aSRussell King ret = drm_universal_plane_init(dev, overlay, crtcs, 558d563c245SRussell King &armada_ovl_plane_funcs, 559d563c245SRussell King armada_ovl_formats, 560d563c245SRussell King ARRAY_SIZE(armada_ovl_formats), 561e6fc3b68SBen Widawsky NULL, 562b0b3b795SVille Syrjälä DRM_PLANE_TYPE_OVERLAY, NULL); 56328a2aebeSRussell King if (ret) { 564d701278aSRussell King kfree(overlay); 56528a2aebeSRussell King return ret; 56628a2aebeSRussell King } 56796f60e37SRussell King 568d701278aSRussell King mobj = &overlay->base; 56996f60e37SRussell King drm_object_attach_property(mobj, priv->colorkey_prop, 57096f60e37SRussell King 0x0101fe); 57196f60e37SRussell King drm_object_attach_property(mobj, priv->colorkey_min_prop, 57296f60e37SRussell King 0x0101fe); 57396f60e37SRussell King drm_object_attach_property(mobj, priv->colorkey_max_prop, 57496f60e37SRussell King 0x0101fe); 57596f60e37SRussell King drm_object_attach_property(mobj, priv->colorkey_val_prop, 57696f60e37SRussell King 0x0101fe); 57796f60e37SRussell King drm_object_attach_property(mobj, priv->colorkey_alpha_prop, 57896f60e37SRussell King 0x000000); 57996f60e37SRussell King drm_object_attach_property(mobj, priv->colorkey_mode_prop, 58096f60e37SRussell King CKMODE_RGB); 58161ba2527SRussell King drm_object_attach_property(mobj, priv->brightness_prop, 58261ba2527SRussell King 256 + DEFAULT_BRIGHTNESS); 58396f60e37SRussell King drm_object_attach_property(mobj, priv->contrast_prop, 58461ba2527SRussell King DEFAULT_CONTRAST); 58596f60e37SRussell King drm_object_attach_property(mobj, priv->saturation_prop, 58661ba2527SRussell King DEFAULT_SATURATION); 58796f60e37SRussell King 588d701278aSRussell King ret = drm_plane_create_color_properties(overlay, 589c29277d4SRussell King BIT(DRM_COLOR_YCBCR_BT601) | 590c29277d4SRussell King BIT(DRM_COLOR_YCBCR_BT709), 591c29277d4SRussell King BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), 592c29277d4SRussell King DEFAULT_ENCODING, 593c29277d4SRussell King DRM_COLOR_YCBCR_LIMITED_RANGE); 594c29277d4SRussell King 595c29277d4SRussell King return ret; 59696f60e37SRussell King } 597