1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
296f60e37SRussell King /*
396f60e37SRussell King  * Copyright (C) 2012 Russell King
496f60e37SRussell King  *  Rewritten from the dovefb driver, and Armada510 manuals.
596f60e37SRussell King  */
625e28ef2SSam Ravnborg 
7d40af7b1SRussell King #include <drm/armada_drm.h>
825e28ef2SSam Ravnborg #include <drm/drm_atomic.h>
925e28ef2SSam Ravnborg #include <drm/drm_atomic_helper.h>
1025e28ef2SSam Ravnborg #include <drm/drm_atomic_uapi.h>
1125e28ef2SSam Ravnborg #include <drm/drm_fourcc.h>
1225e28ef2SSam Ravnborg #include <drm/drm_plane_helper.h>
1325e28ef2SSam Ravnborg 
1496f60e37SRussell King #include "armada_crtc.h"
1596f60e37SRussell King #include "armada_drm.h"
1696f60e37SRussell King #include "armada_fb.h"
1796f60e37SRussell King #include "armada_gem.h"
1896f60e37SRussell King #include "armada_hw.h"
1996f60e37SRussell King #include "armada_ioctlP.h"
20d40af7b1SRussell King #include "armada_plane.h"
21c8a220c6SRussell King #include "armada_trace.h"
2296f60e37SRussell King 
2361ba2527SRussell King #define DEFAULT_BRIGHTNESS	0
2461ba2527SRussell King #define DEFAULT_CONTRAST	0x4000
2561ba2527SRussell King #define DEFAULT_SATURATION	0x4000
26c29277d4SRussell King #define DEFAULT_ENCODING	DRM_COLOR_YCBCR_BT601
2761ba2527SRussell King 
2861ba2527SRussell King struct armada_overlay_state {
291d1547ecSRussell King 	struct armada_plane_state base;
30c96103b6SRussell King 	u32 colorkey_yr;
31c96103b6SRussell King 	u32 colorkey_ug;
32c96103b6SRussell King 	u32 colorkey_vb;
33c96103b6SRussell King 	u32 colorkey_mode;
34c96103b6SRussell King 	u32 colorkey_enable;
3561ba2527SRussell King 	s16 brightness;
3661ba2527SRussell King 	u16 contrast;
3761ba2527SRussell King 	u16 saturation;
3861ba2527SRussell King };
3961ba2527SRussell King #define drm_to_overlay_state(s) \
401d1547ecSRussell King 	container_of(s, struct armada_overlay_state, base.base)
4161ba2527SRussell King 
4261ba2527SRussell King static inline u32 armada_spu_contrast(struct drm_plane_state *state)
4361ba2527SRussell King {
4461ba2527SRussell King 	return drm_to_overlay_state(state)->brightness << 16 |
4561ba2527SRussell King 	       drm_to_overlay_state(state)->contrast;
4661ba2527SRussell King }
4761ba2527SRussell King 
4861ba2527SRussell King static inline u32 armada_spu_saturation(struct drm_plane_state *state)
4961ba2527SRussell King {
5061ba2527SRussell King 	/* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
5161ba2527SRussell King 	return drm_to_overlay_state(state)->saturation << 16;
5261ba2527SRussell King }
5396f60e37SRussell King 
54c29277d4SRussell King static inline u32 armada_csc(struct drm_plane_state *state)
55c29277d4SRussell King {
56c29277d4SRussell King 	/*
57c29277d4SRussell King 	 * The CFG_CSC_RGB_* settings control the output of the colour space
58c29277d4SRussell King 	 * converter, setting the range of output values it produces.  Since
59c29277d4SRussell King 	 * we will be blending with the full-range graphics, we need to
60c29277d4SRussell King 	 * produce full-range RGB output from the conversion.
61c29277d4SRussell King 	 */
62c29277d4SRussell King 	return CFG_CSC_RGB_COMPUTER |
63c29277d4SRussell King 	       (state->color_encoding == DRM_COLOR_YCBCR_BT709 ?
64c29277d4SRussell King 			CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601);
65c29277d4SRussell King }
66c29277d4SRussell King 
6796f60e37SRussell King /* === Plane support === */
6847dc413bSRussell King static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
6947dc413bSRussell King 	struct drm_plane_state *old_state)
7047dc413bSRussell King {
71*41016fe1SMaxime Ripard 	struct drm_plane_state *new_state = plane->state;
7247dc413bSRussell King 	struct armada_crtc *dcrtc;
7347dc413bSRussell King 	struct armada_regs *regs;
743acea7b9SRussell King 	unsigned int idx;
753acea7b9SRussell King 	u32 cfg, cfg_mask, val;
7647dc413bSRussell King 
7747dc413bSRussell King 	DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
7847dc413bSRussell King 
79*41016fe1SMaxime Ripard 	if (!new_state->fb || WARN_ON(!new_state->crtc))
8047dc413bSRussell King 		return;
8147dc413bSRussell King 
8247dc413bSRussell King 	DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
8347dc413bSRussell King 		plane->base.id, plane->name,
84*41016fe1SMaxime Ripard 		new_state->crtc->base.id, new_state->crtc->name,
85*41016fe1SMaxime Ripard 		new_state->fb->base.id,
86*41016fe1SMaxime Ripard 		old_state->visible, new_state->visible);
8747dc413bSRussell King 
88*41016fe1SMaxime Ripard 	dcrtc = drm_to_armada_crtc(new_state->crtc);
8947dc413bSRussell King 	regs = dcrtc->regs + dcrtc->regs_idx;
9047dc413bSRussell King 
913acea7b9SRussell King 	idx = 0;
92*41016fe1SMaxime Ripard 	if (!old_state->visible && new_state->visible)
933acea7b9SRussell King 		armada_reg_queue_mod(regs, idx,
943acea7b9SRussell King 				     0, CFG_PDWN16x66 | CFG_PDWN32x66,
953acea7b9SRussell King 				     LCD_SPU_SRAM_PARA1);
96*41016fe1SMaxime Ripard 	val = armada_src_hw(new_state);
979184ae8dSRussell King 	if (armada_src_hw(old_state) != val)
983acea7b9SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
99*41016fe1SMaxime Ripard 	val = armada_dst_yx(new_state);
1009184ae8dSRussell King 	if (armada_dst_yx(old_state) != val)
1013acea7b9SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
102*41016fe1SMaxime Ripard 	val = armada_dst_hw(new_state);
1039184ae8dSRussell King 	if (armada_dst_hw(old_state) != val)
1043acea7b9SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
1053acea7b9SRussell King 	/* FIXME: overlay on an interlaced display */
106*41016fe1SMaxime Ripard 	if (old_state->src.x1 != new_state->src.x1 ||
107*41016fe1SMaxime Ripard 	    old_state->src.y1 != new_state->src.y1 ||
108*41016fe1SMaxime Ripard 	    old_state->fb != new_state->fb ||
109*41016fe1SMaxime Ripard 	    new_state->crtc->state->mode_changed) {
1103acea7b9SRussell King 		const struct drm_format_info *format;
1117d62237dSRussell King 		u16 src_x;
1123acea7b9SRussell King 
113*41016fe1SMaxime Ripard 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
1143acea7b9SRussell King 				     LCD_SPU_DMA_START_ADDR_Y0);
115*41016fe1SMaxime Ripard 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),
1163acea7b9SRussell King 				     LCD_SPU_DMA_START_ADDR_U0);
117*41016fe1SMaxime Ripard 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),
1183acea7b9SRussell King 				     LCD_SPU_DMA_START_ADDR_V0);
119*41016fe1SMaxime Ripard 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
1203acea7b9SRussell King 				     LCD_SPU_DMA_START_ADDR_Y1);
121*41016fe1SMaxime Ripard 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),
1223acea7b9SRussell King 				     LCD_SPU_DMA_START_ADDR_U1);
123*41016fe1SMaxime Ripard 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),
1243acea7b9SRussell King 				     LCD_SPU_DMA_START_ADDR_V1);
1253acea7b9SRussell King 
126*41016fe1SMaxime Ripard 		val = armada_pitch(new_state, 0) << 16 | armada_pitch(new_state,
127*41016fe1SMaxime Ripard 								      0);
1283acea7b9SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
129*41016fe1SMaxime Ripard 		val = armada_pitch(new_state, 1) << 16 | armada_pitch(new_state,
130*41016fe1SMaxime Ripard 								      2);
1313acea7b9SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
1323acea7b9SRussell King 
133*41016fe1SMaxime Ripard 		cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
134*41016fe1SMaxime Ripard 		      CFG_DMA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod) |
1353acea7b9SRussell King 		      CFG_CBSH_ENA;
136*41016fe1SMaxime Ripard 		if (new_state->visible)
1373acea7b9SRussell King 			cfg |= CFG_DMA_ENA;
1383acea7b9SRussell King 
1393acea7b9SRussell King 		/*
1403acea7b9SRussell King 		 * Shifting a YUV packed format image by one pixel causes the
1413acea7b9SRussell King 		 * U/V planes to swap.  Compensate for it by also toggling
1423acea7b9SRussell King 		 * the UV swap.
1433acea7b9SRussell King 		 */
144*41016fe1SMaxime Ripard 		format = new_state->fb->format;
145*41016fe1SMaxime Ripard 		src_x = new_state->src.x1 >> 16;
1463acea7b9SRussell King 		if (format->num_planes == 1 && src_x & (format->hsub - 1))
1473acea7b9SRussell King 			cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
148*41016fe1SMaxime Ripard 		if (to_armada_plane_state(new_state)->interlace)
14989e0c53cSRussell King 			cfg |= CFG_DMA_FTOGGLE;
1503acea7b9SRussell King 		cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
1513acea7b9SRussell King 			   CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
1523acea7b9SRussell King 				       CFG_SWAPYU | CFG_YUV2RGB) |
1533acea7b9SRussell King 			   CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |
1543acea7b9SRussell King 			   CFG_DMA_ENA;
155*41016fe1SMaxime Ripard 	} else if (old_state->visible != new_state->visible) {
156*41016fe1SMaxime Ripard 		cfg = new_state->visible ? CFG_DMA_ENA : 0;
1573acea7b9SRussell King 		cfg_mask = CFG_DMA_ENA;
1583acea7b9SRussell King 	} else {
1593acea7b9SRussell King 		cfg = cfg_mask = 0;
1603acea7b9SRussell King 	}
161*41016fe1SMaxime Ripard 	if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
162*41016fe1SMaxime Ripard 	    drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
1633acea7b9SRussell King 		cfg_mask |= CFG_DMA_HSMOOTH;
164*41016fe1SMaxime Ripard 		if (drm_rect_width(&new_state->src) >> 16 !=
165*41016fe1SMaxime Ripard 		    drm_rect_width(&new_state->dst))
1663acea7b9SRussell King 			cfg |= CFG_DMA_HSMOOTH;
1673acea7b9SRussell King 	}
1683acea7b9SRussell King 
1693acea7b9SRussell King 	if (cfg_mask)
1703acea7b9SRussell King 		armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
1713acea7b9SRussell King 				     LCD_SPU_DMA_CTRL0);
1723acea7b9SRussell King 
173*41016fe1SMaxime Ripard 	val = armada_spu_contrast(new_state);
174*41016fe1SMaxime Ripard 	if ((!old_state->visible && new_state->visible) ||
17561ba2527SRussell King 	    armada_spu_contrast(old_state) != val)
17661ba2527SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);
177*41016fe1SMaxime Ripard 	val = armada_spu_saturation(new_state);
178*41016fe1SMaxime Ripard 	if ((!old_state->visible && new_state->visible) ||
17961ba2527SRussell King 	    armada_spu_saturation(old_state) != val)
18061ba2527SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);
181*41016fe1SMaxime Ripard 	if (!old_state->visible && new_state->visible)
18261ba2527SRussell King 		armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);
183*41016fe1SMaxime Ripard 	val = armada_csc(new_state);
184*41016fe1SMaxime Ripard 	if ((!old_state->visible && new_state->visible) ||
185c29277d4SRussell King 	    armada_csc(old_state) != val)
186c29277d4SRussell King 		armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK,
187c29277d4SRussell King 				     LCD_SPU_IOPAD_CONTROL);
188*41016fe1SMaxime Ripard 	val = drm_to_overlay_state(new_state)->colorkey_yr;
189*41016fe1SMaxime Ripard 	if ((!old_state->visible && new_state->visible) ||
190c96103b6SRussell King 	    drm_to_overlay_state(old_state)->colorkey_yr != val)
191c96103b6SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);
192*41016fe1SMaxime Ripard 	val = drm_to_overlay_state(new_state)->colorkey_ug;
193*41016fe1SMaxime Ripard 	if ((!old_state->visible && new_state->visible) ||
194c96103b6SRussell King 	    drm_to_overlay_state(old_state)->colorkey_ug != val)
195c96103b6SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);
196*41016fe1SMaxime Ripard 	val = drm_to_overlay_state(new_state)->colorkey_vb;
197*41016fe1SMaxime Ripard 	if ((!old_state->visible && new_state->visible) ||
198c96103b6SRussell King 	    drm_to_overlay_state(old_state)->colorkey_vb != val)
199c96103b6SRussell King 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);
200*41016fe1SMaxime Ripard 	val = drm_to_overlay_state(new_state)->colorkey_mode;
201*41016fe1SMaxime Ripard 	if ((!old_state->visible && new_state->visible) ||
202c96103b6SRussell King 	    drm_to_overlay_state(old_state)->colorkey_mode != val)
203c96103b6SRussell King 		armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK |
204c96103b6SRussell King 				     CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
205c96103b6SRussell King 				     LCD_SPU_DMA_CTRL1);
206*41016fe1SMaxime Ripard 	val = drm_to_overlay_state(new_state)->colorkey_enable;
207*41016fe1SMaxime Ripard 	if (((!old_state->visible && new_state->visible) ||
208c96103b6SRussell King 	     drm_to_overlay_state(old_state)->colorkey_enable != val) &&
209c96103b6SRussell King 	    dcrtc->variant->has_spu_adv_reg)
210c96103b6SRussell King 		armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY |
211c96103b6SRussell King 				     ADV_VIDCOLORKEY, LCD_SPU_ADV_REG);
21261ba2527SRussell King 
2133acea7b9SRussell King 	dcrtc->regs_idx += idx;
21447dc413bSRussell King }
21547dc413bSRussell King 
21647dc413bSRussell King static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane,
21747dc413bSRussell King 	struct drm_plane_state *old_state)
21847dc413bSRussell King {
21947dc413bSRussell King 	struct armada_crtc *dcrtc;
22047dc413bSRussell King 	struct armada_regs *regs;
22147dc413bSRussell King 	unsigned int idx = 0;
22247dc413bSRussell King 
22347dc413bSRussell King 	DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
22447dc413bSRussell King 
22547dc413bSRussell King 	if (!old_state->crtc)
22647dc413bSRussell King 		return;
22747dc413bSRussell King 
22847dc413bSRussell King 	DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
22947dc413bSRussell King 		plane->base.id, plane->name,
23047dc413bSRussell King 		old_state->crtc->base.id, old_state->crtc->name,
23147dc413bSRussell King 		old_state->fb->base.id);
23247dc413bSRussell King 
23347dc413bSRussell King 	dcrtc = drm_to_armada_crtc(old_state->crtc);
23447dc413bSRussell King 	regs = dcrtc->regs + dcrtc->regs_idx;
23547dc413bSRussell King 
23647dc413bSRussell King 	/* Disable plane and power down the YUV FIFOs */
23747dc413bSRussell King 	armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0);
23847dc413bSRussell King 	armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0,
23947dc413bSRussell King 			     LCD_SPU_SRAM_PARA1);
24047dc413bSRussell King 
24147dc413bSRussell King 	dcrtc->regs_idx += idx;
24247dc413bSRussell King }
24347dc413bSRussell King 
24447dc413bSRussell King static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = {
24547dc413bSRussell King 	.prepare_fb	= armada_drm_plane_prepare_fb,
24647dc413bSRussell King 	.cleanup_fb	= armada_drm_plane_cleanup_fb,
24747dc413bSRussell King 	.atomic_check	= armada_drm_plane_atomic_check,
24847dc413bSRussell King 	.atomic_update	= armada_drm_overlay_plane_atomic_update,
24947dc413bSRussell King 	.atomic_disable	= armada_drm_overlay_plane_atomic_disable,
25047dc413bSRussell King };
25147dc413bSRussell King 
25247dc413bSRussell King static int
253b1ec9ed6SRussell King armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
25447dc413bSRussell King 	struct drm_framebuffer *fb,
25547dc413bSRussell King 	int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
25647dc413bSRussell King 	uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
25747dc413bSRussell King 	struct drm_modeset_acquire_ctx *ctx)
25847dc413bSRussell King {
259b1ec9ed6SRussell King 	struct drm_atomic_state *state;
260b1ec9ed6SRussell King 	struct drm_plane_state *plane_state;
261b1ec9ed6SRussell King 	int ret = 0;
26247dc413bSRussell King 
26347dc413bSRussell King 	trace_armada_ovl_plane_update(plane, crtc, fb,
26447dc413bSRussell King 				 crtc_x, crtc_y, crtc_w, crtc_h,
26547dc413bSRussell King 				 src_x, src_y, src_w, src_h);
26647dc413bSRussell King 
267b1ec9ed6SRussell King 	state = drm_atomic_state_alloc(plane->dev);
26847dc413bSRussell King 	if (!state)
26947dc413bSRussell King 		return -ENOMEM;
27047dc413bSRussell King 
271b1ec9ed6SRussell King 	state->acquire_ctx = ctx;
272b1ec9ed6SRussell King 	plane_state = drm_atomic_get_plane_state(state, plane);
273b1ec9ed6SRussell King 	if (IS_ERR(plane_state)) {
274b1ec9ed6SRussell King 		ret = PTR_ERR(plane_state);
275b1ec9ed6SRussell King 		goto fail;
276b1ec9ed6SRussell King 	}
27747dc413bSRussell King 
278b1ec9ed6SRussell King 	ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
279b1ec9ed6SRussell King 	if (ret != 0)
280b1ec9ed6SRussell King 		goto fail;
281b1ec9ed6SRussell King 
282b1ec9ed6SRussell King 	drm_atomic_set_fb_for_plane(plane_state, fb);
283b1ec9ed6SRussell King 	plane_state->crtc_x = crtc_x;
284b1ec9ed6SRussell King 	plane_state->crtc_y = crtc_y;
285b1ec9ed6SRussell King 	plane_state->crtc_h = crtc_h;
286b1ec9ed6SRussell King 	plane_state->crtc_w = crtc_w;
287b1ec9ed6SRussell King 	plane_state->src_x = src_x;
288b1ec9ed6SRussell King 	plane_state->src_y = src_y;
289b1ec9ed6SRussell King 	plane_state->src_h = src_h;
290b1ec9ed6SRussell King 	plane_state->src_w = src_w;
291b1ec9ed6SRussell King 
292b1ec9ed6SRussell King 	ret = drm_atomic_nonblocking_commit(state);
293b1ec9ed6SRussell King fail:
294b1ec9ed6SRussell King 	drm_atomic_state_put(state);
295b1ec9ed6SRussell King 	return ret;
29696f60e37SRussell King }
29796f60e37SRussell King 
29828a2aebeSRussell King static void armada_ovl_plane_destroy(struct drm_plane *plane)
29996f60e37SRussell King {
30041dbb2dbSRussell King 	drm_plane_cleanup(plane);
301d701278aSRussell King 	kfree(plane);
30296f60e37SRussell King }
30396f60e37SRussell King 
30461ba2527SRussell King static void armada_overlay_reset(struct drm_plane *plane)
30561ba2527SRussell King {
30661ba2527SRussell King 	struct armada_overlay_state *state;
30761ba2527SRussell King 
30861ba2527SRussell King 	if (plane->state)
30961ba2527SRussell King 		__drm_atomic_helper_plane_destroy_state(plane->state);
31061ba2527SRussell King 	kfree(plane->state);
311ad52f53fSRussell King 	plane->state = NULL;
31261ba2527SRussell King 
31361ba2527SRussell King 	state = kzalloc(sizeof(*state), GFP_KERNEL);
31461ba2527SRussell King 	if (state) {
315c96103b6SRussell King 		state->colorkey_yr = 0xfefefe00;
316c96103b6SRussell King 		state->colorkey_ug = 0x01010100;
317c96103b6SRussell King 		state->colorkey_vb = 0x01010100;
318c96103b6SRussell King 		state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
319c96103b6SRussell King 				       CFG_ALPHAM_GRA | CFG_ALPHA(0);
320c96103b6SRussell King 		state->colorkey_enable = ADV_GRACOLORKEY;
32161ba2527SRussell King 		state->brightness = DEFAULT_BRIGHTNESS;
32261ba2527SRussell King 		state->contrast = DEFAULT_CONTRAST;
32361ba2527SRussell King 		state->saturation = DEFAULT_SATURATION;
3241d1547ecSRussell King 		__drm_atomic_helper_plane_reset(plane, &state->base.base);
3251d1547ecSRussell King 		state->base.base.color_encoding = DEFAULT_ENCODING;
3261d1547ecSRussell King 		state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
32761ba2527SRussell King 	}
32861ba2527SRussell King }
32961ba2527SRussell King 
330f8ef48ffSLee Jones static struct drm_plane_state *
33161ba2527SRussell King armada_overlay_duplicate_state(struct drm_plane *plane)
33261ba2527SRussell King {
33361ba2527SRussell King 	struct armada_overlay_state *state;
33461ba2527SRussell King 
33561ba2527SRussell King 	if (WARN_ON(!plane->state))
33661ba2527SRussell King 		return NULL;
33761ba2527SRussell King 
33861ba2527SRussell King 	state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL);
33961ba2527SRussell King 	if (state)
3401d1547ecSRussell King 		__drm_atomic_helper_plane_duplicate_state(plane,
3411d1547ecSRussell King 							  &state->base.base);
3421d1547ecSRussell King 	return &state->base.base;
34361ba2527SRussell King }
34461ba2527SRussell King 
34561ba2527SRussell King static int armada_overlay_set_property(struct drm_plane *plane,
34661ba2527SRussell King 	struct drm_plane_state *state, struct drm_property *property,
34761ba2527SRussell King 	uint64_t val)
34861ba2527SRussell King {
349dad75a52SDaniel Vetter 	struct armada_private *priv = drm_to_armada_dev(plane->dev);
35061ba2527SRussell King 
351c96103b6SRussell King #define K2R(val) (((val) >> 0) & 0xff)
352c96103b6SRussell King #define K2G(val) (((val) >> 8) & 0xff)
353c96103b6SRussell King #define K2B(val) (((val) >> 16) & 0xff)
354c96103b6SRussell King 	if (property == priv->colorkey_prop) {
355c96103b6SRussell King #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
356c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val));
357c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val));
358c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val));
359c96103b6SRussell King #undef CCC
360c96103b6SRussell King 	} else if (property == priv->colorkey_min_prop) {
361c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000;
362c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16;
363c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000;
364c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16;
365c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000;
366c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16;
367c96103b6SRussell King 	} else if (property == priv->colorkey_max_prop) {
368c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000;
369c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24;
370c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000;
371c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24;
372c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000;
373c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24;
374c96103b6SRussell King 	} else if (property == priv->colorkey_val_prop) {
375c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00;
376c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8;
377c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00;
378c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8;
379c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00;
380c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8;
381c96103b6SRussell King 	} else if (property == priv->colorkey_alpha_prop) {
382c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff;
383c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_yr |= K2R(val);
384c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff;
385c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_ug |= K2G(val);
386c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff;
387c96103b6SRussell King 		drm_to_overlay_state(state)->colorkey_vb |= K2B(val);
388c96103b6SRussell King 	} else if (property == priv->colorkey_mode_prop) {
389c96103b6SRussell King 		if (val == CKMODE_DISABLE) {
390c96103b6SRussell King 			drm_to_overlay_state(state)->colorkey_mode =
391c96103b6SRussell King 				CFG_CKMODE(CKMODE_DISABLE) |
392c96103b6SRussell King 				CFG_ALPHAM_CFG | CFG_ALPHA(255);
393c96103b6SRussell King 			drm_to_overlay_state(state)->colorkey_enable = 0;
394c96103b6SRussell King 		} else {
395c96103b6SRussell King 			drm_to_overlay_state(state)->colorkey_mode =
396c96103b6SRussell King 				CFG_CKMODE(val) |
397c96103b6SRussell King 				CFG_ALPHAM_GRA | CFG_ALPHA(0);
398c96103b6SRussell King 			drm_to_overlay_state(state)->colorkey_enable =
399c96103b6SRussell King 				ADV_GRACOLORKEY;
400c96103b6SRussell King 		}
401c96103b6SRussell King 	} else if (property == priv->brightness_prop) {
40261ba2527SRussell King 		drm_to_overlay_state(state)->brightness = val - 256;
40361ba2527SRussell King 	} else if (property == priv->contrast_prop) {
40461ba2527SRussell King 		drm_to_overlay_state(state)->contrast = val;
40561ba2527SRussell King 	} else if (property == priv->saturation_prop) {
40661ba2527SRussell King 		drm_to_overlay_state(state)->saturation = val;
40761ba2527SRussell King 	} else {
40861ba2527SRussell King 		return -EINVAL;
40961ba2527SRussell King 	}
41061ba2527SRussell King 	return 0;
41161ba2527SRussell King }
41261ba2527SRussell King 
41361ba2527SRussell King static int armada_overlay_get_property(struct drm_plane *plane,
41461ba2527SRussell King 	const struct drm_plane_state *state, struct drm_property *property,
41561ba2527SRussell King 	uint64_t *val)
41661ba2527SRussell King {
417dad75a52SDaniel Vetter 	struct armada_private *priv = drm_to_armada_dev(plane->dev);
41861ba2527SRussell King 
419c96103b6SRussell King #define C2K(c,s)	(((c) >> (s)) & 0xff)
420c96103b6SRussell King #define R2BGR(r,g,b,s)	(C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16)
421c96103b6SRussell King 	if (property == priv->colorkey_prop) {
422c96103b6SRussell King 		/* Do best-efforts here for this property */
423c96103b6SRussell King 		*val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
424c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_ug,
425c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_vb, 16);
426c96103b6SRussell King 		/* If min != max, or min != val, error out */
427c96103b6SRussell King 		if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
428c96103b6SRussell King 				  drm_to_overlay_state(state)->colorkey_ug,
429c96103b6SRussell King 				  drm_to_overlay_state(state)->colorkey_vb, 24) ||
430c96103b6SRussell King 		    *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
431c96103b6SRussell King 				  drm_to_overlay_state(state)->colorkey_ug,
432c96103b6SRussell King 				  drm_to_overlay_state(state)->colorkey_vb, 8))
433c96103b6SRussell King 			return -EINVAL;
434c96103b6SRussell King 	} else if (property == priv->colorkey_min_prop) {
435c96103b6SRussell King 		*val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
436c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_ug,
437c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_vb, 16);
438c96103b6SRussell King 	} else if (property == priv->colorkey_max_prop) {
439c96103b6SRussell King 		*val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
440c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_ug,
441c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_vb, 24);
442c96103b6SRussell King 	} else if (property == priv->colorkey_val_prop) {
443c96103b6SRussell King 		*val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
444c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_ug,
445c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_vb, 8);
446c96103b6SRussell King 	} else if (property == priv->colorkey_alpha_prop) {
447c96103b6SRussell King 		*val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
448c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_ug,
449c96103b6SRussell King 			     drm_to_overlay_state(state)->colorkey_vb, 0);
450c96103b6SRussell King 	} else if (property == priv->colorkey_mode_prop) {
451c96103b6SRussell King 		*val = (drm_to_overlay_state(state)->colorkey_mode &
452c96103b6SRussell King 			CFG_CKMODE_MASK) >> ffs(CFG_CKMODE_MASK);
453c96103b6SRussell King 	} else if (property == priv->brightness_prop) {
45461ba2527SRussell King 		*val = drm_to_overlay_state(state)->brightness + 256;
45561ba2527SRussell King 	} else if (property == priv->contrast_prop) {
45661ba2527SRussell King 		*val = drm_to_overlay_state(state)->contrast;
45761ba2527SRussell King 	} else if (property == priv->saturation_prop) {
45861ba2527SRussell King 		*val = drm_to_overlay_state(state)->saturation;
45961ba2527SRussell King 	} else {
46061ba2527SRussell King 		return -EINVAL;
46161ba2527SRussell King 	}
46261ba2527SRussell King 	return 0;
46361ba2527SRussell King }
46461ba2527SRussell King 
46528a2aebeSRussell King static const struct drm_plane_funcs armada_ovl_plane_funcs = {
466b1ec9ed6SRussell King 	.update_plane	= armada_overlay_plane_update,
467b1ec9ed6SRussell King 	.disable_plane	= drm_atomic_helper_disable_plane,
46828a2aebeSRussell King 	.destroy	= armada_ovl_plane_destroy,
46961ba2527SRussell King 	.reset		= armada_overlay_reset,
47061ba2527SRussell King 	.atomic_duplicate_state = armada_overlay_duplicate_state,
47161ba2527SRussell King 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
47261ba2527SRussell King 	.atomic_set_property = armada_overlay_set_property,
47361ba2527SRussell King 	.atomic_get_property = armada_overlay_get_property,
47496f60e37SRussell King };
47596f60e37SRussell King 
47628a2aebeSRussell King static const uint32_t armada_ovl_formats[] = {
47796f60e37SRussell King 	DRM_FORMAT_UYVY,
47896f60e37SRussell King 	DRM_FORMAT_YUYV,
47996f60e37SRussell King 	DRM_FORMAT_YUV420,
48096f60e37SRussell King 	DRM_FORMAT_YVU420,
48196f60e37SRussell King 	DRM_FORMAT_YUV422,
48296f60e37SRussell King 	DRM_FORMAT_YVU422,
48396f60e37SRussell King 	DRM_FORMAT_VYUY,
48496f60e37SRussell King 	DRM_FORMAT_YVYU,
48596f60e37SRussell King 	DRM_FORMAT_ARGB8888,
48696f60e37SRussell King 	DRM_FORMAT_ABGR8888,
48796f60e37SRussell King 	DRM_FORMAT_XRGB8888,
48896f60e37SRussell King 	DRM_FORMAT_XBGR8888,
48996f60e37SRussell King 	DRM_FORMAT_RGB888,
49096f60e37SRussell King 	DRM_FORMAT_BGR888,
49196f60e37SRussell King 	DRM_FORMAT_ARGB1555,
49296f60e37SRussell King 	DRM_FORMAT_ABGR1555,
49396f60e37SRussell King 	DRM_FORMAT_RGB565,
49496f60e37SRussell King 	DRM_FORMAT_BGR565,
49596f60e37SRussell King };
49696f60e37SRussell King 
4978a63ca58SArvind Yadav static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
49896f60e37SRussell King 	{ CKMODE_DISABLE, "disabled" },
49996f60e37SRussell King 	{ CKMODE_Y,       "Y component" },
50096f60e37SRussell King 	{ CKMODE_U,       "U component" },
50196f60e37SRussell King 	{ CKMODE_V,       "V component" },
50296f60e37SRussell King 	{ CKMODE_RGB,     "RGB" },
50396f60e37SRussell King 	{ CKMODE_R,       "R component" },
50496f60e37SRussell King 	{ CKMODE_G,       "G component" },
50596f60e37SRussell King 	{ CKMODE_B,       "B component" },
50696f60e37SRussell King };
50796f60e37SRussell King 
50896f60e37SRussell King static int armada_overlay_create_properties(struct drm_device *dev)
50996f60e37SRussell King {
510dad75a52SDaniel Vetter 	struct armada_private *priv = drm_to_armada_dev(dev);
51196f60e37SRussell King 
51296f60e37SRussell King 	if (priv->colorkey_prop)
51396f60e37SRussell King 		return 0;
51496f60e37SRussell King 
51596f60e37SRussell King 	priv->colorkey_prop = drm_property_create_range(dev, 0,
51696f60e37SRussell King 				"colorkey", 0, 0xffffff);
51796f60e37SRussell King 	priv->colorkey_min_prop = drm_property_create_range(dev, 0,
51896f60e37SRussell King 				"colorkey_min", 0, 0xffffff);
51996f60e37SRussell King 	priv->colorkey_max_prop = drm_property_create_range(dev, 0,
52096f60e37SRussell King 				"colorkey_max", 0, 0xffffff);
52196f60e37SRussell King 	priv->colorkey_val_prop = drm_property_create_range(dev, 0,
52296f60e37SRussell King 				"colorkey_val", 0, 0xffffff);
52396f60e37SRussell King 	priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
52496f60e37SRussell King 				"colorkey_alpha", 0, 0xffffff);
52596f60e37SRussell King 	priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
52696f60e37SRussell King 				"colorkey_mode",
52796f60e37SRussell King 				armada_drm_colorkey_enum_list,
52896f60e37SRussell King 				ARRAY_SIZE(armada_drm_colorkey_enum_list));
52996f60e37SRussell King 	priv->brightness_prop = drm_property_create_range(dev, 0,
53096f60e37SRussell King 				"brightness", 0, 256 + 255);
53196f60e37SRussell King 	priv->contrast_prop = drm_property_create_range(dev, 0,
53296f60e37SRussell King 				"contrast", 0, 0x7fff);
53396f60e37SRussell King 	priv->saturation_prop = drm_property_create_range(dev, 0,
53496f60e37SRussell King 				"saturation", 0, 0x7fff);
53596f60e37SRussell King 
53696f60e37SRussell King 	if (!priv->colorkey_prop)
53796f60e37SRussell King 		return -ENOMEM;
53896f60e37SRussell King 
53996f60e37SRussell King 	return 0;
54096f60e37SRussell King }
54196f60e37SRussell King 
54296f60e37SRussell King int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
54396f60e37SRussell King {
544dad75a52SDaniel Vetter 	struct armada_private *priv = drm_to_armada_dev(dev);
54596f60e37SRussell King 	struct drm_mode_object *mobj;
546d701278aSRussell King 	struct drm_plane *overlay;
54796f60e37SRussell King 	int ret;
54896f60e37SRussell King 
54996f60e37SRussell King 	ret = armada_overlay_create_properties(dev);
55096f60e37SRussell King 	if (ret)
55196f60e37SRussell King 		return ret;
55296f60e37SRussell King 
553d701278aSRussell King 	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
554d701278aSRussell King 	if (!overlay)
55596f60e37SRussell King 		return -ENOMEM;
55696f60e37SRussell King 
557d701278aSRussell King 	drm_plane_helper_add(overlay, &armada_overlay_plane_helper_funcs);
5585740d27fSRussell King 
559d701278aSRussell King 	ret = drm_universal_plane_init(dev, overlay, crtcs,
560d563c245SRussell King 				       &armada_ovl_plane_funcs,
561d563c245SRussell King 				       armada_ovl_formats,
562d563c245SRussell King 				       ARRAY_SIZE(armada_ovl_formats),
563e6fc3b68SBen Widawsky 				       NULL,
564b0b3b795SVille Syrjälä 				       DRM_PLANE_TYPE_OVERLAY, NULL);
56528a2aebeSRussell King 	if (ret) {
566d701278aSRussell King 		kfree(overlay);
56728a2aebeSRussell King 		return ret;
56828a2aebeSRussell King 	}
56996f60e37SRussell King 
570d701278aSRussell King 	mobj = &overlay->base;
57196f60e37SRussell King 	drm_object_attach_property(mobj, priv->colorkey_prop,
57296f60e37SRussell King 				   0x0101fe);
57396f60e37SRussell King 	drm_object_attach_property(mobj, priv->colorkey_min_prop,
57496f60e37SRussell King 				   0x0101fe);
57596f60e37SRussell King 	drm_object_attach_property(mobj, priv->colorkey_max_prop,
57696f60e37SRussell King 				   0x0101fe);
57796f60e37SRussell King 	drm_object_attach_property(mobj, priv->colorkey_val_prop,
57896f60e37SRussell King 				   0x0101fe);
57996f60e37SRussell King 	drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
58096f60e37SRussell King 				   0x000000);
58196f60e37SRussell King 	drm_object_attach_property(mobj, priv->colorkey_mode_prop,
58296f60e37SRussell King 				   CKMODE_RGB);
58361ba2527SRussell King 	drm_object_attach_property(mobj, priv->brightness_prop,
58461ba2527SRussell King 				   256 + DEFAULT_BRIGHTNESS);
58596f60e37SRussell King 	drm_object_attach_property(mobj, priv->contrast_prop,
58661ba2527SRussell King 				   DEFAULT_CONTRAST);
58796f60e37SRussell King 	drm_object_attach_property(mobj, priv->saturation_prop,
58861ba2527SRussell King 				   DEFAULT_SATURATION);
58996f60e37SRussell King 
590d701278aSRussell King 	ret = drm_plane_create_color_properties(overlay,
591c29277d4SRussell King 						BIT(DRM_COLOR_YCBCR_BT601) |
592c29277d4SRussell King 						BIT(DRM_COLOR_YCBCR_BT709),
593c29277d4SRussell King 						BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
594c29277d4SRussell King 						DEFAULT_ENCODING,
595c29277d4SRussell King 						DRM_COLOR_YCBCR_LIMITED_RANGE);
596c29277d4SRussell King 
597c29277d4SRussell King 	return ret;
59896f60e37SRussell King }
599