1 /* 2 * Copyright (C) 2012 Russell King 3 * Rewritten from the dovefb driver, and Armada510 manuals. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 #include <linux/clk.h> 10 #include <linux/component.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <drm/drmP.h> 14 #include <drm/drm_crtc_helper.h> 15 #include <drm/drm_plane_helper.h> 16 #include "armada_crtc.h" 17 #include "armada_drm.h" 18 #include "armada_fb.h" 19 #include "armada_gem.h" 20 #include "armada_hw.h" 21 #include "armada_trace.h" 22 23 struct armada_frame_work { 24 struct armada_plane_work work; 25 struct drm_pending_vblank_event *event; 26 struct armada_regs regs[4]; 27 struct drm_framebuffer *old_fb; 28 }; 29 30 enum csc_mode { 31 CSC_AUTO = 0, 32 CSC_YUV_CCIR601 = 1, 33 CSC_YUV_CCIR709 = 2, 34 CSC_RGB_COMPUTER = 1, 35 CSC_RGB_STUDIO = 2, 36 }; 37 38 static const uint32_t armada_primary_formats[] = { 39 DRM_FORMAT_UYVY, 40 DRM_FORMAT_YUYV, 41 DRM_FORMAT_VYUY, 42 DRM_FORMAT_YVYU, 43 DRM_FORMAT_ARGB8888, 44 DRM_FORMAT_ABGR8888, 45 DRM_FORMAT_XRGB8888, 46 DRM_FORMAT_XBGR8888, 47 DRM_FORMAT_RGB888, 48 DRM_FORMAT_BGR888, 49 DRM_FORMAT_ARGB1555, 50 DRM_FORMAT_ABGR1555, 51 DRM_FORMAT_RGB565, 52 DRM_FORMAT_BGR565, 53 }; 54 55 /* 56 * A note about interlacing. Let's consider HDMI 1920x1080i. 57 * The timing parameters we have from X are: 58 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot 59 * 1920 2448 2492 2640 1080 1084 1094 1125 60 * Which get translated to: 61 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot 62 * 1920 2448 2492 2640 540 542 547 562 63 * 64 * This is how it is defined by CEA-861-D - line and pixel numbers are 65 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per 66 * line: 2640. The odd frame, the first active line is at line 21, and 67 * the even frame, the first active line is 584. 68 * 69 * LN: 560 561 562 563 567 568 569 70 * DE: ~~~|____________________________//__________________________ 71 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ 72 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________ 73 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge). 74 * 75 * LN: 1123 1124 1125 1 5 6 7 76 * DE: ~~~|____________________________//__________________________ 77 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ 78 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________ 79 * 23 blanking lines 80 * 81 * The Armada LCD Controller line and pixel numbers are, like X timings, 82 * referenced to the top left of the active frame. 83 * 84 * So, translating these to our LCD controller: 85 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128. 86 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448. 87 * Note: Vsync front porch remains constant! 88 * 89 * if (odd_frame) { 90 * vtotal = mode->crtc_vtotal + 1; 91 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1; 92 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2 93 * } else { 94 * vtotal = mode->crtc_vtotal; 95 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay; 96 * vhorizpos = mode->crtc_hsync_start; 97 * } 98 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end; 99 * 100 * So, we need to reprogram these registers on each vsync event: 101 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL 102 * 103 * Note: we do not use the frame done interrupts because these appear 104 * to happen too early, and lead to jitter on the display (presumably 105 * they occur at the end of the last active line, before the vsync back 106 * porch, which we're reprogramming.) 107 */ 108 109 void 110 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) 111 { 112 while (regs->offset != ~0) { 113 void __iomem *reg = dcrtc->base + regs->offset; 114 uint32_t val; 115 116 val = regs->mask; 117 if (val != 0) 118 val &= readl_relaxed(reg); 119 writel_relaxed(val | regs->val, reg); 120 ++regs; 121 } 122 } 123 124 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON) 125 126 static void armada_drm_crtc_update(struct armada_crtc *dcrtc) 127 { 128 uint32_t dumb_ctrl; 129 130 dumb_ctrl = dcrtc->cfg_dumb_ctrl; 131 132 if (!dpms_blanked(dcrtc->dpms)) 133 dumb_ctrl |= CFG_DUMB_ENA; 134 135 /* 136 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might 137 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will 138 * force LCD_D[23:0] to output blank color, overriding the GPIO or 139 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode. 140 */ 141 if (dpms_blanked(dcrtc->dpms) && 142 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) { 143 dumb_ctrl &= ~DUMB_MASK; 144 dumb_ctrl |= DUMB_BLANK; 145 } 146 147 /* 148 * The documentation doesn't indicate what the normal state of 149 * the sync signals are. Sebastian Hesselbart kindly probed 150 * these signals on his board to determine their state. 151 * 152 * The non-inverted state of the sync signals is active high. 153 * Setting these bits makes the appropriate signal active low. 154 */ 155 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC) 156 dumb_ctrl |= CFG_INV_CSYNC; 157 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC) 158 dumb_ctrl |= CFG_INV_HSYNC; 159 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC) 160 dumb_ctrl |= CFG_INV_VSYNC; 161 162 if (dcrtc->dumb_ctrl != dumb_ctrl) { 163 dcrtc->dumb_ctrl = dumb_ctrl; 164 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL); 165 } 166 } 167 168 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, 169 int x, int y) 170 { 171 u32 addr = drm_fb_obj(fb)->dev_addr; 172 int num_planes = fb->format->num_planes; 173 int i; 174 175 if (num_planes > 3) 176 num_planes = 3; 177 178 for (i = 0; i < num_planes; i++) 179 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + 180 x * fb->format->cpp[i]; 181 for (; i < 3; i++) 182 addrs[i] = 0; 183 } 184 185 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, 186 int x, int y, struct armada_regs *regs, bool interlaced) 187 { 188 unsigned pitch = fb->pitches[0]; 189 u32 addrs[3], addr_odd, addr_even; 190 unsigned i = 0; 191 192 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n", 193 pitch, x, y, fb->format->cpp[0] * 8); 194 195 armada_drm_plane_calc_addrs(addrs, fb, x, y); 196 197 addr_odd = addr_even = addrs[0]; 198 199 if (interlaced) { 200 addr_even += pitch; 201 pitch *= 2; 202 } 203 204 /* write offset, base, and pitch */ 205 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0); 206 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1); 207 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH); 208 209 return i; 210 } 211 212 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, 213 struct drm_plane *plane) 214 { 215 struct armada_plane *dplane = drm_to_armada_plane(plane); 216 struct armada_plane_work *work = xchg(&dplane->work, NULL); 217 218 /* Handle any pending frame work. */ 219 if (work) { 220 work->fn(dcrtc, dplane, work); 221 drm_crtc_vblank_put(&dcrtc->crtc); 222 } 223 224 wake_up(&dplane->frame_wait); 225 } 226 227 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, 228 struct armada_plane *plane, struct armada_plane_work *work) 229 { 230 int ret; 231 232 ret = drm_crtc_vblank_get(&dcrtc->crtc); 233 if (ret) { 234 DRM_ERROR("failed to acquire vblank counter\n"); 235 return ret; 236 } 237 238 ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0; 239 if (ret) 240 drm_crtc_vblank_put(&dcrtc->crtc); 241 242 return ret; 243 } 244 245 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout) 246 { 247 return wait_event_timeout(plane->frame_wait, !plane->work, timeout); 248 } 249 250 struct armada_plane_work *armada_drm_plane_work_cancel( 251 struct armada_crtc *dcrtc, struct armada_plane *plane) 252 { 253 struct armada_plane_work *work = xchg(&plane->work, NULL); 254 255 if (work) 256 drm_crtc_vblank_put(&dcrtc->crtc); 257 258 return work; 259 } 260 261 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, 262 struct armada_frame_work *work) 263 { 264 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); 265 266 return armada_drm_plane_work_queue(dcrtc, plane, &work->work); 267 } 268 269 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, 270 struct armada_plane *plane, struct armada_plane_work *work) 271 { 272 struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); 273 struct drm_device *dev = dcrtc->crtc.dev; 274 unsigned long flags; 275 276 spin_lock_irqsave(&dcrtc->irq_lock, flags); 277 armada_drm_crtc_update_regs(dcrtc, fwork->regs); 278 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); 279 280 if (fwork->event) { 281 spin_lock_irqsave(&dev->event_lock, flags); 282 drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event); 283 spin_unlock_irqrestore(&dev->event_lock, flags); 284 } 285 286 /* Finally, queue the process-half of the cleanup. */ 287 __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb); 288 kfree(fwork); 289 } 290 291 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, 292 struct drm_framebuffer *fb, bool force) 293 { 294 struct armada_frame_work *work; 295 296 if (!fb) 297 return; 298 299 if (force) { 300 /* Display is disabled, so just drop the old fb */ 301 drm_framebuffer_unreference(fb); 302 return; 303 } 304 305 work = kmalloc(sizeof(*work), GFP_KERNEL); 306 if (work) { 307 int i = 0; 308 work->work.fn = armada_drm_crtc_complete_frame_work; 309 work->event = NULL; 310 work->old_fb = fb; 311 armada_reg_queue_end(work->regs, i); 312 313 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) 314 return; 315 316 kfree(work); 317 } 318 319 /* 320 * Oops - just drop the reference immediately and hope for 321 * the best. The worst that will happen is the buffer gets 322 * reused before it has finished being displayed. 323 */ 324 drm_framebuffer_unreference(fb); 325 } 326 327 static void armada_drm_vblank_off(struct armada_crtc *dcrtc) 328 { 329 /* 330 * Tell the DRM core that vblank IRQs aren't going to happen for 331 * a while. This cleans up any pending vblank events for us. 332 */ 333 drm_crtc_vblank_off(&dcrtc->crtc); 334 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); 335 } 336 337 /* The mode_config.mutex will be held for this call */ 338 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms) 339 { 340 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 341 342 if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) { 343 if (dpms_blanked(dpms)) 344 armada_drm_vblank_off(dcrtc); 345 else if (!IS_ERR(dcrtc->clk)) 346 WARN_ON(clk_prepare_enable(dcrtc->clk)); 347 dcrtc->dpms = dpms; 348 armada_drm_crtc_update(dcrtc); 349 if (!dpms_blanked(dpms)) 350 drm_crtc_vblank_on(&dcrtc->crtc); 351 else if (!IS_ERR(dcrtc->clk)) 352 clk_disable_unprepare(dcrtc->clk); 353 } else if (dcrtc->dpms != dpms) { 354 dcrtc->dpms = dpms; 355 } 356 } 357 358 /* 359 * Prepare for a mode set. Turn off overlay to ensure that we don't end 360 * up with the overlay size being bigger than the active screen size. 361 * We rely upon X refreshing this state after the mode set has completed. 362 * 363 * The mode_config.mutex will be held for this call 364 */ 365 static void armada_drm_crtc_prepare(struct drm_crtc *crtc) 366 { 367 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 368 struct drm_plane *plane; 369 370 /* 371 * If we have an overlay plane associated with this CRTC, disable 372 * it before the modeset to avoid its coordinates being outside 373 * the new mode parameters. 374 */ 375 plane = dcrtc->plane; 376 if (plane) 377 drm_plane_force_disable(plane); 378 } 379 380 /* The mode_config.mutex will be held for this call */ 381 static void armada_drm_crtc_commit(struct drm_crtc *crtc) 382 { 383 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 384 385 if (dcrtc->dpms != DRM_MODE_DPMS_ON) { 386 dcrtc->dpms = DRM_MODE_DPMS_ON; 387 armada_drm_crtc_update(dcrtc); 388 } 389 } 390 391 /* The mode_config.mutex will be held for this call */ 392 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc, 393 const struct drm_display_mode *mode, struct drm_display_mode *adj) 394 { 395 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 396 int ret; 397 398 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */ 399 if (!dcrtc->variant->has_spu_adv_reg && 400 adj->flags & DRM_MODE_FLAG_INTERLACE) 401 return false; 402 403 /* Check whether the display mode is possible */ 404 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); 405 if (ret) 406 return false; 407 408 return true; 409 } 410 411 /* These are locked by dev->vbl_lock */ 412 static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) 413 { 414 if (dcrtc->irq_ena & mask) { 415 dcrtc->irq_ena &= ~mask; 416 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); 417 } 418 } 419 420 static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) 421 { 422 if ((dcrtc->irq_ena & mask) != mask) { 423 dcrtc->irq_ena |= mask; 424 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); 425 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) 426 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); 427 } 428 } 429 430 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) 431 { 432 void __iomem *base = dcrtc->base; 433 struct drm_plane *ovl_plane; 434 435 if (stat & DMA_FF_UNDERFLOW) 436 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); 437 if (stat & GRA_FF_UNDERFLOW) 438 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); 439 440 if (stat & VSYNC_IRQ) 441 drm_crtc_handle_vblank(&dcrtc->crtc); 442 443 spin_lock(&dcrtc->irq_lock); 444 ovl_plane = dcrtc->plane; 445 if (ovl_plane) 446 armada_drm_plane_work_run(dcrtc, ovl_plane); 447 448 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { 449 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1; 450 uint32_t val; 451 452 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); 453 writel_relaxed(dcrtc->v[i].spu_v_h_total, 454 base + LCD_SPUT_V_H_TOTAL); 455 456 val = readl_relaxed(base + LCD_SPU_ADV_REG); 457 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN); 458 val |= dcrtc->v[i].spu_adv_reg; 459 writel_relaxed(val, base + LCD_SPU_ADV_REG); 460 } 461 462 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) { 463 writel_relaxed(dcrtc->cursor_hw_pos, 464 base + LCD_SPU_HWC_OVSA_HPXL_VLN); 465 writel_relaxed(dcrtc->cursor_hw_sz, 466 base + LCD_SPU_HWC_HPXL_VLN); 467 armada_updatel(CFG_HWC_ENA, 468 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA, 469 base + LCD_SPU_DMA_CTRL0); 470 dcrtc->cursor_update = false; 471 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); 472 } 473 474 spin_unlock(&dcrtc->irq_lock); 475 476 if (stat & GRA_FRAME_IRQ) 477 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); 478 } 479 480 static irqreturn_t armada_drm_irq(int irq, void *arg) 481 { 482 struct armada_crtc *dcrtc = arg; 483 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); 484 485 /* 486 * This is rediculous - rather than writing bits to clear, we 487 * have to set the actual status register value. This is racy. 488 */ 489 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); 490 491 trace_armada_drm_irq(&dcrtc->crtc, stat); 492 493 /* Mask out those interrupts we haven't enabled */ 494 v = stat & dcrtc->irq_ena; 495 496 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) { 497 armada_drm_crtc_irq(dcrtc, stat); 498 return IRQ_HANDLED; 499 } 500 return IRQ_NONE; 501 } 502 503 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) 504 { 505 struct drm_display_mode *adj = &dcrtc->crtc.mode; 506 uint32_t val = 0; 507 508 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709) 509 val |= CFG_CSC_YUV_CCIR709; 510 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO) 511 val |= CFG_CSC_RGB_STUDIO; 512 513 /* 514 * In auto mode, set the colorimetry, based upon the HDMI spec. 515 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use 516 * ITU601. It may be more appropriate to set this depending on 517 * the source - but what if the graphic frame is YUV and the 518 * video frame is RGB? 519 */ 520 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 && 521 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) || 522 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) { 523 if (dcrtc->csc_yuv_mode == CSC_AUTO) 524 val |= CFG_CSC_YUV_CCIR709; 525 } 526 527 /* 528 * We assume we're connected to a TV-like device, so the YUV->RGB 529 * conversion should produce a limited range. We should set this 530 * depending on the connectors attached to this CRTC, and what 531 * kind of device they report being connected. 532 */ 533 if (dcrtc->csc_rgb_mode == CSC_AUTO) 534 val |= CFG_CSC_RGB_STUDIO; 535 536 return val; 537 } 538 539 static void armada_drm_primary_set(struct drm_crtc *crtc, 540 struct drm_plane *plane, int x, int y) 541 { 542 struct armada_plane_state *state = &drm_to_armada_plane(plane)->state; 543 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 544 struct armada_regs regs[8]; 545 bool interlaced = dcrtc->interlaced; 546 unsigned i; 547 u32 ctrl0; 548 549 i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced); 550 551 armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN); 552 armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN); 553 armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN); 554 555 ctrl0 = state->ctrl0; 556 if (interlaced) 557 ctrl0 |= CFG_GRA_FTOGGLE; 558 559 armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT | 560 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | 561 CFG_SWAPYU | CFG_YUV2RGB) | 562 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE, 563 LCD_SPU_DMA_CTRL0); 564 armada_reg_queue_end(regs, i); 565 armada_drm_crtc_update_regs(dcrtc, regs); 566 } 567 568 /* The mode_config.mutex will be held for this call */ 569 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, 570 struct drm_display_mode *mode, struct drm_display_mode *adj, 571 int x, int y, struct drm_framebuffer *old_fb) 572 { 573 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 574 struct armada_regs regs[17]; 575 uint32_t lm, rm, tm, bm, val, sclk; 576 unsigned long flags; 577 unsigned i; 578 bool interlaced; 579 580 drm_framebuffer_reference(crtc->primary->fb); 581 582 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); 583 584 val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; 585 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); 586 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); 587 588 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) 589 val |= CFG_PALETTE_ENA; 590 591 drm_to_armada_plane(crtc->primary)->state.ctrl0 = val; 592 drm_to_armada_plane(crtc->primary)->state.src_hw = 593 drm_to_armada_plane(crtc->primary)->state.dst_hw = 594 adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; 595 drm_to_armada_plane(crtc->primary)->state.dst_yx = 0; 596 597 i = 0; 598 rm = adj->crtc_hsync_start - adj->crtc_hdisplay; 599 lm = adj->crtc_htotal - adj->crtc_hsync_end; 600 bm = adj->crtc_vsync_start - adj->crtc_vdisplay; 601 tm = adj->crtc_vtotal - adj->crtc_vsync_end; 602 603 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n", 604 adj->crtc_hdisplay, 605 adj->crtc_hsync_start, 606 adj->crtc_hsync_end, 607 adj->crtc_htotal, lm, rm); 608 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n", 609 adj->crtc_vdisplay, 610 adj->crtc_vsync_start, 611 adj->crtc_vsync_end, 612 adj->crtc_vtotal, tm, bm); 613 614 /* Wait for pending flips to complete */ 615 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), 616 MAX_SCHEDULE_TIMEOUT); 617 618 drm_crtc_vblank_off(crtc); 619 620 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA; 621 if (val != dcrtc->dumb_ctrl) { 622 dcrtc->dumb_ctrl = val; 623 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); 624 } 625 626 /* 627 * If we are blanked, we would have disabled the clock. Re-enable 628 * it so that compute_clock() does the right thing. 629 */ 630 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms)) 631 WARN_ON(clk_prepare_enable(dcrtc->clk)); 632 633 /* Now compute the divider for real */ 634 dcrtc->variant->compute_clock(dcrtc, adj, &sclk); 635 636 /* Ensure graphic fifo is enabled */ 637 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1); 638 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); 639 640 if (interlaced ^ dcrtc->interlaced) { 641 if (adj->flags & DRM_MODE_FLAG_INTERLACE) 642 drm_crtc_vblank_get(&dcrtc->crtc); 643 else 644 drm_crtc_vblank_put(&dcrtc->crtc); 645 dcrtc->interlaced = interlaced; 646 } 647 648 spin_lock_irqsave(&dcrtc->irq_lock, flags); 649 650 /* Even interlaced/progressive frame */ 651 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | 652 adj->crtc_htotal; 653 dcrtc->v[1].spu_v_porch = tm << 16 | bm; 654 val = adj->crtc_hsync_start; 655 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | 656 dcrtc->variant->spu_adv_reg; 657 658 if (interlaced) { 659 /* Odd interlaced frame */ 660 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + 661 (1 << 16); 662 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; 663 val = adj->crtc_hsync_start - adj->crtc_htotal / 2; 664 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | 665 dcrtc->variant->spu_adv_reg; 666 } else { 667 dcrtc->v[0] = dcrtc->v[1]; 668 } 669 670 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; 671 672 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); 673 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); 674 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); 675 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, 676 LCD_SPUT_V_H_TOTAL); 677 678 if (dcrtc->variant->has_spu_adv_reg) { 679 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, 680 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | 681 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG); 682 } 683 684 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; 685 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); 686 687 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc); 688 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL); 689 armada_reg_queue_end(regs, i); 690 691 armada_drm_crtc_update_regs(dcrtc, regs); 692 693 armada_drm_primary_set(crtc, crtc->primary, x, y); 694 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); 695 696 armada_drm_crtc_update(dcrtc); 697 698 drm_crtc_vblank_on(crtc); 699 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); 700 701 return 0; 702 } 703 704 /* The mode_config.mutex will be held for this call */ 705 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 706 struct drm_framebuffer *old_fb) 707 { 708 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 709 struct armada_regs regs[4]; 710 unsigned i; 711 712 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs, 713 dcrtc->interlaced); 714 armada_reg_queue_end(regs, i); 715 716 /* Wait for pending flips to complete */ 717 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), 718 MAX_SCHEDULE_TIMEOUT); 719 720 /* Take a reference to the new fb as we're using it */ 721 drm_framebuffer_reference(crtc->primary->fb); 722 723 /* Update the base in the CRTC */ 724 armada_drm_crtc_update_regs(dcrtc, regs); 725 726 /* Drop our previously held reference */ 727 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); 728 729 return 0; 730 } 731 732 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, 733 struct drm_plane *plane) 734 { 735 u32 sram_para1, dma_ctrl0_mask; 736 737 /* 738 * Drop our reference on any framebuffer attached to this plane. 739 * We don't need to NULL this out as drm_plane_force_disable(), 740 * and __setplane_internal() will do so for an overlay plane, and 741 * __drm_helper_disable_unused_functions() will do so for the 742 * primary plane. 743 */ 744 if (plane->fb) 745 drm_framebuffer_unreference(plane->fb); 746 747 /* Power down the Y/U/V FIFOs */ 748 sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; 749 750 /* Power down most RAMs and FIFOs if this is the primary plane */ 751 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 752 sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | 753 CFG_PDWN32x32 | CFG_PDWN64x66; 754 dma_ctrl0_mask = CFG_GRA_ENA; 755 } else { 756 dma_ctrl0_mask = CFG_DMA_ENA; 757 } 758 759 spin_lock_irq(&dcrtc->irq_lock); 760 armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); 761 spin_unlock_irq(&dcrtc->irq_lock); 762 763 armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); 764 } 765 766 /* The mode_config.mutex will be held for this call */ 767 static void armada_drm_crtc_disable(struct drm_crtc *crtc) 768 { 769 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 770 771 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 772 armada_drm_crtc_plane_disable(dcrtc, crtc->primary); 773 } 774 775 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = { 776 .dpms = armada_drm_crtc_dpms, 777 .prepare = armada_drm_crtc_prepare, 778 .commit = armada_drm_crtc_commit, 779 .mode_fixup = armada_drm_crtc_mode_fixup, 780 .mode_set = armada_drm_crtc_mode_set, 781 .mode_set_base = armada_drm_crtc_mode_set_base, 782 .disable = armada_drm_crtc_disable, 783 }; 784 785 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, 786 unsigned stride, unsigned width, unsigned height) 787 { 788 uint32_t addr; 789 unsigned y; 790 791 addr = SRAM_HWC32_RAM1; 792 for (y = 0; y < height; y++) { 793 uint32_t *p = &pix[y * stride]; 794 unsigned x; 795 796 for (x = 0; x < width; x++, p++) { 797 uint32_t val = *p; 798 799 val = (val & 0xff00ff00) | 800 (val & 0x000000ff) << 16 | 801 (val & 0x00ff0000) >> 16; 802 803 writel_relaxed(val, 804 base + LCD_SPU_SRAM_WRDAT); 805 writel_relaxed(addr | SRAM_WRITE, 806 base + LCD_SPU_SRAM_CTRL); 807 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); 808 addr += 1; 809 if ((addr & 0x00ff) == 0) 810 addr += 0xf00; 811 if ((addr & 0x30ff) == 0) 812 addr = SRAM_HWC32_RAM2; 813 } 814 } 815 } 816 817 static void armada_drm_crtc_cursor_tran(void __iomem *base) 818 { 819 unsigned addr; 820 821 for (addr = 0; addr < 256; addr++) { 822 /* write the default value */ 823 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT); 824 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN, 825 base + LCD_SPU_SRAM_CTRL); 826 } 827 } 828 829 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) 830 { 831 uint32_t xoff, xscr, w = dcrtc->cursor_w, s; 832 uint32_t yoff, yscr, h = dcrtc->cursor_h; 833 uint32_t para1; 834 835 /* 836 * Calculate the visible width and height of the cursor, 837 * screen position, and the position in the cursor bitmap. 838 */ 839 if (dcrtc->cursor_x < 0) { 840 xoff = -dcrtc->cursor_x; 841 xscr = 0; 842 w -= min(xoff, w); 843 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { 844 xoff = 0; 845 xscr = dcrtc->cursor_x; 846 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); 847 } else { 848 xoff = 0; 849 xscr = dcrtc->cursor_x; 850 } 851 852 if (dcrtc->cursor_y < 0) { 853 yoff = -dcrtc->cursor_y; 854 yscr = 0; 855 h -= min(yoff, h); 856 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { 857 yoff = 0; 858 yscr = dcrtc->cursor_y; 859 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); 860 } else { 861 yoff = 0; 862 yscr = dcrtc->cursor_y; 863 } 864 865 /* On interlaced modes, the vertical cursor size must be halved */ 866 s = dcrtc->cursor_w; 867 if (dcrtc->interlaced) { 868 s *= 2; 869 yscr /= 2; 870 h /= 2; 871 } 872 873 if (!dcrtc->cursor_obj || !h || !w) { 874 spin_lock_irq(&dcrtc->irq_lock); 875 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); 876 dcrtc->cursor_update = false; 877 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); 878 spin_unlock_irq(&dcrtc->irq_lock); 879 return 0; 880 } 881 882 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); 883 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32, 884 dcrtc->base + LCD_SPU_SRAM_PARA1); 885 886 /* 887 * Initialize the transparency if the SRAM was powered down. 888 * We must also reload the cursor data as well. 889 */ 890 if (!(para1 & CFG_CSB_256x32)) { 891 armada_drm_crtc_cursor_tran(dcrtc->base); 892 reload = true; 893 } 894 895 if (dcrtc->cursor_hw_sz != (h << 16 | w)) { 896 spin_lock_irq(&dcrtc->irq_lock); 897 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); 898 dcrtc->cursor_update = false; 899 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); 900 spin_unlock_irq(&dcrtc->irq_lock); 901 reload = true; 902 } 903 if (reload) { 904 struct armada_gem_object *obj = dcrtc->cursor_obj; 905 uint32_t *pix; 906 /* Set the top-left corner of the cursor image */ 907 pix = obj->addr; 908 pix += yoff * s + xoff; 909 armada_load_cursor_argb(dcrtc->base, pix, s, w, h); 910 } 911 912 /* Reload the cursor position, size and enable in the IRQ handler */ 913 spin_lock_irq(&dcrtc->irq_lock); 914 dcrtc->cursor_hw_pos = yscr << 16 | xscr; 915 dcrtc->cursor_hw_sz = h << 16 | w; 916 dcrtc->cursor_update = true; 917 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); 918 spin_unlock_irq(&dcrtc->irq_lock); 919 920 return 0; 921 } 922 923 static void cursor_update(void *data) 924 { 925 armada_drm_crtc_cursor_update(data, true); 926 } 927 928 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc, 929 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h) 930 { 931 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 932 struct armada_gem_object *obj = NULL; 933 int ret; 934 935 /* If no cursor support, replicate drm's return value */ 936 if (!dcrtc->variant->has_spu_adv_reg) 937 return -ENXIO; 938 939 if (handle && w > 0 && h > 0) { 940 /* maximum size is 64x32 or 32x64 */ 941 if (w > 64 || h > 64 || (w > 32 && h > 32)) 942 return -ENOMEM; 943 944 obj = armada_gem_object_lookup(file, handle); 945 if (!obj) 946 return -ENOENT; 947 948 /* Must be a kernel-mapped object */ 949 if (!obj->addr) { 950 drm_gem_object_unreference_unlocked(&obj->obj); 951 return -EINVAL; 952 } 953 954 if (obj->obj.size < w * h * 4) { 955 DRM_ERROR("buffer is too small\n"); 956 drm_gem_object_unreference_unlocked(&obj->obj); 957 return -ENOMEM; 958 } 959 } 960 961 if (dcrtc->cursor_obj) { 962 dcrtc->cursor_obj->update = NULL; 963 dcrtc->cursor_obj->update_data = NULL; 964 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj); 965 } 966 dcrtc->cursor_obj = obj; 967 dcrtc->cursor_w = w; 968 dcrtc->cursor_h = h; 969 ret = armada_drm_crtc_cursor_update(dcrtc, true); 970 if (obj) { 971 obj->update_data = dcrtc; 972 obj->update = cursor_update; 973 } 974 975 return ret; 976 } 977 978 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 979 { 980 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 981 int ret; 982 983 /* If no cursor support, replicate drm's return value */ 984 if (!dcrtc->variant->has_spu_adv_reg) 985 return -EFAULT; 986 987 dcrtc->cursor_x = x; 988 dcrtc->cursor_y = y; 989 ret = armada_drm_crtc_cursor_update(dcrtc, false); 990 991 return ret; 992 } 993 994 static void armada_drm_crtc_destroy(struct drm_crtc *crtc) 995 { 996 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 997 struct armada_private *priv = crtc->dev->dev_private; 998 999 if (dcrtc->cursor_obj) 1000 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj); 1001 1002 priv->dcrtc[dcrtc->num] = NULL; 1003 drm_crtc_cleanup(&dcrtc->crtc); 1004 1005 if (!IS_ERR(dcrtc->clk)) 1006 clk_disable_unprepare(dcrtc->clk); 1007 1008 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); 1009 1010 of_node_put(dcrtc->crtc.port); 1011 1012 kfree(dcrtc); 1013 } 1014 1015 /* 1016 * The mode_config lock is held here, to prevent races between this 1017 * and a mode_set. 1018 */ 1019 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, 1020 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags, 1021 struct drm_modeset_acquire_ctx *ctx) 1022 { 1023 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 1024 struct armada_frame_work *work; 1025 unsigned i; 1026 int ret; 1027 1028 /* We don't support changing the pixel format */ 1029 if (fb->format != crtc->primary->fb->format) 1030 return -EINVAL; 1031 1032 work = kmalloc(sizeof(*work), GFP_KERNEL); 1033 if (!work) 1034 return -ENOMEM; 1035 1036 work->work.fn = armada_drm_crtc_complete_frame_work; 1037 work->event = event; 1038 work->old_fb = dcrtc->crtc.primary->fb; 1039 1040 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs, 1041 dcrtc->interlaced); 1042 armada_reg_queue_end(work->regs, i); 1043 1044 /* 1045 * Ensure that we hold a reference on the new framebuffer. 1046 * This has to match the behaviour in mode_set. 1047 */ 1048 drm_framebuffer_reference(fb); 1049 1050 ret = armada_drm_crtc_queue_frame_work(dcrtc, work); 1051 if (ret) { 1052 /* Undo our reference above */ 1053 drm_framebuffer_unreference(fb); 1054 kfree(work); 1055 return ret; 1056 } 1057 1058 /* 1059 * Don't take a reference on the new framebuffer; 1060 * drm_mode_page_flip_ioctl() has already grabbed a reference and 1061 * will _not_ drop that reference on successful return from this 1062 * function. Simply mark this new framebuffer as the current one. 1063 */ 1064 dcrtc->crtc.primary->fb = fb; 1065 1066 /* 1067 * Finally, if the display is blanked, we won't receive an 1068 * interrupt, so complete it now. 1069 */ 1070 if (dpms_blanked(dcrtc->dpms)) 1071 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); 1072 1073 return 0; 1074 } 1075 1076 static int 1077 armada_drm_crtc_set_property(struct drm_crtc *crtc, 1078 struct drm_property *property, uint64_t val) 1079 { 1080 struct armada_private *priv = crtc->dev->dev_private; 1081 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 1082 bool update_csc = false; 1083 1084 if (property == priv->csc_yuv_prop) { 1085 dcrtc->csc_yuv_mode = val; 1086 update_csc = true; 1087 } else if (property == priv->csc_rgb_prop) { 1088 dcrtc->csc_rgb_mode = val; 1089 update_csc = true; 1090 } 1091 1092 if (update_csc) { 1093 uint32_t val; 1094 1095 val = dcrtc->spu_iopad_ctrl | 1096 armada_drm_crtc_calculate_csc(dcrtc); 1097 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL); 1098 } 1099 1100 return 0; 1101 } 1102 1103 /* These are called under the vbl_lock. */ 1104 static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc) 1105 { 1106 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 1107 1108 armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA); 1109 return 0; 1110 } 1111 1112 static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc) 1113 { 1114 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 1115 1116 armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA); 1117 } 1118 1119 static const struct drm_crtc_funcs armada_crtc_funcs = { 1120 .cursor_set = armada_drm_crtc_cursor_set, 1121 .cursor_move = armada_drm_crtc_cursor_move, 1122 .destroy = armada_drm_crtc_destroy, 1123 .set_config = drm_crtc_helper_set_config, 1124 .page_flip = armada_drm_crtc_page_flip, 1125 .set_property = armada_drm_crtc_set_property, 1126 .enable_vblank = armada_drm_crtc_enable_vblank, 1127 .disable_vblank = armada_drm_crtc_disable_vblank, 1128 }; 1129 1130 static const struct drm_plane_funcs armada_primary_plane_funcs = { 1131 .update_plane = drm_primary_helper_update, 1132 .disable_plane = drm_primary_helper_disable, 1133 .destroy = drm_primary_helper_destroy, 1134 }; 1135 1136 int armada_drm_plane_init(struct armada_plane *plane) 1137 { 1138 init_waitqueue_head(&plane->frame_wait); 1139 1140 return 0; 1141 } 1142 1143 static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = { 1144 { CSC_AUTO, "Auto" }, 1145 { CSC_YUV_CCIR601, "CCIR601" }, 1146 { CSC_YUV_CCIR709, "CCIR709" }, 1147 }; 1148 1149 static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = { 1150 { CSC_AUTO, "Auto" }, 1151 { CSC_RGB_COMPUTER, "Computer system" }, 1152 { CSC_RGB_STUDIO, "Studio" }, 1153 }; 1154 1155 static int armada_drm_crtc_create_properties(struct drm_device *dev) 1156 { 1157 struct armada_private *priv = dev->dev_private; 1158 1159 if (priv->csc_yuv_prop) 1160 return 0; 1161 1162 priv->csc_yuv_prop = drm_property_create_enum(dev, 0, 1163 "CSC_YUV", armada_drm_csc_yuv_enum_list, 1164 ARRAY_SIZE(armada_drm_csc_yuv_enum_list)); 1165 priv->csc_rgb_prop = drm_property_create_enum(dev, 0, 1166 "CSC_RGB", armada_drm_csc_rgb_enum_list, 1167 ARRAY_SIZE(armada_drm_csc_rgb_enum_list)); 1168 1169 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop) 1170 return -ENOMEM; 1171 1172 return 0; 1173 } 1174 1175 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, 1176 struct resource *res, int irq, const struct armada_variant *variant, 1177 struct device_node *port) 1178 { 1179 struct armada_private *priv = drm->dev_private; 1180 struct armada_crtc *dcrtc; 1181 struct armada_plane *primary; 1182 void __iomem *base; 1183 int ret; 1184 1185 ret = armada_drm_crtc_create_properties(drm); 1186 if (ret) 1187 return ret; 1188 1189 base = devm_ioremap_resource(dev, res); 1190 if (IS_ERR(base)) 1191 return PTR_ERR(base); 1192 1193 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); 1194 if (!dcrtc) { 1195 DRM_ERROR("failed to allocate Armada crtc\n"); 1196 return -ENOMEM; 1197 } 1198 1199 if (dev != drm->dev) 1200 dev_set_drvdata(dev, dcrtc); 1201 1202 dcrtc->variant = variant; 1203 dcrtc->base = base; 1204 dcrtc->num = drm->mode_config.num_crtc; 1205 dcrtc->clk = ERR_PTR(-EINVAL); 1206 dcrtc->csc_yuv_mode = CSC_AUTO; 1207 dcrtc->csc_rgb_mode = CSC_AUTO; 1208 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; 1209 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; 1210 spin_lock_init(&dcrtc->irq_lock); 1211 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; 1212 1213 /* Initialize some registers which we don't otherwise set */ 1214 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); 1215 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); 1216 writel_relaxed(dcrtc->spu_iopad_ctrl, 1217 dcrtc->base + LCD_SPU_IOPAD_CONTROL); 1218 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); 1219 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | 1220 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | 1221 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); 1222 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); 1223 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); 1224 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); 1225 1226 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc", 1227 dcrtc); 1228 if (ret < 0) { 1229 kfree(dcrtc); 1230 return ret; 1231 } 1232 1233 if (dcrtc->variant->init) { 1234 ret = dcrtc->variant->init(dcrtc, dev); 1235 if (ret) { 1236 kfree(dcrtc); 1237 return ret; 1238 } 1239 } 1240 1241 /* Ensure AXI pipeline is enabled */ 1242 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); 1243 1244 priv->dcrtc[dcrtc->num] = dcrtc; 1245 1246 dcrtc->crtc.port = port; 1247 1248 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 1249 if (!primary) 1250 return -ENOMEM; 1251 1252 ret = armada_drm_plane_init(primary); 1253 if (ret) { 1254 kfree(primary); 1255 return ret; 1256 } 1257 1258 ret = drm_universal_plane_init(drm, &primary->base, 0, 1259 &armada_primary_plane_funcs, 1260 armada_primary_formats, 1261 ARRAY_SIZE(armada_primary_formats), 1262 NULL, 1263 DRM_PLANE_TYPE_PRIMARY, NULL); 1264 if (ret) { 1265 kfree(primary); 1266 return ret; 1267 } 1268 1269 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL, 1270 &armada_crtc_funcs, NULL); 1271 if (ret) 1272 goto err_crtc_init; 1273 1274 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); 1275 1276 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop, 1277 dcrtc->csc_yuv_mode); 1278 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop, 1279 dcrtc->csc_rgb_mode); 1280 1281 return armada_overlay_plane_create(drm, 1 << dcrtc->num); 1282 1283 err_crtc_init: 1284 primary->base.funcs->destroy(&primary->base); 1285 return ret; 1286 } 1287 1288 static int 1289 armada_lcd_bind(struct device *dev, struct device *master, void *data) 1290 { 1291 struct platform_device *pdev = to_platform_device(dev); 1292 struct drm_device *drm = data; 1293 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1294 int irq = platform_get_irq(pdev, 0); 1295 const struct armada_variant *variant; 1296 struct device_node *port = NULL; 1297 1298 if (irq < 0) 1299 return irq; 1300 1301 if (!dev->of_node) { 1302 const struct platform_device_id *id; 1303 1304 id = platform_get_device_id(pdev); 1305 if (!id) 1306 return -ENXIO; 1307 1308 variant = (const struct armada_variant *)id->driver_data; 1309 } else { 1310 const struct of_device_id *match; 1311 struct device_node *np, *parent = dev->of_node; 1312 1313 match = of_match_device(dev->driver->of_match_table, dev); 1314 if (!match) 1315 return -ENXIO; 1316 1317 np = of_get_child_by_name(parent, "ports"); 1318 if (np) 1319 parent = np; 1320 port = of_get_child_by_name(parent, "port"); 1321 of_node_put(np); 1322 if (!port) { 1323 dev_err(dev, "no port node found in %pOF\n", parent); 1324 return -ENXIO; 1325 } 1326 1327 variant = match->data; 1328 } 1329 1330 return armada_drm_crtc_create(drm, dev, res, irq, variant, port); 1331 } 1332 1333 static void 1334 armada_lcd_unbind(struct device *dev, struct device *master, void *data) 1335 { 1336 struct armada_crtc *dcrtc = dev_get_drvdata(dev); 1337 1338 armada_drm_crtc_destroy(&dcrtc->crtc); 1339 } 1340 1341 static const struct component_ops armada_lcd_ops = { 1342 .bind = armada_lcd_bind, 1343 .unbind = armada_lcd_unbind, 1344 }; 1345 1346 static int armada_lcd_probe(struct platform_device *pdev) 1347 { 1348 return component_add(&pdev->dev, &armada_lcd_ops); 1349 } 1350 1351 static int armada_lcd_remove(struct platform_device *pdev) 1352 { 1353 component_del(&pdev->dev, &armada_lcd_ops); 1354 return 0; 1355 } 1356 1357 static const struct of_device_id armada_lcd_of_match[] = { 1358 { 1359 .compatible = "marvell,dove-lcd", 1360 .data = &armada510_ops, 1361 }, 1362 {} 1363 }; 1364 MODULE_DEVICE_TABLE(of, armada_lcd_of_match); 1365 1366 static const struct platform_device_id armada_lcd_platform_ids[] = { 1367 { 1368 .name = "armada-lcd", 1369 .driver_data = (unsigned long)&armada510_ops, 1370 }, { 1371 .name = "armada-510-lcd", 1372 .driver_data = (unsigned long)&armada510_ops, 1373 }, 1374 { }, 1375 }; 1376 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids); 1377 1378 struct platform_driver armada_lcd_platform_driver = { 1379 .probe = armada_lcd_probe, 1380 .remove = armada_lcd_remove, 1381 .driver = { 1382 .name = "armada-lcd", 1383 .owner = THIS_MODULE, 1384 .of_match_table = armada_lcd_of_match, 1385 }, 1386 .id_table = armada_lcd_platform_ids, 1387 }; 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