1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP500/DP550/DP650 registers definition. 11 */ 12 13 #ifndef __MALIDP_REGS_H__ 14 #define __MALIDP_REGS_H__ 15 16 /* 17 * abbreviations used: 18 * - DC - display core (general settings) 19 * - DE - display engine 20 * - SE - scaling engine 21 */ 22 23 /* interrupt bit masks */ 24 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0) 25 26 #define MALIDP500_DE_IRQ_AXI_ERR (1 << 4) 27 #define MALIDP500_DE_IRQ_VSYNC (1 << 5) 28 #define MALIDP500_DE_IRQ_PROG_LINE (1 << 6) 29 #define MALIDP500_DE_IRQ_SATURATION (1 << 7) 30 #define MALIDP500_DE_IRQ_CONF_VALID (1 << 8) 31 #define MALIDP500_DE_IRQ_CONF_MODE (1 << 11) 32 #define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17) 33 #define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18) 34 #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19) 35 #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24) 36 #define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28) 37 #define MALIDP500_DE_IRQ_GLOBAL (1 << 31) 38 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0) 39 #define MALIDP500_SE_IRQ_CONF_VALID (1 << 4) 40 #define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5) 41 #define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8) 42 #define MALIDP500_SE_IRQ_OVERRUN (1 << 9) 43 #define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12) 44 #define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13) 45 #define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17) 46 #define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18) 47 #define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28) 48 #define MALIDP500_SE_IRQ_GLOBAL (1 << 31) 49 50 #define MALIDP550_DE_IRQ_SATURATION (1 << 8) 51 #define MALIDP550_DE_IRQ_VSYNC (1 << 12) 52 #define MALIDP550_DE_IRQ_PROG_LINE (1 << 13) 53 #define MALIDP550_DE_IRQ_AXI_ERR (1 << 16) 54 #define MALIDP550_SE_IRQ_EOW (1 << 0) 55 #define MALIDP550_SE_IRQ_AXI_ERR (1 << 16) 56 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0) 57 #define MALIDP550_DC_IRQ_CONF_MODE (1 << 4) 58 #define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16) 59 #define MALIDP550_DC_IRQ_DE (1 << 20) 60 #define MALIDP550_DC_IRQ_SE (1 << 24) 61 62 #define MALIDP650_DE_IRQ_DRIFT (1 << 4) 63 64 /* bit masks that are common between products */ 65 #define MALIDP_CFG_VALID (1 << 0) 66 #define MALIDP_DISP_FUNC_GAMMA (1 << 0) 67 #define MALIDP_DISP_FUNC_CADJ (1 << 4) 68 #define MALIDP_DISP_FUNC_ILACED (1 << 8) 69 70 /* register offsets for IRQ management */ 71 #define MALIDP_REG_STATUS 0x00000 72 #define MALIDP_REG_SETIRQ 0x00004 73 #define MALIDP_REG_MASKIRQ 0x00008 74 #define MALIDP_REG_CLEARIRQ 0x0000c 75 76 /* register offsets */ 77 #define MALIDP_DE_CORE_ID 0x00018 78 #define MALIDP_DE_DISPLAY_FUNC 0x00020 79 80 /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */ 81 #define MALIDP_DE_H_TIMINGS 0x0 82 #define MALIDP_DE_V_TIMINGS 0x4 83 #define MALIDP_DE_SYNC_WIDTH 0x8 84 #define MALIDP_DE_HV_ACTIVE 0xc 85 86 /* Stride register offsets relative to Lx_BASE */ 87 #define MALIDP_DE_LG_STRIDE 0x18 88 #define MALIDP_DE_LV_STRIDE0 0x18 89 #define MALIDP550_DE_LS_R1_STRIDE 0x28 90 91 /* macros to set values into registers */ 92 #define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0) 93 #define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16) 94 #define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0) 95 #define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0) 96 #define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16) 97 #define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0) 98 #define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16) 99 #define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0) 100 #define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16) 101 102 #define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16) 103 104 /* register offsets relative to MALIDP5x0_COEFFS_BASE */ 105 #define MALIDP_COLOR_ADJ_COEF 0x00000 106 #define MALIDP_COEF_TABLE_ADDR 0x00030 107 #define MALIDP_COEF_TABLE_DATA 0x00034 108 109 /* Scaling engine registers and masks. */ 110 #define MALIDP_SE_SCALING_EN (1 << 0) 111 #define MALIDP_SE_ALPHA_EN (1 << 1) 112 #define MALIDP_SE_ENH_MASK 3 113 #define MALIDP_SE_ENH(x) (((x) & MALIDP_SE_ENH_MASK) << 2) 114 #define MALIDP_SE_RGBO_IF_EN (1 << 4) 115 #define MALIDP550_SE_CTL_SEL_MASK 7 116 #define MALIDP550_SE_CTL_VCSEL(x) \ 117 (((x) & MALIDP550_SE_CTL_SEL_MASK) << 20) 118 #define MALIDP550_SE_CTL_HCSEL(x) \ 119 (((x) & MALIDP550_SE_CTL_SEL_MASK) << 16) 120 121 /* Blocks with offsets from SE_CONTROL register. */ 122 #define MALIDP_SE_LAYER_CONTROL 0x14 123 #define MALIDP_SE_L0_IN_SIZE 0x00 124 #define MALIDP_SE_L0_OUT_SIZE 0x04 125 #define MALIDP_SE_SET_V_SIZE(x) (((x) & 0x1fff) << 16) 126 #define MALIDP_SE_SET_H_SIZE(x) (((x) & 0x1fff) << 0) 127 #define MALIDP_SE_SCALING_CONTROL 0x24 128 #define MALIDP_SE_H_INIT_PH 0x00 129 #define MALIDP_SE_H_DELTA_PH 0x04 130 #define MALIDP_SE_V_INIT_PH 0x08 131 #define MALIDP_SE_V_DELTA_PH 0x0c 132 #define MALIDP_SE_COEFFTAB_ADDR 0x10 133 #define MALIDP_SE_COEFFTAB_ADDR_MASK 0x7f 134 #define MALIDP_SE_V_COEFFTAB (1 << 8) 135 #define MALIDP_SE_H_COEFFTAB (1 << 9) 136 #define MALIDP_SE_SET_V_COEFFTAB_ADDR(x) \ 137 (MALIDP_SE_V_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) 138 #define MALIDP_SE_SET_H_COEFFTAB_ADDR(x) \ 139 (MALIDP_SE_H_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) 140 #define MALIDP_SE_COEFFTAB_DATA 0x14 141 #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff 142 #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ 143 ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) 144 /* Enhance coeffents reigster offset */ 145 #define MALIDP_SE_IMAGE_ENH 0x3C 146 /* ENH_LIMITS offset 0x0 */ 147 #define MALIDP_SE_ENH_LOW_LEVEL 24 148 #define MALIDP_SE_ENH_HIGH_LEVEL 63 149 #define MALIDP_SE_ENH_LIMIT_MASK 0xfff 150 #define MALIDP_SE_SET_ENH_LIMIT_LOW(x) \ 151 ((x) & MALIDP_SE_ENH_LIMIT_MASK) 152 #define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \ 153 (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16) 154 #define MALIDP_SE_ENH_COEFF0 0x04 155 156 /* register offsets and bits specific to DP500 */ 157 #define MALIDP500_ADDR_SPACE_SIZE 0x01000 158 #define MALIDP500_DC_BASE 0x00000 159 #define MALIDP500_DC_CONTROL 0x0000c 160 #define MALIDP500_DC_CONFIG_REQ (1 << 17) 161 #define MALIDP500_HSYNCPOL (1 << 20) 162 #define MALIDP500_VSYNCPOL (1 << 21) 163 #define MALIDP500_DC_CLEAR_MASK 0x300fff 164 #define MALIDP500_DE_LINE_COUNTER 0x00010 165 #define MALIDP500_DE_AXI_CONTROL 0x00014 166 #define MALIDP500_DE_SECURE_CTRL 0x0001c 167 #define MALIDP500_DE_CHROMA_KEY 0x00024 168 #define MALIDP500_TIMINGS_BASE 0x00028 169 170 #define MALIDP500_CONFIG_3D 0x00038 171 #define MALIDP500_BGND_COLOR 0x0003c 172 #define MALIDP500_OUTPUT_DEPTH 0x00044 173 #define MALIDP500_YUV_RGB_COEF 0x00048 174 #define MALIDP500_COLOR_ADJ_COEF 0x00078 175 #define MALIDP500_COEF_TABLE_ADDR 0x000a8 176 #define MALIDP500_COEF_TABLE_DATA 0x000ac 177 178 /* 179 * The YUV2RGB coefficients on the DP500 are not in the video layer's register 180 * block. They belong in a separate block above the layer's registers, hence 181 * the negative offset. 182 */ 183 #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8)) 184 /* 185 * To match DP550/650, the start of the coeffs registers is 186 * at COLORADJ_COEFF0 instead of at YUV_RGB_COEF1. 187 */ 188 #define MALIDP500_COEFFS_BASE 0x00078 189 #define MALIDP500_DE_LV_BASE 0x00100 190 #define MALIDP500_DE_LV_PTR_BASE 0x00124 191 #define MALIDP500_DE_LG1_BASE 0x00200 192 #define MALIDP500_DE_LG1_PTR_BASE 0x0021c 193 #define MALIDP500_DE_LG2_BASE 0x00300 194 #define MALIDP500_DE_LG2_PTR_BASE 0x0031c 195 #define MALIDP500_SE_BASE 0x00c00 196 #define MALIDP500_SE_CONTROL 0x00c0c 197 #define MALIDP500_SE_PTR_BASE 0x00e0c 198 #define MALIDP500_DC_IRQ_BASE 0x00f00 199 #define MALIDP500_CONFIG_VALID 0x00f00 200 #define MALIDP500_CONFIG_ID 0x00fd4 201 202 /* register offsets and bits specific to DP550/DP650 */ 203 #define MALIDP550_ADDR_SPACE_SIZE 0x10000 204 #define MALIDP550_DE_CONTROL 0x00010 205 #define MALIDP550_DE_LINE_COUNTER 0x00014 206 #define MALIDP550_DE_AXI_CONTROL 0x00018 207 #define MALIDP550_DE_QOS 0x0001c 208 #define MALIDP550_TIMINGS_BASE 0x00030 209 #define MALIDP550_HSYNCPOL (1 << 12) 210 #define MALIDP550_VSYNCPOL (1 << 28) 211 212 #define MALIDP550_DE_DISP_SIDEBAND 0x00040 213 #define MALIDP550_DE_BGND_COLOR 0x00044 214 #define MALIDP550_DE_OUTPUT_DEPTH 0x0004c 215 #define MALIDP550_COEFFS_BASE 0x00050 216 #define MALIDP550_DE_LV1_BASE 0x00100 217 #define MALIDP550_DE_LV1_PTR_BASE 0x00124 218 #define MALIDP550_DE_LV2_BASE 0x00200 219 #define MALIDP550_DE_LV2_PTR_BASE 0x00224 220 #define MALIDP550_DE_LG_BASE 0x00300 221 #define MALIDP550_DE_LG_PTR_BASE 0x0031c 222 #define MALIDP550_DE_LS_BASE 0x00400 223 #define MALIDP550_DE_LS_PTR_BASE 0x0042c 224 #define MALIDP550_DE_PERF_BASE 0x00500 225 #define MALIDP550_SE_BASE 0x08000 226 #define MALIDP550_SE_CONTROL 0x08010 227 #define MALIDP550_DC_BASE 0x0c000 228 #define MALIDP550_DC_CONTROL 0x0c010 229 #define MALIDP550_DC_CONFIG_REQ (1 << 16) 230 #define MALIDP550_CONFIG_VALID 0x0c014 231 #define MALIDP550_CONFIG_ID 0x0ffd4 232 233 /* 234 * Starting with DP550 the register map blocks has been standardised to the 235 * following layout: 236 * 237 * Offset Block registers 238 * 0x00000 Display Engine 239 * 0x08000 Scaling Engine 240 * 0x0c000 Display Core 241 * 0x10000 Secure control 242 * 243 * The old DP500 IP mixes some DC with the DE registers, hence the need 244 * for a mapping structure. 245 */ 246 247 #endif /* __MALIDP_REGS_H__ */ 248