xref: /openbmc/linux/drivers/gpu/drm/arm/malidp_regs.h (revision 151f4e2b)
1 /*
2  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
3  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4  *
5  * This program is free software and is provided to you under the terms of the
6  * GNU General Public License version 2 as published by the Free Software
7  * Foundation, and any use by you of this program is subject to the terms
8  * of such GNU licence.
9  *
10  * ARM Mali DP500/DP550/DP650 registers definition.
11  */
12 
13 #ifndef __MALIDP_REGS_H__
14 #define __MALIDP_REGS_H__
15 
16 /*
17  * abbreviations used:
18  *    - DC - display core (general settings)
19  *    - DE - display engine
20  *    - SE - scaling engine
21  */
22 
23 /* interrupt bit masks */
24 #define MALIDP_DE_IRQ_UNDERRUN			(1 << 0)
25 
26 #define MALIDP500_DE_IRQ_AXI_ERR		(1 << 4)
27 #define MALIDP500_DE_IRQ_VSYNC			(1 << 5)
28 #define MALIDP500_DE_IRQ_PROG_LINE		(1 << 6)
29 #define MALIDP500_DE_IRQ_SATURATION		(1 << 7)
30 #define MALIDP500_DE_IRQ_CONF_VALID		(1 << 8)
31 #define MALIDP500_DE_IRQ_CONF_MODE		(1 << 11)
32 #define MALIDP500_DE_IRQ_CONF_ACTIVE		(1 << 17)
33 #define MALIDP500_DE_IRQ_PM_ACTIVE		(1 << 18)
34 #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE	(1 << 19)
35 #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE	(1 << 24)
36 #define MALIDP500_DE_IRQ_AXI_BUSY		(1 << 28)
37 #define MALIDP500_DE_IRQ_GLOBAL			(1 << 31)
38 #define MALIDP500_SE_IRQ_CONF_MODE		(1 << 0)
39 #define MALIDP500_SE_IRQ_CONF_VALID		(1 << 4)
40 #define MALIDP500_SE_IRQ_INIT_BUSY		(1 << 5)
41 #define MALIDP500_SE_IRQ_AXI_ERROR		(1 << 8)
42 #define MALIDP500_SE_IRQ_OVERRUN		(1 << 9)
43 #define MALIDP500_SE_IRQ_PROG_LINE1		(1 << 12)
44 #define MALIDP500_SE_IRQ_PROG_LINE2		(1 << 13)
45 #define MALIDP500_SE_IRQ_CONF_ACTIVE		(1 << 17)
46 #define MALIDP500_SE_IRQ_PM_ACTIVE		(1 << 18)
47 #define MALIDP500_SE_IRQ_AXI_BUSY		(1 << 28)
48 #define MALIDP500_SE_IRQ_GLOBAL			(1 << 31)
49 
50 #define MALIDP550_DE_IRQ_SATURATION		(1 << 8)
51 #define MALIDP550_DE_IRQ_VSYNC			(1 << 12)
52 #define MALIDP550_DE_IRQ_PROG_LINE		(1 << 13)
53 #define MALIDP550_DE_IRQ_AXI_ERR		(1 << 16)
54 #define MALIDP550_SE_IRQ_EOW			(1 << 0)
55 #define MALIDP550_SE_IRQ_AXI_ERR		(1 << 16)
56 #define MALIDP550_SE_IRQ_OVR			(1 << 17)
57 #define MALIDP550_SE_IRQ_IBSY			(1 << 18)
58 #define MALIDP550_DC_IRQ_CONF_VALID		(1 << 0)
59 #define MALIDP550_DC_IRQ_CONF_MODE		(1 << 4)
60 #define MALIDP550_DC_IRQ_CONF_ACTIVE		(1 << 16)
61 #define MALIDP550_DC_IRQ_DE			(1 << 20)
62 #define MALIDP550_DC_IRQ_SE			(1 << 24)
63 
64 #define MALIDP650_DE_IRQ_DRIFT			(1 << 4)
65 #define MALIDP650_DE_IRQ_ACEV1			(1 << 17)
66 #define MALIDP650_DE_IRQ_ACEV2			(1 << 18)
67 #define MALIDP650_DE_IRQ_ACEG			(1 << 19)
68 #define MALIDP650_DE_IRQ_AXIEP			(1 << 28)
69 
70 /* bit masks that are common between products */
71 #define   MALIDP_CFG_VALID		(1 << 0)
72 #define   MALIDP_DISP_FUNC_GAMMA	(1 << 0)
73 #define   MALIDP_DISP_FUNC_CADJ		(1 << 4)
74 #define   MALIDP_DISP_FUNC_ILACED	(1 << 8)
75 #define   MALIDP_SCALE_ENGINE_EN	(1 << 16)
76 #define   MALIDP_SE_MEMWRITE_EN		(2 << 5)
77 
78 /* register offsets for IRQ management */
79 #define MALIDP_REG_STATUS		0x00000
80 #define MALIDP_REG_SETIRQ		0x00004
81 #define MALIDP_REG_MASKIRQ		0x00008
82 #define MALIDP_REG_CLEARIRQ		0x0000c
83 
84 /* register offsets */
85 #define MALIDP_DE_CORE_ID		0x00018
86 #define MALIDP_DE_DISPLAY_FUNC		0x00020
87 
88 /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */
89 #define MALIDP_DE_H_TIMINGS		0x0
90 #define MALIDP_DE_V_TIMINGS		0x4
91 #define MALIDP_DE_SYNC_WIDTH		0x8
92 #define MALIDP_DE_HV_ACTIVE		0xc
93 
94 /* Stride register offsets relative to Lx_BASE */
95 #define MALIDP_DE_LG_STRIDE		0x18
96 #define MALIDP_DE_LV_STRIDE0		0x18
97 #define MALIDP550_DE_LS_R1_STRIDE	0x28
98 
99 /* macros to set values into registers */
100 #define MALIDP_DE_H_FRONTPORCH(x)	(((x) & 0xfff) << 0)
101 #define MALIDP_DE_H_BACKPORCH(x)	(((x) & 0x3ff) << 16)
102 #define MALIDP500_DE_V_FRONTPORCH(x)	(((x) & 0xff) << 0)
103 #define MALIDP550_DE_V_FRONTPORCH(x)	(((x) & 0xfff) << 0)
104 #define MALIDP_DE_V_BACKPORCH(x)	(((x) & 0xff) << 16)
105 #define MALIDP_DE_H_SYNCWIDTH(x)	(((x) & 0x3ff) << 0)
106 #define MALIDP_DE_V_SYNCWIDTH(x)	(((x) & 0xff) << 16)
107 #define MALIDP_DE_H_ACTIVE(x)		(((x) & 0x1fff) << 0)
108 #define MALIDP_DE_V_ACTIVE(x)		(((x) & 0x1fff) << 16)
109 
110 #define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16)
111 
112 /* register offsets relative to MALIDP5x0_COEFFS_BASE */
113 #define MALIDP_COLOR_ADJ_COEF		0x00000
114 #define MALIDP_COEF_TABLE_ADDR		0x00030
115 #define MALIDP_COEF_TABLE_DATA		0x00034
116 
117 /* Scaling engine registers and masks. */
118 #define   MALIDP_SE_SCALING_EN			(1 << 0)
119 #define   MALIDP_SE_ALPHA_EN			(1 << 1)
120 #define   MALIDP_SE_ENH_MASK			3
121 #define   MALIDP_SE_ENH(x)			(((x) & MALIDP_SE_ENH_MASK) << 2)
122 #define   MALIDP_SE_RGBO_IF_EN			(1 << 4)
123 #define   MALIDP550_SE_CTL_SEL_MASK		7
124 #define   MALIDP550_SE_CTL_VCSEL(x) \
125 		(((x) & MALIDP550_SE_CTL_SEL_MASK) << 20)
126 #define   MALIDP550_SE_CTL_HCSEL(x) \
127 		(((x) & MALIDP550_SE_CTL_SEL_MASK) << 16)
128 
129 /* Blocks with offsets from SE_CONTROL register. */
130 #define MALIDP_SE_LAYER_CONTROL			0x14
131 #define   MALIDP_SE_L0_IN_SIZE			0x00
132 #define   MALIDP_SE_L0_OUT_SIZE			0x04
133 #define   MALIDP_SE_SET_V_SIZE(x)		(((x) & 0x1fff) << 16)
134 #define   MALIDP_SE_SET_H_SIZE(x)		(((x) & 0x1fff) << 0)
135 #define MALIDP_SE_SCALING_CONTROL		0x24
136 #define   MALIDP_SE_H_INIT_PH			0x00
137 #define   MALIDP_SE_H_DELTA_PH			0x04
138 #define   MALIDP_SE_V_INIT_PH			0x08
139 #define   MALIDP_SE_V_DELTA_PH			0x0c
140 #define   MALIDP_SE_COEFFTAB_ADDR		0x10
141 #define     MALIDP_SE_COEFFTAB_ADDR_MASK	0x7f
142 #define     MALIDP_SE_V_COEFFTAB		(1 << 8)
143 #define     MALIDP_SE_H_COEFFTAB		(1 << 9)
144 #define     MALIDP_SE_SET_V_COEFFTAB_ADDR(x) \
145 		(MALIDP_SE_V_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK))
146 #define     MALIDP_SE_SET_H_COEFFTAB_ADDR(x) \
147 		(MALIDP_SE_H_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK))
148 #define   MALIDP_SE_COEFFTAB_DATA		0x14
149 #define     MALIDP_SE_COEFFTAB_DATA_MASK	0x3fff
150 #define     MALIDP_SE_SET_COEFFTAB_DATA(x) \
151 		((x) & MALIDP_SE_COEFFTAB_DATA_MASK)
152 /* Enhance coeffents reigster offset */
153 #define MALIDP_SE_IMAGE_ENH			0x3C
154 /* ENH_LIMITS offset 0x0 */
155 #define     MALIDP_SE_ENH_LOW_LEVEL		24
156 #define     MALIDP_SE_ENH_HIGH_LEVEL		63
157 #define     MALIDP_SE_ENH_LIMIT_MASK		0xfff
158 #define     MALIDP_SE_SET_ENH_LIMIT_LOW(x) \
159 		((x) & MALIDP_SE_ENH_LIMIT_MASK)
160 #define     MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \
161 		(((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16)
162 #define   MALIDP_SE_ENH_COEFF0			0x04
163 
164 
165 /* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */
166 #define MALIDP_MW_FORMAT		0x00000
167 #define MALIDP_MW_P1_STRIDE		0x00004
168 #define MALIDP_MW_P2_STRIDE		0x00008
169 #define MALIDP_MW_P1_PTR_LOW		0x0000c
170 #define MALIDP_MW_P1_PTR_HIGH		0x00010
171 #define MALIDP_MW_P2_PTR_LOW		0x0002c
172 #define MALIDP_MW_P2_PTR_HIGH		0x00030
173 
174 /* register offsets and bits specific to DP500 */
175 #define MALIDP500_ADDR_SPACE_SIZE	0x01000
176 #define MALIDP500_DC_BASE		0x00000
177 #define MALIDP500_DC_CONTROL		0x0000c
178 #define   MALIDP500_DC_CONFIG_REQ	(1 << 17)
179 #define   MALIDP500_HSYNCPOL		(1 << 20)
180 #define   MALIDP500_VSYNCPOL		(1 << 21)
181 #define   MALIDP500_DC_CLEAR_MASK	0x300fff
182 #define MALIDP500_DE_LINE_COUNTER	0x00010
183 #define MALIDP500_DE_AXI_CONTROL	0x00014
184 #define MALIDP500_DE_SECURE_CTRL	0x0001c
185 #define MALIDP500_DE_CHROMA_KEY		0x00024
186 #define MALIDP500_TIMINGS_BASE		0x00028
187 
188 #define MALIDP500_CONFIG_3D		0x00038
189 #define MALIDP500_BGND_COLOR		0x0003c
190 #define MALIDP500_OUTPUT_DEPTH		0x00044
191 #define MALIDP500_COEFFS_BASE		0x00078
192 
193 /*
194  * The YUV2RGB coefficients on the DP500 are not in the video layer's register
195  * block. They belong in a separate block above the layer's registers, hence
196  * the negative offset.
197  */
198 #define MALIDP500_LV_YUV2RGB		((s16)(-0xB8))
199 #define MALIDP500_DE_LV_BASE		0x00100
200 #define MALIDP500_DE_LV_PTR_BASE	0x00124
201 #define MALIDP500_DE_LV_AD_CTRL		0x00400
202 #define MALIDP500_DE_LG1_BASE		0x00200
203 #define MALIDP500_DE_LG1_PTR_BASE	0x0021c
204 #define MALIDP500_DE_LG1_AD_CTRL	0x0040c
205 #define MALIDP500_DE_LG2_BASE		0x00300
206 #define MALIDP500_DE_LG2_PTR_BASE	0x0031c
207 #define MALIDP500_DE_LG2_AD_CTRL	0x00418
208 #define MALIDP500_SE_BASE		0x00c00
209 #define MALIDP500_SE_CONTROL		0x00c0c
210 #define MALIDP500_SE_MEMWRITE_OUT_SIZE	0x00c2c
211 #define MALIDP500_SE_RGB_YUV_COEFFS	0x00C74
212 #define MALIDP500_SE_MEMWRITE_BASE	0x00e00
213 #define MALIDP500_DC_IRQ_BASE		0x00f00
214 #define MALIDP500_CONFIG_VALID		0x00f00
215 #define MALIDP500_CONFIG_ID		0x00fd4
216 
217 /* register offsets and bits specific to DP550/DP650 */
218 #define MALIDP550_ADDR_SPACE_SIZE	0x10000
219 #define MALIDP550_DE_CONTROL		0x00010
220 #define MALIDP550_DE_LINE_COUNTER	0x00014
221 #define MALIDP550_DE_AXI_CONTROL	0x00018
222 #define MALIDP550_DE_QOS		0x0001c
223 #define MALIDP550_TIMINGS_BASE		0x00030
224 #define MALIDP550_HSYNCPOL		(1 << 12)
225 #define MALIDP550_VSYNCPOL		(1 << 28)
226 
227 #define MALIDP550_DE_DISP_SIDEBAND	0x00040
228 #define MALIDP550_DE_BGND_COLOR		0x00044
229 #define MALIDP550_DE_OUTPUT_DEPTH	0x0004c
230 #define MALIDP550_COEFFS_BASE		0x00050
231 #define MALIDP550_LV_YUV2RGB		0x00084
232 #define MALIDP550_DE_LV1_BASE		0x00100
233 #define MALIDP550_DE_LV1_PTR_BASE	0x00124
234 #define MALIDP550_DE_LV1_AD_CTRL	0x001B8
235 #define MALIDP550_DE_LV2_BASE		0x00200
236 #define MALIDP550_DE_LV2_PTR_BASE	0x00224
237 #define MALIDP550_DE_LV2_AD_CTRL	0x002B8
238 #define MALIDP550_DE_LG_BASE		0x00300
239 #define MALIDP550_DE_LG_PTR_BASE	0x0031c
240 #define MALIDP550_DE_LG_AD_CTRL		0x00330
241 #define MALIDP550_DE_LS_BASE		0x00400
242 #define MALIDP550_DE_LS_PTR_BASE	0x0042c
243 #define MALIDP550_DE_PERF_BASE		0x00500
244 #define MALIDP550_SE_BASE		0x08000
245 #define MALIDP550_SE_CONTROL		0x08010
246 #define   MALIDP550_SE_MEMWRITE_ONESHOT	(1 << 7)
247 #define MALIDP550_SE_MEMWRITE_OUT_SIZE	0x08030
248 #define MALIDP550_SE_RGB_YUV_COEFFS	0x08078
249 #define MALIDP550_SE_MEMWRITE_BASE	0x08100
250 #define MALIDP550_DC_BASE		0x0c000
251 #define MALIDP550_DC_CONTROL		0x0c010
252 #define   MALIDP550_DC_CONFIG_REQ	(1 << 16)
253 #define MALIDP550_CONFIG_VALID		0x0c014
254 #define MALIDP550_CONFIG_ID		0x0ffd4
255 
256 /* register offsets specific to DP650 */
257 #define MALIDP650_DE_LV_MMU_CTRL	0x000D0
258 #define MALIDP650_DE_LG_MMU_CTRL	0x00048
259 #define MALIDP650_DE_LS_MMU_CTRL	0x00078
260 
261 /* bit masks to set the MMU control register */
262 #define MALIDP_MMU_CTRL_EN		(1 << 0)
263 #define MALIDP_MMU_CTRL_MODE		(1 << 4)
264 #define MALIDP_MMU_CTRL_PX_PS(x)	(1 << (8 + (x)))
265 #define MALIDP_MMU_CTRL_PP_NUM_REQ(x)	(((x) & 0x7f) << 12)
266 
267 /* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */
268 /* The following register offsets are common for DP500, DP550 and DP650 */
269 #define MALIDP_AD_CROP_H                0x4
270 #define MALIDP_AD_CROP_V                0x8
271 #define MALIDP_AD_END_PTR_LOW           0xc
272 #define MALIDP_AD_END_PTR_HIGH          0x10
273 
274 /* AFBC decoder Registers */
275 #define MALIDP_AD_EN                    BIT(0)
276 #define MALIDP_AD_YTR                   BIT(4)
277 #define MALIDP_AD_BS                    BIT(8)
278 #define MALIDP_AD_CROP_RIGHT_OFFSET     16
279 #define MALIDP_AD_CROP_BOTTOM_OFFSET    16
280 
281 /*
282  * Starting with DP550 the register map blocks has been standardised to the
283  * following layout:
284  *
285  *   Offset            Block registers
286  *  0x00000            Display Engine
287  *  0x08000            Scaling Engine
288  *  0x0c000            Display Core
289  *  0x10000            Secure control
290  *
291  * The old DP500 IP mixes some DC with the DE registers, hence the need
292  * for a mapping structure.
293  */
294 
295 #endif /* __MALIDP_REGS_H__ */
296