1ad49f860SLiviu Dudau /* 2ad49f860SLiviu Dudau * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3ad49f860SLiviu Dudau * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4ad49f860SLiviu Dudau * 5ad49f860SLiviu Dudau * This program is free software and is provided to you under the terms of the 6ad49f860SLiviu Dudau * GNU General Public License version 2 as published by the Free Software 7ad49f860SLiviu Dudau * Foundation, and any use by you of this program is subject to the terms 8ad49f860SLiviu Dudau * of such GNU licence. 9ad49f860SLiviu Dudau * 10ad49f860SLiviu Dudau * ARM Mali DP500/DP550/DP650 registers definition. 11ad49f860SLiviu Dudau */ 12ad49f860SLiviu Dudau 13ad49f860SLiviu Dudau #ifndef __MALIDP_REGS_H__ 14ad49f860SLiviu Dudau #define __MALIDP_REGS_H__ 15ad49f860SLiviu Dudau 16ad49f860SLiviu Dudau /* 17ad49f860SLiviu Dudau * abbreviations used: 18ad49f860SLiviu Dudau * - DC - display core (general settings) 19ad49f860SLiviu Dudau * - DE - display engine 20ad49f860SLiviu Dudau * - SE - scaling engine 21ad49f860SLiviu Dudau */ 22ad49f860SLiviu Dudau 23ad49f860SLiviu Dudau /* interrupt bit masks */ 24ad49f860SLiviu Dudau #define MALIDP_DE_IRQ_UNDERRUN (1 << 0) 25ad49f860SLiviu Dudau 26ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_AXI_ERR (1 << 4) 27ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_VSYNC (1 << 5) 28ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_PROG_LINE (1 << 6) 29ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_SATURATION (1 << 7) 30ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_VALID (1 << 8) 31ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_MODE (1 << 11) 32ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17) 33ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18) 34ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19) 35ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24) 36ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28) 37ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_GLOBAL (1 << 31) 38ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0) 39ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_VALID (1 << 4) 40ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5) 41ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8) 42ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_OVERRUN (1 << 9) 43ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12) 44ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13) 45ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17) 46ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18) 47ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28) 48ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_GLOBAL (1 << 31) 49ad49f860SLiviu Dudau 50ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_SATURATION (1 << 8) 51ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_VSYNC (1 << 12) 52ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_PROG_LINE (1 << 13) 53ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_AXI_ERR (1 << 16) 54ad49f860SLiviu Dudau #define MALIDP550_SE_IRQ_EOW (1 << 0) 55ad49f860SLiviu Dudau #define MALIDP550_SE_IRQ_AXI_ERR (1 << 16) 56ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0) 57ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_MODE (1 << 4) 58ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16) 59ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_DE (1 << 20) 60ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_SE (1 << 24) 61ad49f860SLiviu Dudau 62ad49f860SLiviu Dudau #define MALIDP650_DE_IRQ_DRIFT (1 << 4) 63ad49f860SLiviu Dudau 64ad49f860SLiviu Dudau /* bit masks that are common between products */ 65ad49f860SLiviu Dudau #define MALIDP_CFG_VALID (1 << 0) 6602725d31SMihail Atanassov #define MALIDP_DISP_FUNC_GAMMA (1 << 0) 676954f245SMihail Atanassov #define MALIDP_DISP_FUNC_CADJ (1 << 4) 68ad49f860SLiviu Dudau #define MALIDP_DISP_FUNC_ILACED (1 << 8) 69846c87a0SLiviu Dudau #define MALIDP_SCALE_ENGINE_EN (1 << 16) 70846c87a0SLiviu Dudau #define MALIDP_SE_MEMWRITE_EN (2 << 5) 71ad49f860SLiviu Dudau 72ad49f860SLiviu Dudau /* register offsets for IRQ management */ 73ad49f860SLiviu Dudau #define MALIDP_REG_STATUS 0x00000 74ad49f860SLiviu Dudau #define MALIDP_REG_SETIRQ 0x00004 75ad49f860SLiviu Dudau #define MALIDP_REG_MASKIRQ 0x00008 76ad49f860SLiviu Dudau #define MALIDP_REG_CLEARIRQ 0x0000c 77ad49f860SLiviu Dudau 78ad49f860SLiviu Dudau /* register offsets */ 79ad49f860SLiviu Dudau #define MALIDP_DE_CORE_ID 0x00018 80ad49f860SLiviu Dudau #define MALIDP_DE_DISPLAY_FUNC 0x00020 81ad49f860SLiviu Dudau 82ad49f860SLiviu Dudau /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */ 83ad49f860SLiviu Dudau #define MALIDP_DE_H_TIMINGS 0x0 84ad49f860SLiviu Dudau #define MALIDP_DE_V_TIMINGS 0x4 85ad49f860SLiviu Dudau #define MALIDP_DE_SYNC_WIDTH 0x8 86ad49f860SLiviu Dudau #define MALIDP_DE_HV_ACTIVE 0xc 87ad49f860SLiviu Dudau 8883d642eeSMihail Atanassov /* Stride register offsets relative to Lx_BASE */ 8983d642eeSMihail Atanassov #define MALIDP_DE_LG_STRIDE 0x18 9083d642eeSMihail Atanassov #define MALIDP_DE_LV_STRIDE0 0x18 91d1479f61SMihail Atanassov #define MALIDP550_DE_LS_R1_STRIDE 0x28 9283d642eeSMihail Atanassov 93ad49f860SLiviu Dudau /* macros to set values into registers */ 94ad49f860SLiviu Dudau #define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0) 95ad49f860SLiviu Dudau #define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16) 96ad49f860SLiviu Dudau #define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0) 97ad49f860SLiviu Dudau #define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0) 98ad49f860SLiviu Dudau #define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16) 99ad49f860SLiviu Dudau #define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0) 100ad49f860SLiviu Dudau #define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16) 101ad49f860SLiviu Dudau #define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0) 102ad49f860SLiviu Dudau #define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16) 103ad49f860SLiviu Dudau 104592d8c8cSMihail Atanassov #define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16) 105592d8c8cSMihail Atanassov 10602725d31SMihail Atanassov /* register offsets relative to MALIDP5x0_COEFFS_BASE */ 10702725d31SMihail Atanassov #define MALIDP_COLOR_ADJ_COEF 0x00000 10802725d31SMihail Atanassov #define MALIDP_COEF_TABLE_ADDR 0x00030 10902725d31SMihail Atanassov #define MALIDP_COEF_TABLE_DATA 0x00034 11002725d31SMihail Atanassov 11128ce675bSMihail Atanassov /* Scaling engine registers and masks. */ 11228ce675bSMihail Atanassov #define MALIDP_SE_SCALING_EN (1 << 0) 11328ce675bSMihail Atanassov #define MALIDP_SE_ALPHA_EN (1 << 1) 1140274e6a0SMihail Atanassov #define MALIDP_SE_ENH_MASK 3 1150274e6a0SMihail Atanassov #define MALIDP_SE_ENH(x) (((x) & MALIDP_SE_ENH_MASK) << 2) 11628ce675bSMihail Atanassov #define MALIDP_SE_RGBO_IF_EN (1 << 4) 11728ce675bSMihail Atanassov #define MALIDP550_SE_CTL_SEL_MASK 7 11828ce675bSMihail Atanassov #define MALIDP550_SE_CTL_VCSEL(x) \ 11928ce675bSMihail Atanassov (((x) & MALIDP550_SE_CTL_SEL_MASK) << 20) 12028ce675bSMihail Atanassov #define MALIDP550_SE_CTL_HCSEL(x) \ 12128ce675bSMihail Atanassov (((x) & MALIDP550_SE_CTL_SEL_MASK) << 16) 12228ce675bSMihail Atanassov 12328ce675bSMihail Atanassov /* Blocks with offsets from SE_CONTROL register. */ 12428ce675bSMihail Atanassov #define MALIDP_SE_LAYER_CONTROL 0x14 12528ce675bSMihail Atanassov #define MALIDP_SE_L0_IN_SIZE 0x00 12628ce675bSMihail Atanassov #define MALIDP_SE_L0_OUT_SIZE 0x04 12728ce675bSMihail Atanassov #define MALIDP_SE_SET_V_SIZE(x) (((x) & 0x1fff) << 16) 12828ce675bSMihail Atanassov #define MALIDP_SE_SET_H_SIZE(x) (((x) & 0x1fff) << 0) 12928ce675bSMihail Atanassov #define MALIDP_SE_SCALING_CONTROL 0x24 13028ce675bSMihail Atanassov #define MALIDP_SE_H_INIT_PH 0x00 13128ce675bSMihail Atanassov #define MALIDP_SE_H_DELTA_PH 0x04 13228ce675bSMihail Atanassov #define MALIDP_SE_V_INIT_PH 0x08 13328ce675bSMihail Atanassov #define MALIDP_SE_V_DELTA_PH 0x0c 13428ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_ADDR 0x10 13528ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_ADDR_MASK 0x7f 13628ce675bSMihail Atanassov #define MALIDP_SE_V_COEFFTAB (1 << 8) 13728ce675bSMihail Atanassov #define MALIDP_SE_H_COEFFTAB (1 << 9) 13828ce675bSMihail Atanassov #define MALIDP_SE_SET_V_COEFFTAB_ADDR(x) \ 13928ce675bSMihail Atanassov (MALIDP_SE_V_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) 14028ce675bSMihail Atanassov #define MALIDP_SE_SET_H_COEFFTAB_ADDR(x) \ 14128ce675bSMihail Atanassov (MALIDP_SE_H_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) 14228ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_DATA 0x14 14328ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff 14428ce675bSMihail Atanassov #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ 14528ce675bSMihail Atanassov ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) 1460274e6a0SMihail Atanassov /* Enhance coeffents reigster offset */ 1470274e6a0SMihail Atanassov #define MALIDP_SE_IMAGE_ENH 0x3C 1480274e6a0SMihail Atanassov /* ENH_LIMITS offset 0x0 */ 1490274e6a0SMihail Atanassov #define MALIDP_SE_ENH_LOW_LEVEL 24 1500274e6a0SMihail Atanassov #define MALIDP_SE_ENH_HIGH_LEVEL 63 1510274e6a0SMihail Atanassov #define MALIDP_SE_ENH_LIMIT_MASK 0xfff 1520274e6a0SMihail Atanassov #define MALIDP_SE_SET_ENH_LIMIT_LOW(x) \ 1530274e6a0SMihail Atanassov ((x) & MALIDP_SE_ENH_LIMIT_MASK) 1540274e6a0SMihail Atanassov #define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \ 1550274e6a0SMihail Atanassov (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16) 1560274e6a0SMihail Atanassov #define MALIDP_SE_ENH_COEFF0 0x04 15728ce675bSMihail Atanassov 158846c87a0SLiviu Dudau 159846c87a0SLiviu Dudau /* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */ 160846c87a0SLiviu Dudau #define MALIDP_MW_FORMAT 0x00000 161846c87a0SLiviu Dudau #define MALIDP_MW_P1_STRIDE 0x00004 162846c87a0SLiviu Dudau #define MALIDP_MW_P2_STRIDE 0x00008 163846c87a0SLiviu Dudau #define MALIDP_MW_P1_PTR_LOW 0x0000c 164846c87a0SLiviu Dudau #define MALIDP_MW_P1_PTR_HIGH 0x00010 165846c87a0SLiviu Dudau #define MALIDP_MW_P2_PTR_LOW 0x0002c 166846c87a0SLiviu Dudau #define MALIDP_MW_P2_PTR_HIGH 0x00030 167846c87a0SLiviu Dudau 168ad49f860SLiviu Dudau /* register offsets and bits specific to DP500 */ 1694d6000edSMihail Atanassov #define MALIDP500_ADDR_SPACE_SIZE 0x01000 170ad49f860SLiviu Dudau #define MALIDP500_DC_BASE 0x00000 171ad49f860SLiviu Dudau #define MALIDP500_DC_CONTROL 0x0000c 172ad49f860SLiviu Dudau #define MALIDP500_DC_CONFIG_REQ (1 << 17) 173ad49f860SLiviu Dudau #define MALIDP500_HSYNCPOL (1 << 20) 174ad49f860SLiviu Dudau #define MALIDP500_VSYNCPOL (1 << 21) 175ad49f860SLiviu Dudau #define MALIDP500_DC_CLEAR_MASK 0x300fff 176ad49f860SLiviu Dudau #define MALIDP500_DE_LINE_COUNTER 0x00010 177ad49f860SLiviu Dudau #define MALIDP500_DE_AXI_CONTROL 0x00014 178ad49f860SLiviu Dudau #define MALIDP500_DE_SECURE_CTRL 0x0001c 179ad49f860SLiviu Dudau #define MALIDP500_DE_CHROMA_KEY 0x00024 180ad49f860SLiviu Dudau #define MALIDP500_TIMINGS_BASE 0x00028 181ad49f860SLiviu Dudau 182ad49f860SLiviu Dudau #define MALIDP500_CONFIG_3D 0x00038 183ad49f860SLiviu Dudau #define MALIDP500_BGND_COLOR 0x0003c 184ad49f860SLiviu Dudau #define MALIDP500_OUTPUT_DEPTH 0x00044 1856e810eb5SMihail Atanassov #define MALIDP500_COEFFS_BASE 0x00078 18602725d31SMihail Atanassov 18702725d31SMihail Atanassov /* 18802725d31SMihail Atanassov * The YUV2RGB coefficients on the DP500 are not in the video layer's register 18902725d31SMihail Atanassov * block. They belong in a separate block above the layer's registers, hence 19002725d31SMihail Atanassov * the negative offset. 19102725d31SMihail Atanassov */ 19202725d31SMihail Atanassov #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8)) 193ad49f860SLiviu Dudau #define MALIDP500_DE_LV_BASE 0x00100 194ad49f860SLiviu Dudau #define MALIDP500_DE_LV_PTR_BASE 0x00124 195ad49f860SLiviu Dudau #define MALIDP500_DE_LG1_BASE 0x00200 196ad49f860SLiviu Dudau #define MALIDP500_DE_LG1_PTR_BASE 0x0021c 197ad49f860SLiviu Dudau #define MALIDP500_DE_LG2_BASE 0x00300 198ad49f860SLiviu Dudau #define MALIDP500_DE_LG2_PTR_BASE 0x0031c 199ad49f860SLiviu Dudau #define MALIDP500_SE_BASE 0x00c00 20028ce675bSMihail Atanassov #define MALIDP500_SE_CONTROL 0x00c0c 2011cb3cbe7SLiviu Dudau #define MALIDP500_SE_MEMWRITE_OUT_SIZE 0x00c2c 2021cb3cbe7SLiviu Dudau #define MALIDP500_SE_MEMWRITE_BASE 0x00e00 203ad49f860SLiviu Dudau #define MALIDP500_DC_IRQ_BASE 0x00f00 204ad49f860SLiviu Dudau #define MALIDP500_CONFIG_VALID 0x00f00 205ad49f860SLiviu Dudau #define MALIDP500_CONFIG_ID 0x00fd4 206ad49f860SLiviu Dudau 207ad49f860SLiviu Dudau /* register offsets and bits specific to DP550/DP650 */ 2084d6000edSMihail Atanassov #define MALIDP550_ADDR_SPACE_SIZE 0x10000 209ad49f860SLiviu Dudau #define MALIDP550_DE_CONTROL 0x00010 210ad49f860SLiviu Dudau #define MALIDP550_DE_LINE_COUNTER 0x00014 211ad49f860SLiviu Dudau #define MALIDP550_DE_AXI_CONTROL 0x00018 212ad49f860SLiviu Dudau #define MALIDP550_DE_QOS 0x0001c 213ad49f860SLiviu Dudau #define MALIDP550_TIMINGS_BASE 0x00030 214ad49f860SLiviu Dudau #define MALIDP550_HSYNCPOL (1 << 12) 215ad49f860SLiviu Dudau #define MALIDP550_VSYNCPOL (1 << 28) 216ad49f860SLiviu Dudau 217ad49f860SLiviu Dudau #define MALIDP550_DE_DISP_SIDEBAND 0x00040 218ad49f860SLiviu Dudau #define MALIDP550_DE_BGND_COLOR 0x00044 219ad49f860SLiviu Dudau #define MALIDP550_DE_OUTPUT_DEPTH 0x0004c 22002725d31SMihail Atanassov #define MALIDP550_COEFFS_BASE 0x00050 2216e810eb5SMihail Atanassov #define MALIDP550_LV_YUV2RGB 0x00084 222ad49f860SLiviu Dudau #define MALIDP550_DE_LV1_BASE 0x00100 223ad49f860SLiviu Dudau #define MALIDP550_DE_LV1_PTR_BASE 0x00124 224ad49f860SLiviu Dudau #define MALIDP550_DE_LV2_BASE 0x00200 225ad49f860SLiviu Dudau #define MALIDP550_DE_LV2_PTR_BASE 0x00224 226ad49f860SLiviu Dudau #define MALIDP550_DE_LG_BASE 0x00300 227ad49f860SLiviu Dudau #define MALIDP550_DE_LG_PTR_BASE 0x0031c 228ad49f860SLiviu Dudau #define MALIDP550_DE_LS_BASE 0x00400 229ad49f860SLiviu Dudau #define MALIDP550_DE_LS_PTR_BASE 0x0042c 230ad49f860SLiviu Dudau #define MALIDP550_DE_PERF_BASE 0x00500 231ad49f860SLiviu Dudau #define MALIDP550_SE_BASE 0x08000 23228ce675bSMihail Atanassov #define MALIDP550_SE_CONTROL 0x08010 233846c87a0SLiviu Dudau #define MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7) 234846c87a0SLiviu Dudau #define MALIDP550_SE_MEMWRITE_OUT_SIZE 0x08030 235846c87a0SLiviu Dudau #define MALIDP550_SE_MEMWRITE_BASE 0x08100 236ad49f860SLiviu Dudau #define MALIDP550_DC_BASE 0x0c000 237ad49f860SLiviu Dudau #define MALIDP550_DC_CONTROL 0x0c010 238ad49f860SLiviu Dudau #define MALIDP550_DC_CONFIG_REQ (1 << 16) 239ad49f860SLiviu Dudau #define MALIDP550_CONFIG_VALID 0x0c014 240ad49f860SLiviu Dudau #define MALIDP550_CONFIG_ID 0x0ffd4 241ad49f860SLiviu Dudau 242ad49f860SLiviu Dudau /* 243ad49f860SLiviu Dudau * Starting with DP550 the register map blocks has been standardised to the 244ad49f860SLiviu Dudau * following layout: 245ad49f860SLiviu Dudau * 246ad49f860SLiviu Dudau * Offset Block registers 247ad49f860SLiviu Dudau * 0x00000 Display Engine 248ad49f860SLiviu Dudau * 0x08000 Scaling Engine 249ad49f860SLiviu Dudau * 0x0c000 Display Core 250ad49f860SLiviu Dudau * 0x10000 Secure control 251ad49f860SLiviu Dudau * 252ad49f860SLiviu Dudau * The old DP500 IP mixes some DC with the DE registers, hence the need 253ad49f860SLiviu Dudau * for a mapping structure. 254ad49f860SLiviu Dudau */ 255ad49f860SLiviu Dudau 256ad49f860SLiviu Dudau #endif /* __MALIDP_REGS_H__ */ 257