1ad49f860SLiviu Dudau /* 2ad49f860SLiviu Dudau * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3ad49f860SLiviu Dudau * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4ad49f860SLiviu Dudau * 5ad49f860SLiviu Dudau * This program is free software and is provided to you under the terms of the 6ad49f860SLiviu Dudau * GNU General Public License version 2 as published by the Free Software 7ad49f860SLiviu Dudau * Foundation, and any use by you of this program is subject to the terms 8ad49f860SLiviu Dudau * of such GNU licence. 9ad49f860SLiviu Dudau * 10ad49f860SLiviu Dudau * ARM Mali DP500/DP550/DP650 registers definition. 11ad49f860SLiviu Dudau */ 12ad49f860SLiviu Dudau 13ad49f860SLiviu Dudau #ifndef __MALIDP_REGS_H__ 14ad49f860SLiviu Dudau #define __MALIDP_REGS_H__ 15ad49f860SLiviu Dudau 16ad49f860SLiviu Dudau /* 17ad49f860SLiviu Dudau * abbreviations used: 18ad49f860SLiviu Dudau * - DC - display core (general settings) 19ad49f860SLiviu Dudau * - DE - display engine 20ad49f860SLiviu Dudau * - SE - scaling engine 21ad49f860SLiviu Dudau */ 22ad49f860SLiviu Dudau 23ad49f860SLiviu Dudau /* interrupt bit masks */ 24ad49f860SLiviu Dudau #define MALIDP_DE_IRQ_UNDERRUN (1 << 0) 25ad49f860SLiviu Dudau 26ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_AXI_ERR (1 << 4) 27ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_VSYNC (1 << 5) 28ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_PROG_LINE (1 << 6) 29ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_SATURATION (1 << 7) 30ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_VALID (1 << 8) 31ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_MODE (1 << 11) 32ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17) 33ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18) 34ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19) 35ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24) 36ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28) 37ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_GLOBAL (1 << 31) 38ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0) 39ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_VALID (1 << 4) 40ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5) 41ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8) 42ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_OVERRUN (1 << 9) 43ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12) 44ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13) 45ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17) 46ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18) 47ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28) 48ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_GLOBAL (1 << 31) 49ad49f860SLiviu Dudau 50ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_SATURATION (1 << 8) 51ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_VSYNC (1 << 12) 52ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_PROG_LINE (1 << 13) 53ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_AXI_ERR (1 << 16) 54ad49f860SLiviu Dudau #define MALIDP550_SE_IRQ_EOW (1 << 0) 55ad49f860SLiviu Dudau #define MALIDP550_SE_IRQ_AXI_ERR (1 << 16) 56ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0) 57ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_MODE (1 << 4) 58ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16) 59ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_DE (1 << 20) 60ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_SE (1 << 24) 61ad49f860SLiviu Dudau 62ad49f860SLiviu Dudau #define MALIDP650_DE_IRQ_DRIFT (1 << 4) 63ad49f860SLiviu Dudau 64ad49f860SLiviu Dudau /* bit masks that are common between products */ 65ad49f860SLiviu Dudau #define MALIDP_CFG_VALID (1 << 0) 6602725d31SMihail Atanassov #define MALIDP_DISP_FUNC_GAMMA (1 << 0) 67ad49f860SLiviu Dudau #define MALIDP_DISP_FUNC_ILACED (1 << 8) 68ad49f860SLiviu Dudau 69ad49f860SLiviu Dudau /* register offsets for IRQ management */ 70ad49f860SLiviu Dudau #define MALIDP_REG_STATUS 0x00000 71ad49f860SLiviu Dudau #define MALIDP_REG_SETIRQ 0x00004 72ad49f860SLiviu Dudau #define MALIDP_REG_MASKIRQ 0x00008 73ad49f860SLiviu Dudau #define MALIDP_REG_CLEARIRQ 0x0000c 74ad49f860SLiviu Dudau 75ad49f860SLiviu Dudau /* register offsets */ 76ad49f860SLiviu Dudau #define MALIDP_DE_CORE_ID 0x00018 77ad49f860SLiviu Dudau #define MALIDP_DE_DISPLAY_FUNC 0x00020 78ad49f860SLiviu Dudau 79ad49f860SLiviu Dudau /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */ 80ad49f860SLiviu Dudau #define MALIDP_DE_H_TIMINGS 0x0 81ad49f860SLiviu Dudau #define MALIDP_DE_V_TIMINGS 0x4 82ad49f860SLiviu Dudau #define MALIDP_DE_SYNC_WIDTH 0x8 83ad49f860SLiviu Dudau #define MALIDP_DE_HV_ACTIVE 0xc 84ad49f860SLiviu Dudau 8583d642eeSMihail Atanassov /* Stride register offsets relative to Lx_BASE */ 8683d642eeSMihail Atanassov #define MALIDP_DE_LG_STRIDE 0x18 8783d642eeSMihail Atanassov #define MALIDP_DE_LV_STRIDE0 0x18 88d1479f61SMihail Atanassov #define MALIDP550_DE_LS_R1_STRIDE 0x28 8983d642eeSMihail Atanassov 90ad49f860SLiviu Dudau /* macros to set values into registers */ 91ad49f860SLiviu Dudau #define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0) 92ad49f860SLiviu Dudau #define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16) 93ad49f860SLiviu Dudau #define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0) 94ad49f860SLiviu Dudau #define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0) 95ad49f860SLiviu Dudau #define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16) 96ad49f860SLiviu Dudau #define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0) 97ad49f860SLiviu Dudau #define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16) 98ad49f860SLiviu Dudau #define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0) 99ad49f860SLiviu Dudau #define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16) 100ad49f860SLiviu Dudau 101592d8c8cSMihail Atanassov #define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16) 102592d8c8cSMihail Atanassov 10302725d31SMihail Atanassov /* register offsets relative to MALIDP5x0_COEFFS_BASE */ 10402725d31SMihail Atanassov #define MALIDP_COLOR_ADJ_COEF 0x00000 10502725d31SMihail Atanassov #define MALIDP_COEF_TABLE_ADDR 0x00030 10602725d31SMihail Atanassov #define MALIDP_COEF_TABLE_DATA 0x00034 10702725d31SMihail Atanassov 108ad49f860SLiviu Dudau /* register offsets and bits specific to DP500 */ 1094d6000edSMihail Atanassov #define MALIDP500_ADDR_SPACE_SIZE 0x01000 110ad49f860SLiviu Dudau #define MALIDP500_DC_BASE 0x00000 111ad49f860SLiviu Dudau #define MALIDP500_DC_CONTROL 0x0000c 112ad49f860SLiviu Dudau #define MALIDP500_DC_CONFIG_REQ (1 << 17) 113ad49f860SLiviu Dudau #define MALIDP500_HSYNCPOL (1 << 20) 114ad49f860SLiviu Dudau #define MALIDP500_VSYNCPOL (1 << 21) 115ad49f860SLiviu Dudau #define MALIDP500_DC_CLEAR_MASK 0x300fff 116ad49f860SLiviu Dudau #define MALIDP500_DE_LINE_COUNTER 0x00010 117ad49f860SLiviu Dudau #define MALIDP500_DE_AXI_CONTROL 0x00014 118ad49f860SLiviu Dudau #define MALIDP500_DE_SECURE_CTRL 0x0001c 119ad49f860SLiviu Dudau #define MALIDP500_DE_CHROMA_KEY 0x00024 120ad49f860SLiviu Dudau #define MALIDP500_TIMINGS_BASE 0x00028 121ad49f860SLiviu Dudau 122ad49f860SLiviu Dudau #define MALIDP500_CONFIG_3D 0x00038 123ad49f860SLiviu Dudau #define MALIDP500_BGND_COLOR 0x0003c 124ad49f860SLiviu Dudau #define MALIDP500_OUTPUT_DEPTH 0x00044 125ad49f860SLiviu Dudau #define MALIDP500_YUV_RGB_COEF 0x00048 126ad49f860SLiviu Dudau #define MALIDP500_COLOR_ADJ_COEF 0x00078 127ad49f860SLiviu Dudau #define MALIDP500_COEF_TABLE_ADDR 0x000a8 128ad49f860SLiviu Dudau #define MALIDP500_COEF_TABLE_DATA 0x000ac 12902725d31SMihail Atanassov 13002725d31SMihail Atanassov /* 13102725d31SMihail Atanassov * The YUV2RGB coefficients on the DP500 are not in the video layer's register 13202725d31SMihail Atanassov * block. They belong in a separate block above the layer's registers, hence 13302725d31SMihail Atanassov * the negative offset. 13402725d31SMihail Atanassov */ 13502725d31SMihail Atanassov #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8)) 13602725d31SMihail Atanassov /* 13702725d31SMihail Atanassov * To match DP550/650, the start of the coeffs registers is 13802725d31SMihail Atanassov * at COLORADJ_COEFF0 instead of at YUV_RGB_COEF1. 13902725d31SMihail Atanassov */ 14002725d31SMihail Atanassov #define MALIDP500_COEFFS_BASE 0x00078 141ad49f860SLiviu Dudau #define MALIDP500_DE_LV_BASE 0x00100 142ad49f860SLiviu Dudau #define MALIDP500_DE_LV_PTR_BASE 0x00124 143ad49f860SLiviu Dudau #define MALIDP500_DE_LG1_BASE 0x00200 144ad49f860SLiviu Dudau #define MALIDP500_DE_LG1_PTR_BASE 0x0021c 145ad49f860SLiviu Dudau #define MALIDP500_DE_LG2_BASE 0x00300 146ad49f860SLiviu Dudau #define MALIDP500_DE_LG2_PTR_BASE 0x0031c 147ad49f860SLiviu Dudau #define MALIDP500_SE_BASE 0x00c00 148ad49f860SLiviu Dudau #define MALIDP500_SE_PTR_BASE 0x00e0c 149ad49f860SLiviu Dudau #define MALIDP500_DC_IRQ_BASE 0x00f00 150ad49f860SLiviu Dudau #define MALIDP500_CONFIG_VALID 0x00f00 151ad49f860SLiviu Dudau #define MALIDP500_CONFIG_ID 0x00fd4 152ad49f860SLiviu Dudau 153ad49f860SLiviu Dudau /* register offsets and bits specific to DP550/DP650 */ 1544d6000edSMihail Atanassov #define MALIDP550_ADDR_SPACE_SIZE 0x10000 155ad49f860SLiviu Dudau #define MALIDP550_DE_CONTROL 0x00010 156ad49f860SLiviu Dudau #define MALIDP550_DE_LINE_COUNTER 0x00014 157ad49f860SLiviu Dudau #define MALIDP550_DE_AXI_CONTROL 0x00018 158ad49f860SLiviu Dudau #define MALIDP550_DE_QOS 0x0001c 159ad49f860SLiviu Dudau #define MALIDP550_TIMINGS_BASE 0x00030 160ad49f860SLiviu Dudau #define MALIDP550_HSYNCPOL (1 << 12) 161ad49f860SLiviu Dudau #define MALIDP550_VSYNCPOL (1 << 28) 162ad49f860SLiviu Dudau 163ad49f860SLiviu Dudau #define MALIDP550_DE_DISP_SIDEBAND 0x00040 164ad49f860SLiviu Dudau #define MALIDP550_DE_BGND_COLOR 0x00044 165ad49f860SLiviu Dudau #define MALIDP550_DE_OUTPUT_DEPTH 0x0004c 16602725d31SMihail Atanassov #define MALIDP550_COEFFS_BASE 0x00050 167ad49f860SLiviu Dudau #define MALIDP550_DE_LV1_BASE 0x00100 168ad49f860SLiviu Dudau #define MALIDP550_DE_LV1_PTR_BASE 0x00124 169ad49f860SLiviu Dudau #define MALIDP550_DE_LV2_BASE 0x00200 170ad49f860SLiviu Dudau #define MALIDP550_DE_LV2_PTR_BASE 0x00224 171ad49f860SLiviu Dudau #define MALIDP550_DE_LG_BASE 0x00300 172ad49f860SLiviu Dudau #define MALIDP550_DE_LG_PTR_BASE 0x0031c 173ad49f860SLiviu Dudau #define MALIDP550_DE_LS_BASE 0x00400 174ad49f860SLiviu Dudau #define MALIDP550_DE_LS_PTR_BASE 0x0042c 175ad49f860SLiviu Dudau #define MALIDP550_DE_PERF_BASE 0x00500 176ad49f860SLiviu Dudau #define MALIDP550_SE_BASE 0x08000 177ad49f860SLiviu Dudau #define MALIDP550_DC_BASE 0x0c000 178ad49f860SLiviu Dudau #define MALIDP550_DC_CONTROL 0x0c010 179ad49f860SLiviu Dudau #define MALIDP550_DC_CONFIG_REQ (1 << 16) 180ad49f860SLiviu Dudau #define MALIDP550_CONFIG_VALID 0x0c014 181ad49f860SLiviu Dudau #define MALIDP550_CONFIG_ID 0x0ffd4 182ad49f860SLiviu Dudau 183ad49f860SLiviu Dudau /* 184ad49f860SLiviu Dudau * Starting with DP550 the register map blocks has been standardised to the 185ad49f860SLiviu Dudau * following layout: 186ad49f860SLiviu Dudau * 187ad49f860SLiviu Dudau * Offset Block registers 188ad49f860SLiviu Dudau * 0x00000 Display Engine 189ad49f860SLiviu Dudau * 0x08000 Scaling Engine 190ad49f860SLiviu Dudau * 0x0c000 Display Core 191ad49f860SLiviu Dudau * 0x10000 Secure control 192ad49f860SLiviu Dudau * 193ad49f860SLiviu Dudau * The old DP500 IP mixes some DC with the DE registers, hence the need 194ad49f860SLiviu Dudau * for a mapping structure. 195ad49f860SLiviu Dudau */ 196ad49f860SLiviu Dudau 197ad49f860SLiviu Dudau #endif /* __MALIDP_REGS_H__ */ 198