1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <linux/iommu.h> 14 15 #include <drm/drmP.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_fb_cma_helper.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_gem_framebuffer_helper.h> 21 #include <drm/drm_plane_helper.h> 22 #include <drm/drm_print.h> 23 24 #include "malidp_hw.h" 25 #include "malidp_drv.h" 26 27 /* Layer specific register offsets */ 28 #define MALIDP_LAYER_FORMAT 0x000 29 #define LAYER_FORMAT_MASK 0x3f 30 #define MALIDP_LAYER_CONTROL 0x004 31 #define LAYER_ENABLE (1 << 0) 32 #define LAYER_FLOWCFG_MASK 7 33 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) 34 #define LAYER_FLOWCFG_SCALE_SE 3 35 #define LAYER_ROT_OFFSET 8 36 #define LAYER_H_FLIP (1 << 10) 37 #define LAYER_V_FLIP (1 << 11) 38 #define LAYER_ROT_MASK (0xf << 8) 39 #define LAYER_COMP_MASK (0x3 << 12) 40 #define LAYER_COMP_PIXEL (0x3 << 12) 41 #define LAYER_COMP_PLANE (0x2 << 12) 42 #define LAYER_PMUL_ENABLE (0x1 << 14) 43 #define LAYER_ALPHA_OFFSET (16) 44 #define LAYER_ALPHA_MASK (0xff) 45 #define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) 46 #define MALIDP_LAYER_COMPOSE 0x008 47 #define MALIDP_LAYER_SIZE 0x00c 48 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 49 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 50 #define MALIDP_LAYER_COMP_SIZE 0x010 51 #define MALIDP_LAYER_OFFSET 0x014 52 #define MALIDP550_LS_ENABLE 0x01c 53 #define MALIDP550_LS_R1_IN_SIZE 0x020 54 55 #define MODIFIERS_COUNT_MAX 15 56 57 /* 58 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 59 * for formats with 1- or 2-bit alpha channels. 60 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 61 * opacity for 2-bit formats. 62 */ 63 #define MALIDP_ALPHA_LUT 0xffaa5500 64 65 /* page sizes the MMU prefetcher can support */ 66 #define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K) 67 #define MALIDP_MMU_PREFETCH_FULL_PGSIZES (SZ_1M | SZ_2M) 68 69 /* readahead for partial-frame prefetch */ 70 #define MALIDP_MMU_PREFETCH_READAHEAD 8 71 72 static void malidp_de_plane_destroy(struct drm_plane *plane) 73 { 74 struct malidp_plane *mp = to_malidp_plane(plane); 75 76 drm_plane_cleanup(plane); 77 kfree(mp); 78 } 79 80 /* 81 * Replicate what the default ->reset hook does: free the state pointer and 82 * allocate a new empty object. We just need enough space to store 83 * a malidp_plane_state instead of a drm_plane_state. 84 */ 85 static void malidp_plane_reset(struct drm_plane *plane) 86 { 87 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); 88 89 if (state) 90 __drm_atomic_helper_plane_destroy_state(&state->base); 91 kfree(state); 92 plane->state = NULL; 93 state = kzalloc(sizeof(*state), GFP_KERNEL); 94 if (state) 95 __drm_atomic_helper_plane_reset(plane, &state->base); 96 } 97 98 static struct 99 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 100 { 101 struct malidp_plane_state *state, *m_state; 102 103 if (!plane->state) 104 return NULL; 105 106 state = kmalloc(sizeof(*state), GFP_KERNEL); 107 if (!state) 108 return NULL; 109 110 m_state = to_malidp_plane_state(plane->state); 111 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 112 state->rotmem_size = m_state->rotmem_size; 113 state->format = m_state->format; 114 state->n_planes = m_state->n_planes; 115 116 state->mmu_prefetch_mode = m_state->mmu_prefetch_mode; 117 state->mmu_prefetch_pgsize = m_state->mmu_prefetch_pgsize; 118 119 return &state->base; 120 } 121 122 static void malidp_destroy_plane_state(struct drm_plane *plane, 123 struct drm_plane_state *state) 124 { 125 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 126 127 __drm_atomic_helper_plane_destroy_state(state); 128 kfree(m_state); 129 } 130 131 static const char * const prefetch_mode_names[] = { 132 [MALIDP_PREFETCH_MODE_NONE] = "MMU_PREFETCH_NONE", 133 [MALIDP_PREFETCH_MODE_PARTIAL] = "MMU_PREFETCH_PARTIAL", 134 [MALIDP_PREFETCH_MODE_FULL] = "MMU_PREFETCH_FULL", 135 }; 136 137 static void malidp_plane_atomic_print_state(struct drm_printer *p, 138 const struct drm_plane_state *state) 139 { 140 struct malidp_plane_state *ms = to_malidp_plane_state(state); 141 142 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); 143 drm_printf(p, "\tformat_id=%u\n", ms->format); 144 drm_printf(p, "\tn_planes=%u\n", ms->n_planes); 145 drm_printf(p, "\tmmu_prefetch_mode=%s\n", 146 prefetch_mode_names[ms->mmu_prefetch_mode]); 147 drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize); 148 } 149 150 bool malidp_format_mod_supported(struct drm_device *drm, 151 u32 format, u64 modifier) 152 { 153 const struct drm_format_info *info; 154 const u64 *modifiers; 155 struct malidp_drm *malidp = drm->dev_private; 156 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 157 158 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) 159 return false; 160 161 /* Some pixel formats are supported without any modifier */ 162 if (modifier == DRM_FORMAT_MOD_LINEAR) { 163 /* 164 * However these pixel formats need to be supported with 165 * modifiers only 166 */ 167 return !malidp_hw_format_is_afbc_only(format); 168 } 169 170 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_ARM) { 171 DRM_ERROR("Unknown modifier (not Arm)\n"); 172 return false; 173 } 174 175 if (modifier & 176 ~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) { 177 DRM_DEBUG_KMS("Unsupported modifiers\n"); 178 return false; 179 } 180 181 modifiers = malidp_format_modifiers; 182 183 /* SPLIT buffers must use SPARSE layout */ 184 if (WARN_ON_ONCE((modifier & AFBC_SPLIT) && !(modifier & AFBC_SPARSE))) 185 return false; 186 187 /* CBR only applies to YUV formats, where YTR should be always 0 */ 188 if (WARN_ON_ONCE((modifier & AFBC_CBR) && (modifier & AFBC_YTR))) 189 return false; 190 191 while (*modifiers != DRM_FORMAT_MOD_INVALID) { 192 if (*modifiers == modifier) 193 break; 194 195 modifiers++; 196 } 197 198 /* return false, if the modifier was not found */ 199 if (*modifiers == DRM_FORMAT_MOD_INVALID) { 200 DRM_DEBUG_KMS("Unsupported modifier\n"); 201 return false; 202 } 203 204 info = drm_format_info(format); 205 206 if (info->num_planes != 1) { 207 DRM_DEBUG_KMS("AFBC buffers expect one plane\n"); 208 return false; 209 } 210 211 if (malidp_hw_format_is_linear_only(format) == true) { 212 DRM_DEBUG_KMS("Given format (0x%x) is supported is linear mode only\n", 213 format); 214 return false; 215 } 216 217 /* 218 * RGB formats need to provide YTR modifier and YUV formats should not 219 * provide YTR modifier. 220 */ 221 if (!(info->is_yuv) != !!(modifier & AFBC_FORMAT_MOD_YTR)) { 222 DRM_DEBUG_KMS("AFBC_FORMAT_MOD_YTR is %s for %s formats\n", 223 info->is_yuv ? "disallowed" : "mandatory", 224 info->is_yuv ? "YUV" : "RGB"); 225 return false; 226 } 227 228 if (modifier & AFBC_SPLIT) { 229 if (!info->is_yuv) { 230 if (drm_format_plane_cpp(format, 0) <= 2) { 231 DRM_DEBUG_KMS("RGB formats <= 16bpp are not supported with SPLIT\n"); 232 return false; 233 } 234 } 235 236 if ((info->hsub != 1) || (info->vsub != 1)) { 237 if (!(format == DRM_FORMAT_YUV420_10BIT && 238 (map->features & MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT))) { 239 DRM_DEBUG_KMS("Formats which are sub-sampled should never be split\n"); 240 return false; 241 } 242 } 243 } 244 245 if (modifier & AFBC_CBR) { 246 if ((info->hsub == 1) || (info->vsub == 1)) { 247 DRM_DEBUG_KMS("Formats which are not sub-sampled should not have CBR set\n"); 248 return false; 249 } 250 } 251 252 return true; 253 } 254 255 static bool malidp_format_mod_supported_per_plane(struct drm_plane *plane, 256 u32 format, u64 modifier) 257 { 258 return malidp_format_mod_supported(plane->dev, format, modifier); 259 } 260 261 static const struct drm_plane_funcs malidp_de_plane_funcs = { 262 .update_plane = drm_atomic_helper_update_plane, 263 .disable_plane = drm_atomic_helper_disable_plane, 264 .destroy = malidp_de_plane_destroy, 265 .reset = malidp_plane_reset, 266 .atomic_duplicate_state = malidp_duplicate_plane_state, 267 .atomic_destroy_state = malidp_destroy_plane_state, 268 .atomic_print_state = malidp_plane_atomic_print_state, 269 .format_mod_supported = malidp_format_mod_supported_per_plane, 270 }; 271 272 static int malidp_se_check_scaling(struct malidp_plane *mp, 273 struct drm_plane_state *state) 274 { 275 struct drm_crtc_state *crtc_state = 276 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 277 struct malidp_crtc_state *mc; 278 u32 src_w, src_h; 279 int ret; 280 281 if (!crtc_state) 282 return -EINVAL; 283 284 mc = to_malidp_crtc_state(crtc_state); 285 286 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 287 0, INT_MAX, true, true); 288 if (ret) 289 return ret; 290 291 if (state->rotation & MALIDP_ROTATED_MASK) { 292 src_w = state->src_h >> 16; 293 src_h = state->src_w >> 16; 294 } else { 295 src_w = state->src_w >> 16; 296 src_h = state->src_h >> 16; 297 } 298 299 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { 300 /* Scaling not necessary for this plane. */ 301 mc->scaled_planes_mask &= ~(mp->layer->id); 302 return 0; 303 } 304 305 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) 306 return -EINVAL; 307 308 mc->scaled_planes_mask |= mp->layer->id; 309 /* Defer scaling requirements calculation to the crtc check. */ 310 return 0; 311 } 312 313 static u32 malidp_get_pgsize_bitmap(struct malidp_plane *mp) 314 { 315 u32 pgsize_bitmap = 0; 316 317 if (iommu_present(&platform_bus_type)) { 318 struct iommu_domain *mmu_dom = 319 iommu_get_domain_for_dev(mp->base.dev->dev); 320 321 if (mmu_dom) 322 pgsize_bitmap = mmu_dom->pgsize_bitmap; 323 } 324 325 return pgsize_bitmap; 326 } 327 328 /* 329 * Check if the framebuffer is entirely made up of pages at least pgsize in 330 * size. Only a heuristic: assumes that each scatterlist entry has been aligned 331 * to the largest page size smaller than its length and that the MMU maps to 332 * the largest page size possible. 333 */ 334 static bool malidp_check_pages_threshold(struct malidp_plane_state *ms, 335 u32 pgsize) 336 { 337 int i; 338 339 for (i = 0; i < ms->n_planes; i++) { 340 struct drm_gem_object *obj; 341 struct drm_gem_cma_object *cma_obj; 342 struct sg_table *sgt; 343 struct scatterlist *sgl; 344 345 obj = drm_gem_fb_get_obj(ms->base.fb, i); 346 cma_obj = to_drm_gem_cma_obj(obj); 347 348 if (cma_obj->sgt) 349 sgt = cma_obj->sgt; 350 else 351 sgt = obj->dev->driver->gem_prime_get_sg_table(obj); 352 353 if (!sgt) 354 return false; 355 356 sgl = sgt->sgl; 357 358 while (sgl) { 359 if (sgl->length < pgsize) { 360 if (!cma_obj->sgt) 361 kfree(sgt); 362 return false; 363 } 364 365 sgl = sg_next(sgl); 366 } 367 if (!cma_obj->sgt) 368 kfree(sgt); 369 } 370 371 return true; 372 } 373 374 /* 375 * Check if it is possible to enable partial-frame MMU prefetch given the 376 * current format, AFBC state and rotation. 377 */ 378 static bool malidp_partial_prefetch_supported(u32 format, u64 modifier, 379 unsigned int rotation) 380 { 381 bool afbc, sparse; 382 383 /* rotation and horizontal flip not supported for partial prefetch */ 384 if (rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 385 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X)) 386 return false; 387 388 afbc = modifier & DRM_FORMAT_MOD_ARM_AFBC(0); 389 sparse = modifier & AFBC_FORMAT_MOD_SPARSE; 390 391 switch (format) { 392 case DRM_FORMAT_ARGB2101010: 393 case DRM_FORMAT_RGBA1010102: 394 case DRM_FORMAT_BGRA1010102: 395 case DRM_FORMAT_ARGB8888: 396 case DRM_FORMAT_RGBA8888: 397 case DRM_FORMAT_BGRA8888: 398 case DRM_FORMAT_XRGB8888: 399 case DRM_FORMAT_XBGR8888: 400 case DRM_FORMAT_RGBX8888: 401 case DRM_FORMAT_BGRX8888: 402 case DRM_FORMAT_RGB888: 403 case DRM_FORMAT_RGBA5551: 404 case DRM_FORMAT_RGB565: 405 /* always supported */ 406 return true; 407 408 case DRM_FORMAT_ABGR2101010: 409 case DRM_FORMAT_ABGR8888: 410 case DRM_FORMAT_ABGR1555: 411 case DRM_FORMAT_BGR565: 412 /* supported, but if AFBC then must be sparse mode */ 413 return (!afbc) || (afbc && sparse); 414 415 case DRM_FORMAT_BGR888: 416 /* supported, but not for AFBC */ 417 return !afbc; 418 419 case DRM_FORMAT_YUYV: 420 case DRM_FORMAT_UYVY: 421 case DRM_FORMAT_NV12: 422 case DRM_FORMAT_YUV420: 423 /* not supported */ 424 return false; 425 426 default: 427 return false; 428 } 429 } 430 431 /* 432 * Select the preferred MMU prefetch mode. Full-frame prefetch is preferred as 433 * long as the framebuffer is all large pages. Otherwise partial-frame prefetch 434 * is selected as long as it is supported for the current format. The selected 435 * page size for prefetch is returned in pgsize_bitmap. 436 */ 437 static enum mmu_prefetch_mode malidp_mmu_prefetch_select_mode 438 (struct malidp_plane_state *ms, u32 *pgsize_bitmap) 439 { 440 u32 pgsizes; 441 442 /* get the full-frame prefetch page size(s) supported by the MMU */ 443 pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_FULL_PGSIZES; 444 445 while (pgsizes) { 446 u32 largest_pgsize = 1 << __fls(pgsizes); 447 448 if (malidp_check_pages_threshold(ms, largest_pgsize)) { 449 *pgsize_bitmap = largest_pgsize; 450 return MALIDP_PREFETCH_MODE_FULL; 451 } 452 453 pgsizes -= largest_pgsize; 454 } 455 456 /* get the partial-frame prefetch page size(s) supported by the MMU */ 457 pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES; 458 459 if (malidp_partial_prefetch_supported(ms->base.fb->format->format, 460 ms->base.fb->modifier, 461 ms->base.rotation)) { 462 /* partial prefetch using the smallest page size */ 463 *pgsize_bitmap = 1 << __ffs(pgsizes); 464 return MALIDP_PREFETCH_MODE_PARTIAL; 465 } 466 *pgsize_bitmap = 0; 467 return MALIDP_PREFETCH_MODE_NONE; 468 } 469 470 static u32 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode, 471 u8 readahead, u8 n_planes, u32 pgsize) 472 { 473 u32 mmu_ctrl = 0; 474 475 if (mode != MALIDP_PREFETCH_MODE_NONE) { 476 mmu_ctrl |= MALIDP_MMU_CTRL_EN; 477 478 if (mode == MALIDP_PREFETCH_MODE_PARTIAL) { 479 mmu_ctrl |= MALIDP_MMU_CTRL_MODE; 480 mmu_ctrl |= MALIDP_MMU_CTRL_PP_NUM_REQ(readahead); 481 } 482 483 if (pgsize == SZ_64K || pgsize == SZ_2M) { 484 int i; 485 486 for (i = 0; i < n_planes; i++) 487 mmu_ctrl |= MALIDP_MMU_CTRL_PX_PS(i); 488 } 489 } 490 491 return mmu_ctrl; 492 } 493 494 static void malidp_de_prefetch_settings(struct malidp_plane *mp, 495 struct malidp_plane_state *ms) 496 { 497 if (!mp->layer->mmu_ctrl_offset) 498 return; 499 500 /* get the page sizes supported by the MMU */ 501 ms->mmu_prefetch_pgsize = malidp_get_pgsize_bitmap(mp); 502 ms->mmu_prefetch_mode = 503 malidp_mmu_prefetch_select_mode(ms, &ms->mmu_prefetch_pgsize); 504 } 505 506 static int malidp_de_plane_check(struct drm_plane *plane, 507 struct drm_plane_state *state) 508 { 509 struct malidp_plane *mp = to_malidp_plane(plane); 510 struct malidp_plane_state *ms = to_malidp_plane_state(state); 511 bool rotated = state->rotation & MALIDP_ROTATED_MASK; 512 struct drm_framebuffer *fb; 513 u16 pixel_alpha = state->pixel_blend_mode; 514 int i, ret; 515 unsigned int block_w, block_h; 516 517 if (!state->crtc || !state->fb) 518 return 0; 519 520 fb = state->fb; 521 522 ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, 523 mp->layer->id, fb->format->format, 524 !!fb->modifier); 525 if (ms->format == MALIDP_INVALID_FORMAT_ID) 526 return -EINVAL; 527 528 ms->n_planes = fb->format->num_planes; 529 for (i = 0; i < ms->n_planes; i++) { 530 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); 531 532 if (((fb->pitches[i] * drm_format_info_block_height(fb->format, i)) 533 & (alignment - 1)) && !(fb->modifier)) { 534 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 535 fb->pitches[i], i); 536 return -EINVAL; 537 } 538 } 539 540 block_w = drm_format_info_block_width(fb->format, 0); 541 block_h = drm_format_info_block_height(fb->format, 0); 542 if (fb->width % block_w || fb->height % block_h) { 543 DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes"); 544 return -EINVAL; 545 } 546 if ((state->src_x >> 16) % block_w || (state->src_y >> 16) % block_h) { 547 DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes"); 548 return -EINVAL; 549 } 550 551 if ((state->crtc_w > mp->hwdev->max_line_size) || 552 (state->crtc_h > mp->hwdev->max_line_size) || 553 (state->crtc_w < mp->hwdev->min_line_size) || 554 (state->crtc_h < mp->hwdev->min_line_size)) 555 return -EINVAL; 556 557 /* 558 * DP550/650 video layers can accept 3 plane formats only if 559 * fb->pitches[1] == fb->pitches[2] since they don't have a 560 * third plane stride register. 561 */ 562 if (ms->n_planes == 3 && 563 !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 564 (state->fb->pitches[1] != state->fb->pitches[2])) 565 return -EINVAL; 566 567 ret = malidp_se_check_scaling(mp, state); 568 if (ret) 569 return ret; 570 571 /* validate the rotation constraints for each layer */ 572 if (state->rotation != DRM_MODE_ROTATE_0) { 573 if (mp->layer->rot == ROTATE_NONE) 574 return -EINVAL; 575 if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier)) 576 return -EINVAL; 577 /* 578 * packed RGB888 / BGR888 can't be rotated or flipped 579 * unless they are stored in a compressed way 580 */ 581 if ((fb->format->format == DRM_FORMAT_RGB888 || 582 fb->format->format == DRM_FORMAT_BGR888) && !(fb->modifier)) 583 return -EINVAL; 584 } 585 586 /* SMART layer does not support AFBC */ 587 if (mp->layer->id == DE_SMART && fb->modifier) { 588 DRM_ERROR("AFBC framebuffer not supported in SMART layer"); 589 return -EINVAL; 590 } 591 592 ms->rotmem_size = 0; 593 if (state->rotation & MALIDP_ROTATED_MASK) { 594 int val; 595 596 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, 597 state->crtc_h, 598 fb->format->format, 599 !!(fb->modifier)); 600 if (val < 0) 601 return val; 602 603 ms->rotmem_size = val; 604 } 605 606 /* HW can't support plane + pixel blending */ 607 if ((state->alpha != DRM_BLEND_ALPHA_OPAQUE) && 608 (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) && 609 fb->format->has_alpha) 610 return -EINVAL; 611 612 malidp_de_prefetch_settings(mp, ms); 613 614 return 0; 615 } 616 617 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 618 int num_planes, unsigned int pitches[3]) 619 { 620 int i; 621 int num_strides = num_planes; 622 623 if (!mp->layer->stride_offset) 624 return; 625 626 if (num_planes == 3) 627 num_strides = (mp->hwdev->hw->features & 628 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 629 630 /* 631 * The drm convention for pitch is that it needs to cover width * cpp, 632 * but our hardware wants the pitch/stride to cover all rows included 633 * in a tile. 634 */ 635 for (i = 0; i < num_strides; ++i) { 636 unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i); 637 638 malidp_hw_write(mp->hwdev, pitches[i] * block_h, 639 mp->layer->base + 640 mp->layer->stride_offset + i * 4); 641 } 642 } 643 644 static const s16 645 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = { 646 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 647 1192, 0, 1634, 648 1192, -401, -832, 649 1192, 2066, 0, 650 64, 512, 512 651 }, 652 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 653 1024, 0, 1436, 654 1024, -352, -731, 655 1024, 1815, 0, 656 0, 512, 512 657 }, 658 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 659 1192, 0, 1836, 660 1192, -218, -546, 661 1192, 2163, 0, 662 64, 512, 512 663 }, 664 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 665 1024, 0, 1613, 666 1024, -192, -479, 667 1024, 1900, 0, 668 0, 512, 512 669 }, 670 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 671 1024, 0, 1476, 672 1024, -165, -572, 673 1024, 1884, 0, 674 0, 512, 512 675 }, 676 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = { 677 1024, 0, 1510, 678 1024, -168, -585, 679 1024, 1927, 0, 680 0, 512, 512 681 } 682 }; 683 684 static void malidp_de_set_color_encoding(struct malidp_plane *plane, 685 enum drm_color_encoding enc, 686 enum drm_color_range range) 687 { 688 unsigned int i; 689 690 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) { 691 /* coefficients are signed, two's complement values */ 692 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], 693 plane->layer->base + plane->layer->yuv2rgb_offset + 694 i * 4); 695 } 696 } 697 698 static void malidp_de_set_mmu_control(struct malidp_plane *mp, 699 struct malidp_plane_state *ms) 700 { 701 u32 mmu_ctrl; 702 703 /* check hardware supports MMU prefetch */ 704 if (!mp->layer->mmu_ctrl_offset) 705 return; 706 707 mmu_ctrl = malidp_calc_mmu_control_value(ms->mmu_prefetch_mode, 708 MALIDP_MMU_PREFETCH_READAHEAD, 709 ms->n_planes, 710 ms->mmu_prefetch_pgsize); 711 712 malidp_hw_write(mp->hwdev, mmu_ctrl, 713 mp->layer->base + mp->layer->mmu_ctrl_offset); 714 } 715 716 static void malidp_set_plane_base_addr(struct drm_framebuffer *fb, 717 struct malidp_plane *mp, 718 int plane_index) 719 { 720 dma_addr_t paddr; 721 u16 ptr; 722 struct drm_plane *plane = &mp->base; 723 bool afbc = fb->modifier ? true : false; 724 725 ptr = mp->layer->ptr + (plane_index << 4); 726 727 /* 728 * drm_fb_cma_get_gem_addr() alters the physical base address of the 729 * framebuffer as per the plane's src_x, src_y co-ordinates (ie to 730 * take care of source cropping). 731 * For AFBC, this is not needed as the cropping is handled by _AD_CROP_H 732 * and _AD_CROP_V registers. 733 */ 734 if (!afbc) { 735 paddr = drm_fb_cma_get_gem_addr(fb, plane->state, 736 plane_index); 737 } else { 738 struct drm_gem_cma_object *obj; 739 740 obj = drm_fb_cma_get_gem_obj(fb, plane_index); 741 742 if (WARN_ON(!obj)) 743 return; 744 paddr = obj->paddr; 745 } 746 747 malidp_hw_write(mp->hwdev, lower_32_bits(paddr), ptr); 748 malidp_hw_write(mp->hwdev, upper_32_bits(paddr), ptr + 4); 749 } 750 751 static void malidp_de_set_plane_afbc(struct drm_plane *plane) 752 { 753 struct malidp_plane *mp; 754 u32 src_w, src_h, val = 0, src_x, src_y; 755 struct drm_framebuffer *fb = plane->state->fb; 756 757 mp = to_malidp_plane(plane); 758 759 /* no afbc_decoder_offset means AFBC is not supported on this plane */ 760 if (!mp->layer->afbc_decoder_offset) 761 return; 762 763 if (!fb->modifier) { 764 malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset); 765 return; 766 } 767 768 /* convert src values from Q16 fixed point to integer */ 769 src_w = plane->state->src_w >> 16; 770 src_h = plane->state->src_h >> 16; 771 src_x = plane->state->src_x >> 16; 772 src_y = plane->state->src_y >> 16; 773 774 val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) | 775 src_x; 776 malidp_hw_write(mp->hwdev, val, 777 mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_H); 778 779 val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) | 780 src_y; 781 malidp_hw_write(mp->hwdev, val, 782 mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_V); 783 784 val = MALIDP_AD_EN; 785 if (fb->modifier & AFBC_FORMAT_MOD_SPLIT) 786 val |= MALIDP_AD_BS; 787 if (fb->modifier & AFBC_FORMAT_MOD_YTR) 788 val |= MALIDP_AD_YTR; 789 790 malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset); 791 } 792 793 static void malidp_de_plane_update(struct drm_plane *plane, 794 struct drm_plane_state *old_state) 795 { 796 struct malidp_plane *mp; 797 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 798 struct drm_plane_state *state = plane->state; 799 u16 pixel_alpha = state->pixel_blend_mode; 800 u8 plane_alpha = state->alpha >> 8; 801 u32 src_w, src_h, dest_w, dest_h, val; 802 int i; 803 struct drm_framebuffer *fb = plane->state->fb; 804 805 mp = to_malidp_plane(plane); 806 807 /* 808 * For AFBC framebuffer, use the framebuffer width and height for 809 * configuring layer input size register. 810 */ 811 if (fb->modifier) { 812 src_w = fb->width; 813 src_h = fb->height; 814 } else { 815 /* convert src values from Q16 fixed point to integer */ 816 src_w = state->src_w >> 16; 817 src_h = state->src_h >> 16; 818 } 819 820 dest_w = state->crtc_w; 821 dest_h = state->crtc_h; 822 823 val = malidp_hw_read(mp->hwdev, mp->layer->base); 824 val = (val & ~LAYER_FORMAT_MASK) | ms->format; 825 malidp_hw_write(mp->hwdev, val, mp->layer->base); 826 827 for (i = 0; i < ms->n_planes; i++) 828 malidp_set_plane_base_addr(fb, mp, i); 829 830 malidp_de_set_mmu_control(mp, ms); 831 832 malidp_de_set_plane_pitches(mp, ms->n_planes, 833 state->fb->pitches); 834 835 if ((plane->state->color_encoding != old_state->color_encoding) || 836 (plane->state->color_range != old_state->color_range)) 837 malidp_de_set_color_encoding(mp, plane->state->color_encoding, 838 plane->state->color_range); 839 840 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 841 mp->layer->base + MALIDP_LAYER_SIZE); 842 843 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 844 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 845 846 malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) | 847 LAYER_V_VAL(state->crtc_y), 848 mp->layer->base + MALIDP_LAYER_OFFSET); 849 850 if (mp->layer->id == DE_SMART) { 851 /* 852 * Enable the first rectangle in the SMART layer to be 853 * able to use it as a drm plane. 854 */ 855 malidp_hw_write(mp->hwdev, 1, 856 mp->layer->base + MALIDP550_LS_ENABLE); 857 malidp_hw_write(mp->hwdev, 858 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 859 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 860 } 861 862 malidp_de_set_plane_afbc(plane); 863 864 /* first clear the rotation bits */ 865 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 866 val &= ~LAYER_ROT_MASK; 867 868 /* setup the rotation and axis flip bits */ 869 if (state->rotation & DRM_MODE_ROTATE_MASK) 870 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << 871 LAYER_ROT_OFFSET; 872 if (state->rotation & DRM_MODE_REFLECT_X) 873 val |= LAYER_H_FLIP; 874 if (state->rotation & DRM_MODE_REFLECT_Y) 875 val |= LAYER_V_FLIP; 876 877 val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff)); 878 879 if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) { 880 val |= LAYER_COMP_PLANE; 881 } else if (state->fb->format->has_alpha) { 882 /* We only care about blend mode if the format has alpha */ 883 switch (pixel_alpha) { 884 case DRM_MODE_BLEND_PREMULTI: 885 val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE; 886 break; 887 case DRM_MODE_BLEND_COVERAGE: 888 val |= LAYER_COMP_PIXEL; 889 break; 890 } 891 } 892 val |= LAYER_ALPHA(plane_alpha); 893 894 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); 895 if (state->crtc) { 896 struct malidp_crtc_state *m = 897 to_malidp_crtc_state(state->crtc->state); 898 899 if (m->scaler_config.scale_enable && 900 m->scaler_config.plane_src_id == mp->layer->id) 901 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); 902 } 903 904 /* set the 'enable layer' bit */ 905 val |= LAYER_ENABLE; 906 907 malidp_hw_write(mp->hwdev, val, 908 mp->layer->base + MALIDP_LAYER_CONTROL); 909 } 910 911 static void malidp_de_plane_disable(struct drm_plane *plane, 912 struct drm_plane_state *state) 913 { 914 struct malidp_plane *mp = to_malidp_plane(plane); 915 916 malidp_hw_clearbits(mp->hwdev, 917 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), 918 mp->layer->base + MALIDP_LAYER_CONTROL); 919 } 920 921 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 922 .atomic_check = malidp_de_plane_check, 923 .atomic_update = malidp_de_plane_update, 924 .atomic_disable = malidp_de_plane_disable, 925 }; 926 927 int malidp_de_planes_init(struct drm_device *drm) 928 { 929 struct malidp_drm *malidp = drm->dev_private; 930 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 931 struct malidp_plane *plane = NULL; 932 enum drm_plane_type plane_type; 933 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 934 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 935 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 936 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 937 BIT(DRM_MODE_BLEND_PREMULTI) | 938 BIT(DRM_MODE_BLEND_COVERAGE); 939 u32 *formats; 940 int ret, i = 0, j = 0, n; 941 u64 supported_modifiers[MODIFIERS_COUNT_MAX]; 942 const u64 *modifiers; 943 944 modifiers = malidp_format_modifiers; 945 946 if (!(map->features & MALIDP_DEVICE_AFBC_SUPPORT_SPLIT)) { 947 /* 948 * Since our hardware does not support SPLIT, so build the list 949 * of supported modifiers excluding SPLIT ones. 950 */ 951 while (*modifiers != DRM_FORMAT_MOD_INVALID) { 952 if (!(*modifiers & AFBC_SPLIT)) 953 supported_modifiers[j++] = *modifiers; 954 955 modifiers++; 956 } 957 supported_modifiers[j++] = DRM_FORMAT_MOD_INVALID; 958 modifiers = supported_modifiers; 959 } 960 961 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 962 if (!formats) { 963 ret = -ENOMEM; 964 goto cleanup; 965 } 966 967 for (i = 0; i < map->n_layers; i++) { 968 u8 id = map->layers[i].id; 969 970 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 971 if (!plane) { 972 ret = -ENOMEM; 973 goto cleanup; 974 } 975 976 /* build the list of DRM supported formats based on the map */ 977 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 978 if ((map->pixel_formats[j].layer & id) == id) 979 formats[n++] = map->pixel_formats[j].format; 980 } 981 982 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 983 DRM_PLANE_TYPE_OVERLAY; 984 985 /* 986 * All the layers except smart layer supports AFBC modifiers. 987 */ 988 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 989 &malidp_de_plane_funcs, formats, n, 990 (id == DE_SMART) ? NULL : modifiers, plane_type, 991 NULL); 992 993 if (ret < 0) 994 goto cleanup; 995 996 drm_plane_helper_add(&plane->base, 997 &malidp_de_plane_helper_funcs); 998 plane->hwdev = malidp->dev; 999 plane->layer = &map->layers[i]; 1000 1001 drm_plane_create_alpha_property(&plane->base); 1002 drm_plane_create_blend_mode_property(&plane->base, blend_caps); 1003 1004 if (id == DE_SMART) { 1005 /* Skip the features which the SMART layer doesn't have. */ 1006 continue; 1007 } 1008 1009 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); 1010 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 1011 plane->layer->base + MALIDP_LAYER_COMPOSE); 1012 1013 /* Attach the YUV->RGB property only to video layers */ 1014 if (id & (DE_VIDEO1 | DE_VIDEO2)) { 1015 /* default encoding for YUV->RGB is BT601 NARROW */ 1016 enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; 1017 enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; 1018 1019 ret = drm_plane_create_color_properties(&plane->base, 1020 BIT(DRM_COLOR_YCBCR_BT601) | \ 1021 BIT(DRM_COLOR_YCBCR_BT709) | \ 1022 BIT(DRM_COLOR_YCBCR_BT2020), 1023 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ 1024 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1025 enc, range); 1026 if (!ret) 1027 /* program the HW registers */ 1028 malidp_de_set_color_encoding(plane, enc, range); 1029 else 1030 DRM_WARN("Failed to create video layer %d color properties\n", id); 1031 } 1032 } 1033 1034 kfree(formats); 1035 1036 return 0; 1037 1038 cleanup: 1039 kfree(formats); 1040 1041 return ret; 1042 } 1043