1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_fb_cma_helper.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_plane_helper.h> 19 #include <drm/drm_print.h> 20 21 #include "malidp_hw.h" 22 #include "malidp_drv.h" 23 24 /* Layer specific register offsets */ 25 #define MALIDP_LAYER_FORMAT 0x000 26 #define MALIDP_LAYER_CONTROL 0x004 27 #define LAYER_ENABLE (1 << 0) 28 #define LAYER_FLOWCFG_MASK 7 29 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) 30 #define LAYER_FLOWCFG_SCALE_SE 3 31 #define LAYER_ROT_OFFSET 8 32 #define LAYER_H_FLIP (1 << 10) 33 #define LAYER_V_FLIP (1 << 11) 34 #define LAYER_ROT_MASK (0xf << 8) 35 #define LAYER_COMP_MASK (0x3 << 12) 36 #define LAYER_COMP_PIXEL (0x3 << 12) 37 #define LAYER_COMP_PLANE (0x2 << 12) 38 #define MALIDP_LAYER_COMPOSE 0x008 39 #define MALIDP_LAYER_SIZE 0x00c 40 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 41 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 42 #define MALIDP_LAYER_COMP_SIZE 0x010 43 #define MALIDP_LAYER_OFFSET 0x014 44 #define MALIDP550_LS_ENABLE 0x01c 45 #define MALIDP550_LS_R1_IN_SIZE 0x020 46 47 /* 48 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 49 * for formats with 1- or 2-bit alpha channels. 50 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 51 * opacity for 2-bit formats. 52 */ 53 #define MALIDP_ALPHA_LUT 0xffaa5500 54 55 static void malidp_de_plane_destroy(struct drm_plane *plane) 56 { 57 struct malidp_plane *mp = to_malidp_plane(plane); 58 59 if (mp->base.fb) 60 drm_framebuffer_unreference(mp->base.fb); 61 62 drm_plane_helper_disable(plane); 63 drm_plane_cleanup(plane); 64 devm_kfree(plane->dev->dev, mp); 65 } 66 67 /* 68 * Replicate what the default ->reset hook does: free the state pointer and 69 * allocate a new empty object. We just need enough space to store 70 * a malidp_plane_state instead of a drm_plane_state. 71 */ 72 static void malidp_plane_reset(struct drm_plane *plane) 73 { 74 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); 75 76 if (state) 77 __drm_atomic_helper_plane_destroy_state(&state->base); 78 kfree(state); 79 plane->state = NULL; 80 state = kzalloc(sizeof(*state), GFP_KERNEL); 81 if (state) { 82 state->base.plane = plane; 83 state->base.rotation = DRM_MODE_ROTATE_0; 84 plane->state = &state->base; 85 } 86 } 87 88 static struct 89 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 90 { 91 struct malidp_plane_state *state, *m_state; 92 93 if (!plane->state) 94 return NULL; 95 96 state = kmalloc(sizeof(*state), GFP_KERNEL); 97 if (!state) 98 return NULL; 99 100 m_state = to_malidp_plane_state(plane->state); 101 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 102 state->rotmem_size = m_state->rotmem_size; 103 state->format = m_state->format; 104 state->n_planes = m_state->n_planes; 105 106 return &state->base; 107 } 108 109 static void malidp_destroy_plane_state(struct drm_plane *plane, 110 struct drm_plane_state *state) 111 { 112 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 113 114 __drm_atomic_helper_plane_destroy_state(state); 115 kfree(m_state); 116 } 117 118 static void malidp_plane_atomic_print_state(struct drm_printer *p, 119 const struct drm_plane_state *state) 120 { 121 struct malidp_plane_state *ms = to_malidp_plane_state(state); 122 123 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); 124 drm_printf(p, "\tformat_id=%u\n", ms->format); 125 drm_printf(p, "\tn_planes=%u\n", ms->n_planes); 126 } 127 128 static const struct drm_plane_funcs malidp_de_plane_funcs = { 129 .update_plane = drm_atomic_helper_update_plane, 130 .disable_plane = drm_atomic_helper_disable_plane, 131 .set_property = drm_atomic_helper_plane_set_property, 132 .destroy = malidp_de_plane_destroy, 133 .reset = malidp_plane_reset, 134 .atomic_duplicate_state = malidp_duplicate_plane_state, 135 .atomic_destroy_state = malidp_destroy_plane_state, 136 .atomic_print_state = malidp_plane_atomic_print_state, 137 }; 138 139 static int malidp_se_check_scaling(struct malidp_plane *mp, 140 struct drm_plane_state *state) 141 { 142 struct drm_crtc_state *crtc_state = 143 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 144 struct malidp_crtc_state *mc; 145 struct drm_rect clip = { 0 }; 146 u32 src_w, src_h; 147 int ret; 148 149 if (!crtc_state) 150 return -EINVAL; 151 152 clip.x2 = crtc_state->adjusted_mode.hdisplay; 153 clip.y2 = crtc_state->adjusted_mode.vdisplay; 154 ret = drm_plane_helper_check_state(state, &clip, 0, INT_MAX, true, true); 155 if (ret) 156 return ret; 157 158 src_w = state->src_w >> 16; 159 src_h = state->src_h >> 16; 160 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { 161 /* Scaling not necessary for this plane. */ 162 mc->scaled_planes_mask &= ~(mp->layer->id); 163 return 0; 164 } 165 166 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) 167 return -EINVAL; 168 169 mc = to_malidp_crtc_state(crtc_state); 170 171 mc->scaled_planes_mask |= mp->layer->id; 172 /* Defer scaling requirements calculation to the crtc check. */ 173 return 0; 174 } 175 176 static int malidp_de_plane_check(struct drm_plane *plane, 177 struct drm_plane_state *state) 178 { 179 struct malidp_plane *mp = to_malidp_plane(plane); 180 struct malidp_plane_state *ms = to_malidp_plane_state(state); 181 struct drm_framebuffer *fb; 182 int i, ret; 183 184 if (!state->crtc || !state->fb) 185 return 0; 186 187 fb = state->fb; 188 189 ms->format = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id, 190 fb->format->format); 191 if (ms->format == MALIDP_INVALID_FORMAT_ID) 192 return -EINVAL; 193 194 ms->n_planes = fb->format->num_planes; 195 for (i = 0; i < ms->n_planes; i++) { 196 if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) { 197 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 198 fb->pitches[i], i); 199 return -EINVAL; 200 } 201 } 202 203 if ((state->crtc_w > mp->hwdev->max_line_size) || 204 (state->crtc_h > mp->hwdev->max_line_size) || 205 (state->crtc_w < mp->hwdev->min_line_size) || 206 (state->crtc_h < mp->hwdev->min_line_size)) 207 return -EINVAL; 208 209 /* 210 * DP550/650 video layers can accept 3 plane formats only if 211 * fb->pitches[1] == fb->pitches[2] since they don't have a 212 * third plane stride register. 213 */ 214 if (ms->n_planes == 3 && 215 !(mp->hwdev->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 216 (state->fb->pitches[1] != state->fb->pitches[2])) 217 return -EINVAL; 218 219 ret = malidp_se_check_scaling(mp, state); 220 if (ret) 221 return ret; 222 223 /* packed RGB888 / BGR888 can't be rotated or flipped */ 224 if (state->rotation != DRM_MODE_ROTATE_0 && 225 (fb->format->format == DRM_FORMAT_RGB888 || 226 fb->format->format == DRM_FORMAT_BGR888)) 227 return -EINVAL; 228 229 ms->rotmem_size = 0; 230 if (state->rotation & MALIDP_ROTATED_MASK) { 231 int val; 232 233 val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h, 234 state->crtc_w, 235 fb->format->format); 236 if (val < 0) 237 return val; 238 239 ms->rotmem_size = val; 240 } 241 242 return 0; 243 } 244 245 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 246 int num_planes, unsigned int pitches[3]) 247 { 248 int i; 249 int num_strides = num_planes; 250 251 if (!mp->layer->stride_offset) 252 return; 253 254 if (num_planes == 3) 255 num_strides = (mp->hwdev->features & 256 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 257 258 for (i = 0; i < num_strides; ++i) 259 malidp_hw_write(mp->hwdev, pitches[i], 260 mp->layer->base + 261 mp->layer->stride_offset + i * 4); 262 } 263 264 static void malidp_de_plane_update(struct drm_plane *plane, 265 struct drm_plane_state *old_state) 266 { 267 struct malidp_plane *mp; 268 const struct malidp_hw_regmap *map; 269 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 270 u32 src_w, src_h, dest_w, dest_h, val; 271 int i; 272 273 mp = to_malidp_plane(plane); 274 map = &mp->hwdev->map; 275 276 /* convert src values from Q16 fixed point to integer */ 277 src_w = plane->state->src_w >> 16; 278 src_h = plane->state->src_h >> 16; 279 dest_w = plane->state->crtc_w; 280 dest_h = plane->state->crtc_h; 281 282 malidp_hw_write(mp->hwdev, ms->format, mp->layer->base); 283 284 for (i = 0; i < ms->n_planes; i++) { 285 /* calculate the offset for the layer's plane registers */ 286 u16 ptr = mp->layer->ptr + (i << 4); 287 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb, 288 plane->state, i); 289 290 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr); 291 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4); 292 } 293 malidp_de_set_plane_pitches(mp, ms->n_planes, 294 plane->state->fb->pitches); 295 296 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 297 mp->layer->base + MALIDP_LAYER_SIZE); 298 299 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 300 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 301 302 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) | 303 LAYER_V_VAL(plane->state->crtc_y), 304 mp->layer->base + MALIDP_LAYER_OFFSET); 305 306 if (mp->layer->id == DE_SMART) 307 malidp_hw_write(mp->hwdev, 308 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 309 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 310 311 /* first clear the rotation bits */ 312 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 313 val &= ~LAYER_ROT_MASK; 314 315 /* setup the rotation and axis flip bits */ 316 if (plane->state->rotation & DRM_MODE_ROTATE_MASK) 317 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << 318 LAYER_ROT_OFFSET; 319 if (plane->state->rotation & DRM_MODE_REFLECT_X) 320 val |= LAYER_H_FLIP; 321 if (plane->state->rotation & DRM_MODE_REFLECT_Y) 322 val |= LAYER_V_FLIP; 323 324 /* 325 * always enable pixel alpha blending until we have a way to change 326 * blend modes 327 */ 328 val &= ~LAYER_COMP_MASK; 329 val |= LAYER_COMP_PIXEL; 330 331 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); 332 if (plane->state->crtc) { 333 struct malidp_crtc_state *m = 334 to_malidp_crtc_state(plane->state->crtc->state); 335 336 if (m->scaler_config.scale_enable && 337 m->scaler_config.plane_src_id == mp->layer->id) 338 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); 339 } 340 341 /* set the 'enable layer' bit */ 342 val |= LAYER_ENABLE; 343 344 malidp_hw_write(mp->hwdev, val, 345 mp->layer->base + MALIDP_LAYER_CONTROL); 346 } 347 348 static void malidp_de_plane_disable(struct drm_plane *plane, 349 struct drm_plane_state *state) 350 { 351 struct malidp_plane *mp = to_malidp_plane(plane); 352 353 malidp_hw_clearbits(mp->hwdev, 354 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), 355 mp->layer->base + MALIDP_LAYER_CONTROL); 356 } 357 358 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 359 .atomic_check = malidp_de_plane_check, 360 .atomic_update = malidp_de_plane_update, 361 .atomic_disable = malidp_de_plane_disable, 362 }; 363 364 int malidp_de_planes_init(struct drm_device *drm) 365 { 366 struct malidp_drm *malidp = drm->dev_private; 367 const struct malidp_hw_regmap *map = &malidp->dev->map; 368 struct malidp_plane *plane = NULL; 369 enum drm_plane_type plane_type; 370 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 371 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 372 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 373 u32 *formats; 374 int ret, i, j, n; 375 376 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 377 if (!formats) { 378 ret = -ENOMEM; 379 goto cleanup; 380 } 381 382 for (i = 0; i < map->n_layers; i++) { 383 u8 id = map->layers[i].id; 384 385 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 386 if (!plane) { 387 ret = -ENOMEM; 388 goto cleanup; 389 } 390 391 /* build the list of DRM supported formats based on the map */ 392 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 393 if ((map->pixel_formats[j].layer & id) == id) 394 formats[n++] = map->pixel_formats[j].format; 395 } 396 397 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 398 DRM_PLANE_TYPE_OVERLAY; 399 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 400 &malidp_de_plane_funcs, formats, 401 n, plane_type, NULL); 402 if (ret < 0) 403 goto cleanup; 404 405 drm_plane_helper_add(&plane->base, 406 &malidp_de_plane_helper_funcs); 407 plane->hwdev = malidp->dev; 408 plane->layer = &map->layers[i]; 409 410 if (id == DE_SMART) { 411 /* 412 * Enable the first rectangle in the SMART layer to be 413 * able to use it as a drm plane. 414 */ 415 malidp_hw_write(malidp->dev, 1, 416 plane->layer->base + MALIDP550_LS_ENABLE); 417 /* Skip the features which the SMART layer doesn't have. */ 418 continue; 419 } 420 421 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); 422 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 423 plane->layer->base + MALIDP_LAYER_COMPOSE); 424 } 425 426 kfree(formats); 427 428 return 0; 429 430 cleanup: 431 malidp_de_planes_destroy(drm); 432 kfree(formats); 433 434 return ret; 435 } 436 437 void malidp_de_planes_destroy(struct drm_device *drm) 438 { 439 struct drm_plane *p, *pt; 440 441 list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) { 442 drm_plane_cleanup(p); 443 kfree(p); 444 } 445 } 446