1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_fb_cma_helper.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_plane_helper.h> 19 #include <drm/drm_print.h> 20 21 #include "malidp_hw.h" 22 #include "malidp_drv.h" 23 24 /* Layer specific register offsets */ 25 #define MALIDP_LAYER_FORMAT 0x000 26 #define MALIDP_LAYER_CONTROL 0x004 27 #define LAYER_ENABLE (1 << 0) 28 #define LAYER_FLOWCFG_MASK 7 29 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) 30 #define LAYER_FLOWCFG_SCALE_SE 3 31 #define LAYER_ROT_OFFSET 8 32 #define LAYER_H_FLIP (1 << 10) 33 #define LAYER_V_FLIP (1 << 11) 34 #define LAYER_ROT_MASK (0xf << 8) 35 #define LAYER_COMP_MASK (0x3 << 12) 36 #define LAYER_COMP_PIXEL (0x3 << 12) 37 #define LAYER_COMP_PLANE (0x2 << 12) 38 #define LAYER_ALPHA_OFFSET (16) 39 #define LAYER_ALPHA_MASK (0xff) 40 #define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) 41 #define MALIDP_LAYER_COMPOSE 0x008 42 #define MALIDP_LAYER_SIZE 0x00c 43 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 44 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 45 #define MALIDP_LAYER_COMP_SIZE 0x010 46 #define MALIDP_LAYER_OFFSET 0x014 47 #define MALIDP550_LS_ENABLE 0x01c 48 #define MALIDP550_LS_R1_IN_SIZE 0x020 49 50 /* 51 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 52 * for formats with 1- or 2-bit alpha channels. 53 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 54 * opacity for 2-bit formats. 55 */ 56 #define MALIDP_ALPHA_LUT 0xffaa5500 57 58 static void malidp_de_plane_destroy(struct drm_plane *plane) 59 { 60 struct malidp_plane *mp = to_malidp_plane(plane); 61 62 drm_plane_cleanup(plane); 63 kfree(mp); 64 } 65 66 /* 67 * Replicate what the default ->reset hook does: free the state pointer and 68 * allocate a new empty object. We just need enough space to store 69 * a malidp_plane_state instead of a drm_plane_state. 70 */ 71 static void malidp_plane_reset(struct drm_plane *plane) 72 { 73 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); 74 75 if (state) 76 __drm_atomic_helper_plane_destroy_state(&state->base); 77 kfree(state); 78 plane->state = NULL; 79 state = kzalloc(sizeof(*state), GFP_KERNEL); 80 if (state) { 81 state->base.plane = plane; 82 state->base.rotation = DRM_MODE_ROTATE_0; 83 plane->state = &state->base; 84 } 85 } 86 87 static struct 88 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 89 { 90 struct malidp_plane_state *state, *m_state; 91 92 if (!plane->state) 93 return NULL; 94 95 state = kmalloc(sizeof(*state), GFP_KERNEL); 96 if (!state) 97 return NULL; 98 99 m_state = to_malidp_plane_state(plane->state); 100 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 101 state->rotmem_size = m_state->rotmem_size; 102 state->format = m_state->format; 103 state->n_planes = m_state->n_planes; 104 105 return &state->base; 106 } 107 108 static void malidp_destroy_plane_state(struct drm_plane *plane, 109 struct drm_plane_state *state) 110 { 111 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 112 113 __drm_atomic_helper_plane_destroy_state(state); 114 kfree(m_state); 115 } 116 117 static void malidp_plane_atomic_print_state(struct drm_printer *p, 118 const struct drm_plane_state *state) 119 { 120 struct malidp_plane_state *ms = to_malidp_plane_state(state); 121 122 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); 123 drm_printf(p, "\tformat_id=%u\n", ms->format); 124 drm_printf(p, "\tn_planes=%u\n", ms->n_planes); 125 } 126 127 static const struct drm_plane_funcs malidp_de_plane_funcs = { 128 .update_plane = drm_atomic_helper_update_plane, 129 .disable_plane = drm_atomic_helper_disable_plane, 130 .destroy = malidp_de_plane_destroy, 131 .reset = malidp_plane_reset, 132 .atomic_duplicate_state = malidp_duplicate_plane_state, 133 .atomic_destroy_state = malidp_destroy_plane_state, 134 .atomic_print_state = malidp_plane_atomic_print_state, 135 }; 136 137 static int malidp_se_check_scaling(struct malidp_plane *mp, 138 struct drm_plane_state *state) 139 { 140 struct drm_crtc_state *crtc_state = 141 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 142 struct malidp_crtc_state *mc; 143 u32 src_w, src_h; 144 int ret; 145 146 if (!crtc_state) 147 return -EINVAL; 148 149 mc = to_malidp_crtc_state(crtc_state); 150 151 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 152 0, INT_MAX, true, true); 153 if (ret) 154 return ret; 155 156 if (state->rotation & MALIDP_ROTATED_MASK) { 157 src_w = state->src_h >> 16; 158 src_h = state->src_w >> 16; 159 } else { 160 src_w = state->src_w >> 16; 161 src_h = state->src_h >> 16; 162 } 163 164 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { 165 /* Scaling not necessary for this plane. */ 166 mc->scaled_planes_mask &= ~(mp->layer->id); 167 return 0; 168 } 169 170 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) 171 return -EINVAL; 172 173 mc->scaled_planes_mask |= mp->layer->id; 174 /* Defer scaling requirements calculation to the crtc check. */ 175 return 0; 176 } 177 178 static int malidp_de_plane_check(struct drm_plane *plane, 179 struct drm_plane_state *state) 180 { 181 struct malidp_plane *mp = to_malidp_plane(plane); 182 struct malidp_plane_state *ms = to_malidp_plane_state(state); 183 bool rotated = state->rotation & MALIDP_ROTATED_MASK; 184 struct drm_framebuffer *fb; 185 int i, ret; 186 187 if (!state->crtc || !state->fb) 188 return 0; 189 190 fb = state->fb; 191 192 ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, 193 mp->layer->id, 194 fb->format->format); 195 if (ms->format == MALIDP_INVALID_FORMAT_ID) 196 return -EINVAL; 197 198 ms->n_planes = fb->format->num_planes; 199 for (i = 0; i < ms->n_planes; i++) { 200 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); 201 if (fb->pitches[i] & (alignment - 1)) { 202 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 203 fb->pitches[i], i); 204 return -EINVAL; 205 } 206 } 207 208 if ((state->crtc_w > mp->hwdev->max_line_size) || 209 (state->crtc_h > mp->hwdev->max_line_size) || 210 (state->crtc_w < mp->hwdev->min_line_size) || 211 (state->crtc_h < mp->hwdev->min_line_size)) 212 return -EINVAL; 213 214 /* 215 * DP550/650 video layers can accept 3 plane formats only if 216 * fb->pitches[1] == fb->pitches[2] since they don't have a 217 * third plane stride register. 218 */ 219 if (ms->n_planes == 3 && 220 !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 221 (state->fb->pitches[1] != state->fb->pitches[2])) 222 return -EINVAL; 223 224 ret = malidp_se_check_scaling(mp, state); 225 if (ret) 226 return ret; 227 228 /* packed RGB888 / BGR888 can't be rotated or flipped */ 229 if (state->rotation != DRM_MODE_ROTATE_0 && 230 (fb->format->format == DRM_FORMAT_RGB888 || 231 fb->format->format == DRM_FORMAT_BGR888)) 232 return -EINVAL; 233 234 ms->rotmem_size = 0; 235 if (state->rotation & MALIDP_ROTATED_MASK) { 236 int val; 237 238 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h, 239 state->crtc_w, 240 fb->format->format); 241 if (val < 0) 242 return val; 243 244 ms->rotmem_size = val; 245 } 246 247 return 0; 248 } 249 250 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 251 int num_planes, unsigned int pitches[3]) 252 { 253 int i; 254 int num_strides = num_planes; 255 256 if (!mp->layer->stride_offset) 257 return; 258 259 if (num_planes == 3) 260 num_strides = (mp->hwdev->hw->features & 261 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 262 263 for (i = 0; i < num_strides; ++i) 264 malidp_hw_write(mp->hwdev, pitches[i], 265 mp->layer->base + 266 mp->layer->stride_offset + i * 4); 267 } 268 269 static const s16 270 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = { 271 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 272 1192, 0, 1634, 273 1192, -401, -832, 274 1192, 2066, 0, 275 64, 512, 512 276 }, 277 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 278 1024, 0, 1436, 279 1024, -352, -731, 280 1024, 1815, 0, 281 0, 512, 512 282 }, 283 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 284 1192, 0, 1836, 285 1192, -218, -546, 286 1192, 2163, 0, 287 64, 512, 512 288 }, 289 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 290 1024, 0, 1613, 291 1024, -192, -479, 292 1024, 1900, 0, 293 0, 512, 512 294 }, 295 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 296 1024, 0, 1476, 297 1024, -165, -572, 298 1024, 1884, 0, 299 0, 512, 512 300 }, 301 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = { 302 1024, 0, 1510, 303 1024, -168, -585, 304 1024, 1927, 0, 305 0, 512, 512 306 } 307 }; 308 309 static void malidp_de_set_color_encoding(struct malidp_plane *plane, 310 enum drm_color_encoding enc, 311 enum drm_color_range range) 312 { 313 unsigned int i; 314 315 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) { 316 /* coefficients are signed, two's complement values */ 317 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], 318 plane->layer->base + plane->layer->yuv2rgb_offset + 319 i * 4); 320 } 321 } 322 323 static void malidp_de_plane_update(struct drm_plane *plane, 324 struct drm_plane_state *old_state) 325 { 326 struct malidp_plane *mp; 327 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 328 u32 src_w, src_h, dest_w, dest_h, val; 329 int i; 330 bool format_has_alpha = plane->state->fb->format->has_alpha; 331 332 mp = to_malidp_plane(plane); 333 334 /* convert src values from Q16 fixed point to integer */ 335 src_w = plane->state->src_w >> 16; 336 src_h = plane->state->src_h >> 16; 337 dest_w = plane->state->crtc_w; 338 dest_h = plane->state->crtc_h; 339 340 malidp_hw_write(mp->hwdev, ms->format, mp->layer->base); 341 342 for (i = 0; i < ms->n_planes; i++) { 343 /* calculate the offset for the layer's plane registers */ 344 u16 ptr = mp->layer->ptr + (i << 4); 345 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb, 346 plane->state, i); 347 348 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr); 349 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4); 350 } 351 malidp_de_set_plane_pitches(mp, ms->n_planes, 352 plane->state->fb->pitches); 353 354 if ((plane->state->color_encoding != old_state->color_encoding) || 355 (plane->state->color_range != old_state->color_range)) 356 malidp_de_set_color_encoding(mp, plane->state->color_encoding, 357 plane->state->color_range); 358 359 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 360 mp->layer->base + MALIDP_LAYER_SIZE); 361 362 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 363 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 364 365 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) | 366 LAYER_V_VAL(plane->state->crtc_y), 367 mp->layer->base + MALIDP_LAYER_OFFSET); 368 369 if (mp->layer->id == DE_SMART) 370 malidp_hw_write(mp->hwdev, 371 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 372 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 373 374 /* first clear the rotation bits */ 375 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 376 val &= ~LAYER_ROT_MASK; 377 378 /* setup the rotation and axis flip bits */ 379 if (plane->state->rotation & DRM_MODE_ROTATE_MASK) 380 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << 381 LAYER_ROT_OFFSET; 382 if (plane->state->rotation & DRM_MODE_REFLECT_X) 383 val |= LAYER_H_FLIP; 384 if (plane->state->rotation & DRM_MODE_REFLECT_Y) 385 val |= LAYER_V_FLIP; 386 387 val &= ~LAYER_COMP_MASK; 388 if (format_has_alpha) { 389 390 /* 391 * always enable pixel alpha blending until we have a way 392 * to change blend modes 393 */ 394 val |= LAYER_COMP_PIXEL; 395 } else { 396 397 /* 398 * do not enable pixel alpha blending as the color channel 399 * does not have any alpha information 400 */ 401 val |= LAYER_COMP_PLANE; 402 403 /* Set layer alpha coefficient to 0xff ie fully opaque */ 404 val |= LAYER_ALPHA(0xff); 405 } 406 407 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); 408 if (plane->state->crtc) { 409 struct malidp_crtc_state *m = 410 to_malidp_crtc_state(plane->state->crtc->state); 411 412 if (m->scaler_config.scale_enable && 413 m->scaler_config.plane_src_id == mp->layer->id) 414 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); 415 } 416 417 /* set the 'enable layer' bit */ 418 val |= LAYER_ENABLE; 419 420 malidp_hw_write(mp->hwdev, val, 421 mp->layer->base + MALIDP_LAYER_CONTROL); 422 } 423 424 static void malidp_de_plane_disable(struct drm_plane *plane, 425 struct drm_plane_state *state) 426 { 427 struct malidp_plane *mp = to_malidp_plane(plane); 428 429 malidp_hw_clearbits(mp->hwdev, 430 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), 431 mp->layer->base + MALIDP_LAYER_CONTROL); 432 } 433 434 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 435 .atomic_check = malidp_de_plane_check, 436 .atomic_update = malidp_de_plane_update, 437 .atomic_disable = malidp_de_plane_disable, 438 }; 439 440 int malidp_de_planes_init(struct drm_device *drm) 441 { 442 struct malidp_drm *malidp = drm->dev_private; 443 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 444 struct malidp_plane *plane = NULL; 445 enum drm_plane_type plane_type; 446 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 447 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 448 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 449 u32 *formats; 450 int ret, i, j, n; 451 452 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 453 if (!formats) { 454 ret = -ENOMEM; 455 goto cleanup; 456 } 457 458 for (i = 0; i < map->n_layers; i++) { 459 u8 id = map->layers[i].id; 460 461 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 462 if (!plane) { 463 ret = -ENOMEM; 464 goto cleanup; 465 } 466 467 /* build the list of DRM supported formats based on the map */ 468 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 469 if ((map->pixel_formats[j].layer & id) == id) 470 formats[n++] = map->pixel_formats[j].format; 471 } 472 473 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 474 DRM_PLANE_TYPE_OVERLAY; 475 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 476 &malidp_de_plane_funcs, formats, 477 n, NULL, plane_type, NULL); 478 if (ret < 0) 479 goto cleanup; 480 481 drm_plane_helper_add(&plane->base, 482 &malidp_de_plane_helper_funcs); 483 plane->hwdev = malidp->dev; 484 plane->layer = &map->layers[i]; 485 486 if (id == DE_SMART) { 487 /* 488 * Enable the first rectangle in the SMART layer to be 489 * able to use it as a drm plane. 490 */ 491 malidp_hw_write(malidp->dev, 1, 492 plane->layer->base + MALIDP550_LS_ENABLE); 493 /* Skip the features which the SMART layer doesn't have. */ 494 continue; 495 } 496 497 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); 498 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 499 plane->layer->base + MALIDP_LAYER_COMPOSE); 500 501 /* Attach the YUV->RGB property only to video layers */ 502 if (id & (DE_VIDEO1 | DE_VIDEO2)) { 503 /* default encoding for YUV->RGB is BT601 NARROW */ 504 enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; 505 enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; 506 507 ret = drm_plane_create_color_properties(&plane->base, 508 BIT(DRM_COLOR_YCBCR_BT601) | \ 509 BIT(DRM_COLOR_YCBCR_BT709) | \ 510 BIT(DRM_COLOR_YCBCR_BT2020), 511 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ 512 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 513 enc, range); 514 if (!ret) 515 /* program the HW registers */ 516 malidp_de_set_color_encoding(plane, enc, range); 517 else 518 DRM_WARN("Failed to create video layer %d color properties\n", id); 519 } 520 } 521 522 kfree(formats); 523 524 return 0; 525 526 cleanup: 527 kfree(formats); 528 529 return ret; 530 } 531