1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_fb_cma_helper.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_plane_helper.h> 19 20 #include "malidp_hw.h" 21 #include "malidp_drv.h" 22 23 /* Layer specific register offsets */ 24 #define MALIDP_LAYER_FORMAT 0x000 25 #define MALIDP_LAYER_CONTROL 0x004 26 #define LAYER_ENABLE (1 << 0) 27 #define LAYER_ROT_OFFSET 8 28 #define LAYER_H_FLIP (1 << 10) 29 #define LAYER_V_FLIP (1 << 11) 30 #define LAYER_ROT_MASK (0xf << 8) 31 #define LAYER_COMP_MASK (0x3 << 12) 32 #define LAYER_COMP_PIXEL (0x3 << 12) 33 #define LAYER_COMP_PLANE (0x2 << 12) 34 #define MALIDP_LAYER_COMPOSE 0x008 35 #define MALIDP_LAYER_SIZE 0x00c 36 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 37 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 38 #define MALIDP_LAYER_COMP_SIZE 0x010 39 #define MALIDP_LAYER_OFFSET 0x014 40 41 /* 42 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 43 * for formats with 1- or 2-bit alpha channels. 44 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 45 * opacity for 2-bit formats. 46 */ 47 #define MALIDP_ALPHA_LUT 0xffaa5500 48 49 static void malidp_de_plane_destroy(struct drm_plane *plane) 50 { 51 struct malidp_plane *mp = to_malidp_plane(plane); 52 53 if (mp->base.fb) 54 drm_framebuffer_unreference(mp->base.fb); 55 56 drm_plane_helper_disable(plane); 57 drm_plane_cleanup(plane); 58 devm_kfree(plane->dev->dev, mp); 59 } 60 61 static struct 62 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 63 { 64 struct malidp_plane_state *state, *m_state; 65 66 if (!plane->state) 67 return NULL; 68 69 state = kmalloc(sizeof(*state), GFP_KERNEL); 70 if (!state) 71 return NULL; 72 73 m_state = to_malidp_plane_state(plane->state); 74 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 75 state->rotmem_size = m_state->rotmem_size; 76 state->format = m_state->format; 77 state->n_planes = m_state->n_planes; 78 79 return &state->base; 80 } 81 82 static void malidp_destroy_plane_state(struct drm_plane *plane, 83 struct drm_plane_state *state) 84 { 85 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 86 87 __drm_atomic_helper_plane_destroy_state(state); 88 kfree(m_state); 89 } 90 91 static const struct drm_plane_funcs malidp_de_plane_funcs = { 92 .update_plane = drm_atomic_helper_update_plane, 93 .disable_plane = drm_atomic_helper_disable_plane, 94 .set_property = drm_atomic_helper_plane_set_property, 95 .destroy = malidp_de_plane_destroy, 96 .reset = drm_atomic_helper_plane_reset, 97 .atomic_duplicate_state = malidp_duplicate_plane_state, 98 .atomic_destroy_state = malidp_destroy_plane_state, 99 }; 100 101 static int malidp_de_plane_check(struct drm_plane *plane, 102 struct drm_plane_state *state) 103 { 104 struct malidp_plane *mp = to_malidp_plane(plane); 105 struct malidp_plane_state *ms = to_malidp_plane_state(state); 106 struct drm_crtc_state *crtc_state; 107 struct drm_framebuffer *fb; 108 struct drm_rect clip = { 0 }; 109 int i, ret; 110 u32 src_w, src_h; 111 112 if (!state->crtc || !state->fb) 113 return 0; 114 115 fb = state->fb; 116 117 ms->format = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id, 118 fb->format->format); 119 if (ms->format == MALIDP_INVALID_FORMAT_ID) 120 return -EINVAL; 121 122 ms->n_planes = fb->format->num_planes; 123 for (i = 0; i < ms->n_planes; i++) { 124 if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) { 125 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 126 fb->pitches[i], i); 127 return -EINVAL; 128 } 129 } 130 131 src_w = state->src_w >> 16; 132 src_h = state->src_h >> 16; 133 134 if ((state->crtc_w > mp->hwdev->max_line_size) || 135 (state->crtc_h > mp->hwdev->max_line_size) || 136 (state->crtc_w < mp->hwdev->min_line_size) || 137 (state->crtc_h < mp->hwdev->min_line_size)) 138 return -EINVAL; 139 140 /* 141 * DP550/650 video layers can accept 3 plane formats only if 142 * fb->pitches[1] == fb->pitches[2] since they don't have a 143 * third plane stride register. 144 */ 145 if (ms->n_planes == 3 && 146 !(mp->hwdev->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 147 (state->fb->pitches[1] != state->fb->pitches[2])) 148 return -EINVAL; 149 150 /* packed RGB888 / BGR888 can't be rotated or flipped */ 151 if (state->rotation != DRM_ROTATE_0 && 152 (fb->format->format == DRM_FORMAT_RGB888 || 153 fb->format->format == DRM_FORMAT_BGR888)) 154 return -EINVAL; 155 156 crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc); 157 clip.x2 = crtc_state->adjusted_mode.hdisplay; 158 clip.y2 = crtc_state->adjusted_mode.vdisplay; 159 ret = drm_plane_helper_check_state(state, &clip, 160 DRM_PLANE_HELPER_NO_SCALING, 161 DRM_PLANE_HELPER_NO_SCALING, 162 true, true); 163 if (ret) 164 return ret; 165 166 ms->rotmem_size = 0; 167 if (state->rotation & MALIDP_ROTATED_MASK) { 168 int val; 169 170 val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h, 171 state->crtc_w, 172 fb->format->format); 173 if (val < 0) 174 return val; 175 176 ms->rotmem_size = val; 177 } 178 179 return 0; 180 } 181 182 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 183 int num_planes, unsigned int pitches[3]) 184 { 185 int i; 186 int num_strides = num_planes; 187 188 if (!mp->layer->stride_offset) 189 return; 190 191 if (num_planes == 3) 192 num_strides = (mp->hwdev->features & 193 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 194 195 for (i = 0; i < num_strides; ++i) 196 malidp_hw_write(mp->hwdev, pitches[i], 197 mp->layer->base + 198 mp->layer->stride_offset + i * 4); 199 } 200 201 static void malidp_de_plane_update(struct drm_plane *plane, 202 struct drm_plane_state *old_state) 203 { 204 struct drm_gem_cma_object *obj; 205 struct malidp_plane *mp; 206 const struct malidp_hw_regmap *map; 207 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 208 u16 ptr; 209 u32 src_w, src_h, dest_w, dest_h, val; 210 int i; 211 212 mp = to_malidp_plane(plane); 213 map = &mp->hwdev->map; 214 215 /* convert src values from Q16 fixed point to integer */ 216 src_w = plane->state->src_w >> 16; 217 src_h = plane->state->src_h >> 16; 218 dest_w = plane->state->crtc_w; 219 dest_h = plane->state->crtc_h; 220 221 malidp_hw_write(mp->hwdev, ms->format, mp->layer->base); 222 223 for (i = 0; i < ms->n_planes; i++) { 224 /* calculate the offset for the layer's plane registers */ 225 ptr = mp->layer->ptr + (i << 4); 226 227 obj = drm_fb_cma_get_gem_obj(plane->state->fb, i); 228 obj->paddr += plane->state->fb->offsets[i]; 229 malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr); 230 malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4); 231 } 232 malidp_de_set_plane_pitches(mp, ms->n_planes, 233 plane->state->fb->pitches); 234 235 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 236 mp->layer->base + MALIDP_LAYER_SIZE); 237 238 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 239 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 240 241 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) | 242 LAYER_V_VAL(plane->state->crtc_y), 243 mp->layer->base + MALIDP_LAYER_OFFSET); 244 245 /* first clear the rotation bits */ 246 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 247 val &= ~LAYER_ROT_MASK; 248 249 /* setup the rotation and axis flip bits */ 250 if (plane->state->rotation & DRM_ROTATE_MASK) 251 val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) << 252 LAYER_ROT_OFFSET; 253 if (plane->state->rotation & DRM_REFLECT_X) 254 val |= LAYER_H_FLIP; 255 if (plane->state->rotation & DRM_REFLECT_Y) 256 val |= LAYER_V_FLIP; 257 258 /* 259 * always enable pixel alpha blending until we have a way to change 260 * blend modes 261 */ 262 val &= ~LAYER_COMP_MASK; 263 val |= LAYER_COMP_PIXEL; 264 265 /* set the 'enable layer' bit */ 266 val |= LAYER_ENABLE; 267 268 malidp_hw_write(mp->hwdev, val, 269 mp->layer->base + MALIDP_LAYER_CONTROL); 270 } 271 272 static void malidp_de_plane_disable(struct drm_plane *plane, 273 struct drm_plane_state *state) 274 { 275 struct malidp_plane *mp = to_malidp_plane(plane); 276 277 malidp_hw_clearbits(mp->hwdev, LAYER_ENABLE, 278 mp->layer->base + MALIDP_LAYER_CONTROL); 279 } 280 281 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 282 .atomic_check = malidp_de_plane_check, 283 .atomic_update = malidp_de_plane_update, 284 .atomic_disable = malidp_de_plane_disable, 285 }; 286 287 int malidp_de_planes_init(struct drm_device *drm) 288 { 289 struct malidp_drm *malidp = drm->dev_private; 290 const struct malidp_hw_regmap *map = &malidp->dev->map; 291 struct malidp_plane *plane = NULL; 292 enum drm_plane_type plane_type; 293 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 294 unsigned long flags = DRM_ROTATE_0 | DRM_ROTATE_90 | DRM_ROTATE_180 | 295 DRM_ROTATE_270 | DRM_REFLECT_X | DRM_REFLECT_Y; 296 u32 *formats; 297 int ret, i, j, n; 298 299 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 300 if (!formats) { 301 ret = -ENOMEM; 302 goto cleanup; 303 } 304 305 for (i = 0; i < map->n_layers; i++) { 306 u8 id = map->layers[i].id; 307 308 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 309 if (!plane) { 310 ret = -ENOMEM; 311 goto cleanup; 312 } 313 314 /* build the list of DRM supported formats based on the map */ 315 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 316 if ((map->pixel_formats[j].layer & id) == id) 317 formats[n++] = map->pixel_formats[j].format; 318 } 319 320 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 321 DRM_PLANE_TYPE_OVERLAY; 322 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 323 &malidp_de_plane_funcs, formats, 324 n, plane_type, NULL); 325 if (ret < 0) 326 goto cleanup; 327 328 drm_plane_helper_add(&plane->base, 329 &malidp_de_plane_helper_funcs); 330 plane->hwdev = malidp->dev; 331 plane->layer = &map->layers[i]; 332 333 /* Skip the features which the SMART layer doesn't have */ 334 if (id == DE_SMART) 335 continue; 336 337 drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags); 338 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 339 plane->layer->base + MALIDP_LAYER_COMPOSE); 340 } 341 342 kfree(formats); 343 344 return 0; 345 346 cleanup: 347 malidp_de_planes_destroy(drm); 348 kfree(formats); 349 350 return ret; 351 } 352 353 void malidp_de_planes_destroy(struct drm_device *drm) 354 { 355 struct drm_plane *p, *pt; 356 357 list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) { 358 drm_plane_cleanup(p); 359 kfree(p); 360 } 361 } 362