1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_fb_cma_helper.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_plane_helper.h> 19 #include <drm/drm_print.h> 20 21 #include "malidp_hw.h" 22 #include "malidp_drv.h" 23 24 /* Layer specific register offsets */ 25 #define MALIDP_LAYER_FORMAT 0x000 26 #define LAYER_FORMAT_MASK 0x3f 27 #define MALIDP_LAYER_CONTROL 0x004 28 #define LAYER_ENABLE (1 << 0) 29 #define LAYER_FLOWCFG_MASK 7 30 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) 31 #define LAYER_FLOWCFG_SCALE_SE 3 32 #define LAYER_ROT_OFFSET 8 33 #define LAYER_H_FLIP (1 << 10) 34 #define LAYER_V_FLIP (1 << 11) 35 #define LAYER_ROT_MASK (0xf << 8) 36 #define LAYER_COMP_MASK (0x3 << 12) 37 #define LAYER_COMP_PIXEL (0x3 << 12) 38 #define LAYER_COMP_PLANE (0x2 << 12) 39 #define LAYER_ALPHA_OFFSET (16) 40 #define LAYER_ALPHA_MASK (0xff) 41 #define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) 42 #define MALIDP_LAYER_COMPOSE 0x008 43 #define MALIDP_LAYER_SIZE 0x00c 44 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 45 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 46 #define MALIDP_LAYER_COMP_SIZE 0x010 47 #define MALIDP_LAYER_OFFSET 0x014 48 #define MALIDP550_LS_ENABLE 0x01c 49 #define MALIDP550_LS_R1_IN_SIZE 0x020 50 51 /* 52 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 53 * for formats with 1- or 2-bit alpha channels. 54 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 55 * opacity for 2-bit formats. 56 */ 57 #define MALIDP_ALPHA_LUT 0xffaa5500 58 59 static void malidp_de_plane_destroy(struct drm_plane *plane) 60 { 61 struct malidp_plane *mp = to_malidp_plane(plane); 62 63 drm_plane_cleanup(plane); 64 kfree(mp); 65 } 66 67 /* 68 * Replicate what the default ->reset hook does: free the state pointer and 69 * allocate a new empty object. We just need enough space to store 70 * a malidp_plane_state instead of a drm_plane_state. 71 */ 72 static void malidp_plane_reset(struct drm_plane *plane) 73 { 74 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); 75 76 if (state) 77 __drm_atomic_helper_plane_destroy_state(&state->base); 78 kfree(state); 79 plane->state = NULL; 80 state = kzalloc(sizeof(*state), GFP_KERNEL); 81 if (state) 82 __drm_atomic_helper_plane_reset(plane, &state->base); 83 } 84 85 static struct 86 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 87 { 88 struct malidp_plane_state *state, *m_state; 89 90 if (!plane->state) 91 return NULL; 92 93 state = kmalloc(sizeof(*state), GFP_KERNEL); 94 if (!state) 95 return NULL; 96 97 m_state = to_malidp_plane_state(plane->state); 98 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 99 state->rotmem_size = m_state->rotmem_size; 100 state->format = m_state->format; 101 state->n_planes = m_state->n_planes; 102 103 return &state->base; 104 } 105 106 static void malidp_destroy_plane_state(struct drm_plane *plane, 107 struct drm_plane_state *state) 108 { 109 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 110 111 __drm_atomic_helper_plane_destroy_state(state); 112 kfree(m_state); 113 } 114 115 static void malidp_plane_atomic_print_state(struct drm_printer *p, 116 const struct drm_plane_state *state) 117 { 118 struct malidp_plane_state *ms = to_malidp_plane_state(state); 119 120 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); 121 drm_printf(p, "\tformat_id=%u\n", ms->format); 122 drm_printf(p, "\tn_planes=%u\n", ms->n_planes); 123 } 124 125 static const struct drm_plane_funcs malidp_de_plane_funcs = { 126 .update_plane = drm_atomic_helper_update_plane, 127 .disable_plane = drm_atomic_helper_disable_plane, 128 .destroy = malidp_de_plane_destroy, 129 .reset = malidp_plane_reset, 130 .atomic_duplicate_state = malidp_duplicate_plane_state, 131 .atomic_destroy_state = malidp_destroy_plane_state, 132 .atomic_print_state = malidp_plane_atomic_print_state, 133 }; 134 135 static int malidp_se_check_scaling(struct malidp_plane *mp, 136 struct drm_plane_state *state) 137 { 138 struct drm_crtc_state *crtc_state = 139 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 140 struct malidp_crtc_state *mc; 141 u32 src_w, src_h; 142 int ret; 143 144 if (!crtc_state) 145 return -EINVAL; 146 147 mc = to_malidp_crtc_state(crtc_state); 148 149 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 150 0, INT_MAX, true, true); 151 if (ret) 152 return ret; 153 154 if (state->rotation & MALIDP_ROTATED_MASK) { 155 src_w = state->src_h >> 16; 156 src_h = state->src_w >> 16; 157 } else { 158 src_w = state->src_w >> 16; 159 src_h = state->src_h >> 16; 160 } 161 162 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { 163 /* Scaling not necessary for this plane. */ 164 mc->scaled_planes_mask &= ~(mp->layer->id); 165 return 0; 166 } 167 168 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) 169 return -EINVAL; 170 171 mc->scaled_planes_mask |= mp->layer->id; 172 /* Defer scaling requirements calculation to the crtc check. */ 173 return 0; 174 } 175 176 static int malidp_de_plane_check(struct drm_plane *plane, 177 struct drm_plane_state *state) 178 { 179 struct malidp_plane *mp = to_malidp_plane(plane); 180 struct malidp_plane_state *ms = to_malidp_plane_state(state); 181 bool rotated = state->rotation & MALIDP_ROTATED_MASK; 182 struct drm_framebuffer *fb; 183 int i, ret; 184 185 if (!state->crtc || !state->fb) 186 return 0; 187 188 fb = state->fb; 189 190 ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, 191 mp->layer->id, 192 fb->format->format); 193 if (ms->format == MALIDP_INVALID_FORMAT_ID) 194 return -EINVAL; 195 196 ms->n_planes = fb->format->num_planes; 197 for (i = 0; i < ms->n_planes; i++) { 198 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); 199 if (fb->pitches[i] & (alignment - 1)) { 200 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 201 fb->pitches[i], i); 202 return -EINVAL; 203 } 204 } 205 206 if ((state->crtc_w > mp->hwdev->max_line_size) || 207 (state->crtc_h > mp->hwdev->max_line_size) || 208 (state->crtc_w < mp->hwdev->min_line_size) || 209 (state->crtc_h < mp->hwdev->min_line_size)) 210 return -EINVAL; 211 212 /* 213 * DP550/650 video layers can accept 3 plane formats only if 214 * fb->pitches[1] == fb->pitches[2] since they don't have a 215 * third plane stride register. 216 */ 217 if (ms->n_planes == 3 && 218 !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 219 (state->fb->pitches[1] != state->fb->pitches[2])) 220 return -EINVAL; 221 222 ret = malidp_se_check_scaling(mp, state); 223 if (ret) 224 return ret; 225 226 /* packed RGB888 / BGR888 can't be rotated or flipped */ 227 if (state->rotation != DRM_MODE_ROTATE_0 && 228 (fb->format->format == DRM_FORMAT_RGB888 || 229 fb->format->format == DRM_FORMAT_BGR888)) 230 return -EINVAL; 231 232 ms->rotmem_size = 0; 233 if (state->rotation & MALIDP_ROTATED_MASK) { 234 int val; 235 236 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, 237 state->crtc_h, 238 fb->format->format); 239 if (val < 0) 240 return val; 241 242 ms->rotmem_size = val; 243 } 244 245 return 0; 246 } 247 248 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 249 int num_planes, unsigned int pitches[3]) 250 { 251 int i; 252 int num_strides = num_planes; 253 254 if (!mp->layer->stride_offset) 255 return; 256 257 if (num_planes == 3) 258 num_strides = (mp->hwdev->hw->features & 259 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 260 261 for (i = 0; i < num_strides; ++i) 262 malidp_hw_write(mp->hwdev, pitches[i], 263 mp->layer->base + 264 mp->layer->stride_offset + i * 4); 265 } 266 267 static const s16 268 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = { 269 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 270 1192, 0, 1634, 271 1192, -401, -832, 272 1192, 2066, 0, 273 64, 512, 512 274 }, 275 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 276 1024, 0, 1436, 277 1024, -352, -731, 278 1024, 1815, 0, 279 0, 512, 512 280 }, 281 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 282 1192, 0, 1836, 283 1192, -218, -546, 284 1192, 2163, 0, 285 64, 512, 512 286 }, 287 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 288 1024, 0, 1613, 289 1024, -192, -479, 290 1024, 1900, 0, 291 0, 512, 512 292 }, 293 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 294 1024, 0, 1476, 295 1024, -165, -572, 296 1024, 1884, 0, 297 0, 512, 512 298 }, 299 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = { 300 1024, 0, 1510, 301 1024, -168, -585, 302 1024, 1927, 0, 303 0, 512, 512 304 } 305 }; 306 307 static void malidp_de_set_color_encoding(struct malidp_plane *plane, 308 enum drm_color_encoding enc, 309 enum drm_color_range range) 310 { 311 unsigned int i; 312 313 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) { 314 /* coefficients are signed, two's complement values */ 315 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], 316 plane->layer->base + plane->layer->yuv2rgb_offset + 317 i * 4); 318 } 319 } 320 321 static void malidp_de_plane_update(struct drm_plane *plane, 322 struct drm_plane_state *old_state) 323 { 324 struct malidp_plane *mp; 325 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 326 u32 src_w, src_h, dest_w, dest_h, val; 327 int i; 328 bool format_has_alpha = plane->state->fb->format->has_alpha; 329 330 mp = to_malidp_plane(plane); 331 332 /* convert src values from Q16 fixed point to integer */ 333 src_w = plane->state->src_w >> 16; 334 src_h = plane->state->src_h >> 16; 335 dest_w = plane->state->crtc_w; 336 dest_h = plane->state->crtc_h; 337 338 val = malidp_hw_read(mp->hwdev, mp->layer->base); 339 val = (val & ~LAYER_FORMAT_MASK) | ms->format; 340 malidp_hw_write(mp->hwdev, val, mp->layer->base); 341 342 for (i = 0; i < ms->n_planes; i++) { 343 /* calculate the offset for the layer's plane registers */ 344 u16 ptr = mp->layer->ptr + (i << 4); 345 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb, 346 plane->state, i); 347 348 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr); 349 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4); 350 } 351 malidp_de_set_plane_pitches(mp, ms->n_planes, 352 plane->state->fb->pitches); 353 354 if ((plane->state->color_encoding != old_state->color_encoding) || 355 (plane->state->color_range != old_state->color_range)) 356 malidp_de_set_color_encoding(mp, plane->state->color_encoding, 357 plane->state->color_range); 358 359 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 360 mp->layer->base + MALIDP_LAYER_SIZE); 361 362 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 363 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 364 365 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) | 366 LAYER_V_VAL(plane->state->crtc_y), 367 mp->layer->base + MALIDP_LAYER_OFFSET); 368 369 if (mp->layer->id == DE_SMART) 370 malidp_hw_write(mp->hwdev, 371 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 372 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 373 374 /* first clear the rotation bits */ 375 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 376 val &= ~LAYER_ROT_MASK; 377 378 /* setup the rotation and axis flip bits */ 379 if (plane->state->rotation & DRM_MODE_ROTATE_MASK) 380 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << 381 LAYER_ROT_OFFSET; 382 if (plane->state->rotation & DRM_MODE_REFLECT_X) 383 val |= LAYER_H_FLIP; 384 if (plane->state->rotation & DRM_MODE_REFLECT_Y) 385 val |= LAYER_V_FLIP; 386 387 val &= ~LAYER_COMP_MASK; 388 if (format_has_alpha) { 389 390 /* 391 * always enable pixel alpha blending until we have a way 392 * to change blend modes 393 */ 394 val |= LAYER_COMP_PIXEL; 395 } else { 396 397 /* 398 * do not enable pixel alpha blending as the color channel 399 * does not have any alpha information 400 */ 401 val |= LAYER_COMP_PLANE; 402 403 /* Set layer alpha coefficient to 0xff ie fully opaque */ 404 val |= LAYER_ALPHA(0xff); 405 } 406 407 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); 408 if (plane->state->crtc) { 409 struct malidp_crtc_state *m = 410 to_malidp_crtc_state(plane->state->crtc->state); 411 412 if (m->scaler_config.scale_enable && 413 m->scaler_config.plane_src_id == mp->layer->id) 414 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); 415 } 416 417 /* set the 'enable layer' bit */ 418 val |= LAYER_ENABLE; 419 420 malidp_hw_write(mp->hwdev, val, 421 mp->layer->base + MALIDP_LAYER_CONTROL); 422 } 423 424 static void malidp_de_plane_disable(struct drm_plane *plane, 425 struct drm_plane_state *state) 426 { 427 struct malidp_plane *mp = to_malidp_plane(plane); 428 429 malidp_hw_clearbits(mp->hwdev, 430 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), 431 mp->layer->base + MALIDP_LAYER_CONTROL); 432 } 433 434 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 435 .atomic_check = malidp_de_plane_check, 436 .atomic_update = malidp_de_plane_update, 437 .atomic_disable = malidp_de_plane_disable, 438 }; 439 440 int malidp_de_planes_init(struct drm_device *drm) 441 { 442 struct malidp_drm *malidp = drm->dev_private; 443 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 444 struct malidp_plane *plane = NULL; 445 enum drm_plane_type plane_type; 446 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 447 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 448 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 449 u32 *formats; 450 int ret, i, j, n; 451 452 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 453 if (!formats) { 454 ret = -ENOMEM; 455 goto cleanup; 456 } 457 458 for (i = 0; i < map->n_layers; i++) { 459 u8 id = map->layers[i].id; 460 461 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 462 if (!plane) { 463 ret = -ENOMEM; 464 goto cleanup; 465 } 466 467 /* build the list of DRM supported formats based on the map */ 468 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 469 if ((map->pixel_formats[j].layer & id) == id) 470 formats[n++] = map->pixel_formats[j].format; 471 } 472 473 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 474 DRM_PLANE_TYPE_OVERLAY; 475 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 476 &malidp_de_plane_funcs, formats, 477 n, NULL, plane_type, NULL); 478 if (ret < 0) 479 goto cleanup; 480 481 drm_plane_helper_add(&plane->base, 482 &malidp_de_plane_helper_funcs); 483 plane->hwdev = malidp->dev; 484 plane->layer = &map->layers[i]; 485 486 if (id == DE_SMART) { 487 /* 488 * Enable the first rectangle in the SMART layer to be 489 * able to use it as a drm plane. 490 */ 491 malidp_hw_write(malidp->dev, 1, 492 plane->layer->base + MALIDP550_LS_ENABLE); 493 /* Skip the features which the SMART layer doesn't have. */ 494 continue; 495 } 496 497 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); 498 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 499 plane->layer->base + MALIDP_LAYER_COMPOSE); 500 501 /* Attach the YUV->RGB property only to video layers */ 502 if (id & (DE_VIDEO1 | DE_VIDEO2)) { 503 /* default encoding for YUV->RGB is BT601 NARROW */ 504 enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; 505 enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; 506 507 ret = drm_plane_create_color_properties(&plane->base, 508 BIT(DRM_COLOR_YCBCR_BT601) | \ 509 BIT(DRM_COLOR_YCBCR_BT709) | \ 510 BIT(DRM_COLOR_YCBCR_BT2020), 511 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ 512 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 513 enc, range); 514 if (!ret) 515 /* program the HW registers */ 516 malidp_de_set_color_encoding(plane, enc, range); 517 else 518 DRM_WARN("Failed to create video layer %d color properties\n", id); 519 } 520 } 521 522 kfree(formats); 523 524 return 0; 525 526 cleanup: 527 kfree(formats); 528 529 return ret; 530 } 531