1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_fb_cma_helper.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_plane_helper.h> 19 20 #include "malidp_hw.h" 21 #include "malidp_drv.h" 22 23 /* Layer specific register offsets */ 24 #define MALIDP_LAYER_FORMAT 0x000 25 #define MALIDP_LAYER_CONTROL 0x004 26 #define LAYER_ENABLE (1 << 0) 27 #define LAYER_ROT_OFFSET 8 28 #define LAYER_H_FLIP (1 << 10) 29 #define LAYER_V_FLIP (1 << 11) 30 #define LAYER_ROT_MASK (0xf << 8) 31 #define LAYER_COMP_MASK (0x3 << 12) 32 #define LAYER_COMP_PIXEL (0x3 << 12) 33 #define LAYER_COMP_PLANE (0x2 << 12) 34 #define MALIDP_LAYER_COMPOSE 0x008 35 #define MALIDP_LAYER_SIZE 0x00c 36 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 37 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 38 #define MALIDP_LAYER_COMP_SIZE 0x010 39 #define MALIDP_LAYER_OFFSET 0x014 40 #define MALIDP550_LS_ENABLE 0x01c 41 #define MALIDP550_LS_R1_IN_SIZE 0x020 42 43 /* 44 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 45 * for formats with 1- or 2-bit alpha channels. 46 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 47 * opacity for 2-bit formats. 48 */ 49 #define MALIDP_ALPHA_LUT 0xffaa5500 50 51 static void malidp_de_plane_destroy(struct drm_plane *plane) 52 { 53 struct malidp_plane *mp = to_malidp_plane(plane); 54 55 if (mp->base.fb) 56 drm_framebuffer_unreference(mp->base.fb); 57 58 drm_plane_helper_disable(plane); 59 drm_plane_cleanup(plane); 60 devm_kfree(plane->dev->dev, mp); 61 } 62 63 static struct 64 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 65 { 66 struct malidp_plane_state *state, *m_state; 67 68 if (!plane->state) 69 return NULL; 70 71 state = kmalloc(sizeof(*state), GFP_KERNEL); 72 if (!state) 73 return NULL; 74 75 m_state = to_malidp_plane_state(plane->state); 76 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 77 state->rotmem_size = m_state->rotmem_size; 78 state->format = m_state->format; 79 state->n_planes = m_state->n_planes; 80 81 return &state->base; 82 } 83 84 static void malidp_destroy_plane_state(struct drm_plane *plane, 85 struct drm_plane_state *state) 86 { 87 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 88 89 __drm_atomic_helper_plane_destroy_state(state); 90 kfree(m_state); 91 } 92 93 static const struct drm_plane_funcs malidp_de_plane_funcs = { 94 .update_plane = drm_atomic_helper_update_plane, 95 .disable_plane = drm_atomic_helper_disable_plane, 96 .set_property = drm_atomic_helper_plane_set_property, 97 .destroy = malidp_de_plane_destroy, 98 .reset = drm_atomic_helper_plane_reset, 99 .atomic_duplicate_state = malidp_duplicate_plane_state, 100 .atomic_destroy_state = malidp_destroy_plane_state, 101 }; 102 103 static int malidp_de_plane_check(struct drm_plane *plane, 104 struct drm_plane_state *state) 105 { 106 struct malidp_plane *mp = to_malidp_plane(plane); 107 struct malidp_plane_state *ms = to_malidp_plane_state(state); 108 struct drm_crtc_state *crtc_state; 109 struct drm_framebuffer *fb; 110 struct drm_rect clip = { 0 }; 111 int i, ret; 112 u32 src_w, src_h; 113 114 if (!state->crtc || !state->fb) 115 return 0; 116 117 fb = state->fb; 118 119 ms->format = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id, 120 fb->format->format); 121 if (ms->format == MALIDP_INVALID_FORMAT_ID) 122 return -EINVAL; 123 124 ms->n_planes = fb->format->num_planes; 125 for (i = 0; i < ms->n_planes; i++) { 126 if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) { 127 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 128 fb->pitches[i], i); 129 return -EINVAL; 130 } 131 } 132 133 src_w = state->src_w >> 16; 134 src_h = state->src_h >> 16; 135 136 if ((state->crtc_w > mp->hwdev->max_line_size) || 137 (state->crtc_h > mp->hwdev->max_line_size) || 138 (state->crtc_w < mp->hwdev->min_line_size) || 139 (state->crtc_h < mp->hwdev->min_line_size)) 140 return -EINVAL; 141 142 /* 143 * DP550/650 video layers can accept 3 plane formats only if 144 * fb->pitches[1] == fb->pitches[2] since they don't have a 145 * third plane stride register. 146 */ 147 if (ms->n_planes == 3 && 148 !(mp->hwdev->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 149 (state->fb->pitches[1] != state->fb->pitches[2])) 150 return -EINVAL; 151 152 /* packed RGB888 / BGR888 can't be rotated or flipped */ 153 if (state->rotation != DRM_ROTATE_0 && 154 (fb->format->format == DRM_FORMAT_RGB888 || 155 fb->format->format == DRM_FORMAT_BGR888)) 156 return -EINVAL; 157 158 crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc); 159 clip.x2 = crtc_state->adjusted_mode.hdisplay; 160 clip.y2 = crtc_state->adjusted_mode.vdisplay; 161 ret = drm_plane_helper_check_state(state, &clip, 162 DRM_PLANE_HELPER_NO_SCALING, 163 DRM_PLANE_HELPER_NO_SCALING, 164 true, true); 165 if (ret) 166 return ret; 167 168 ms->rotmem_size = 0; 169 if (state->rotation & MALIDP_ROTATED_MASK) { 170 int val; 171 172 val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h, 173 state->crtc_w, 174 fb->format->format); 175 if (val < 0) 176 return val; 177 178 ms->rotmem_size = val; 179 } 180 181 return 0; 182 } 183 184 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 185 int num_planes, unsigned int pitches[3]) 186 { 187 int i; 188 int num_strides = num_planes; 189 190 if (!mp->layer->stride_offset) 191 return; 192 193 if (num_planes == 3) 194 num_strides = (mp->hwdev->features & 195 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 196 197 for (i = 0; i < num_strides; ++i) 198 malidp_hw_write(mp->hwdev, pitches[i], 199 mp->layer->base + 200 mp->layer->stride_offset + i * 4); 201 } 202 203 static void malidp_de_plane_update(struct drm_plane *plane, 204 struct drm_plane_state *old_state) 205 { 206 struct drm_gem_cma_object *obj; 207 struct malidp_plane *mp; 208 const struct malidp_hw_regmap *map; 209 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 210 u16 ptr; 211 u32 src_w, src_h, dest_w, dest_h, val; 212 int i; 213 214 mp = to_malidp_plane(plane); 215 map = &mp->hwdev->map; 216 217 /* convert src values from Q16 fixed point to integer */ 218 src_w = plane->state->src_w >> 16; 219 src_h = plane->state->src_h >> 16; 220 dest_w = plane->state->crtc_w; 221 dest_h = plane->state->crtc_h; 222 223 malidp_hw_write(mp->hwdev, ms->format, mp->layer->base); 224 225 for (i = 0; i < ms->n_planes; i++) { 226 /* calculate the offset for the layer's plane registers */ 227 ptr = mp->layer->ptr + (i << 4); 228 229 obj = drm_fb_cma_get_gem_obj(plane->state->fb, i); 230 obj->paddr += plane->state->fb->offsets[i]; 231 malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr); 232 malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4); 233 } 234 malidp_de_set_plane_pitches(mp, ms->n_planes, 235 plane->state->fb->pitches); 236 237 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 238 mp->layer->base + MALIDP_LAYER_SIZE); 239 240 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 241 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 242 243 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) | 244 LAYER_V_VAL(plane->state->crtc_y), 245 mp->layer->base + MALIDP_LAYER_OFFSET); 246 247 if (mp->layer->id == DE_SMART) 248 malidp_hw_write(mp->hwdev, 249 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 250 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 251 252 /* first clear the rotation bits */ 253 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 254 val &= ~LAYER_ROT_MASK; 255 256 /* setup the rotation and axis flip bits */ 257 if (plane->state->rotation & DRM_ROTATE_MASK) 258 val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) << 259 LAYER_ROT_OFFSET; 260 if (plane->state->rotation & DRM_REFLECT_X) 261 val |= LAYER_H_FLIP; 262 if (plane->state->rotation & DRM_REFLECT_Y) 263 val |= LAYER_V_FLIP; 264 265 /* 266 * always enable pixel alpha blending until we have a way to change 267 * blend modes 268 */ 269 val &= ~LAYER_COMP_MASK; 270 val |= LAYER_COMP_PIXEL; 271 272 /* set the 'enable layer' bit */ 273 val |= LAYER_ENABLE; 274 275 malidp_hw_write(mp->hwdev, val, 276 mp->layer->base + MALIDP_LAYER_CONTROL); 277 } 278 279 static void malidp_de_plane_disable(struct drm_plane *plane, 280 struct drm_plane_state *state) 281 { 282 struct malidp_plane *mp = to_malidp_plane(plane); 283 284 malidp_hw_clearbits(mp->hwdev, LAYER_ENABLE, 285 mp->layer->base + MALIDP_LAYER_CONTROL); 286 } 287 288 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 289 .atomic_check = malidp_de_plane_check, 290 .atomic_update = malidp_de_plane_update, 291 .atomic_disable = malidp_de_plane_disable, 292 }; 293 294 int malidp_de_planes_init(struct drm_device *drm) 295 { 296 struct malidp_drm *malidp = drm->dev_private; 297 const struct malidp_hw_regmap *map = &malidp->dev->map; 298 struct malidp_plane *plane = NULL; 299 enum drm_plane_type plane_type; 300 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 301 unsigned long flags = DRM_ROTATE_0 | DRM_ROTATE_90 | DRM_ROTATE_180 | 302 DRM_ROTATE_270 | DRM_REFLECT_X | DRM_REFLECT_Y; 303 u32 *formats; 304 int ret, i, j, n; 305 306 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 307 if (!formats) { 308 ret = -ENOMEM; 309 goto cleanup; 310 } 311 312 for (i = 0; i < map->n_layers; i++) { 313 u8 id = map->layers[i].id; 314 315 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 316 if (!plane) { 317 ret = -ENOMEM; 318 goto cleanup; 319 } 320 321 /* build the list of DRM supported formats based on the map */ 322 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 323 if ((map->pixel_formats[j].layer & id) == id) 324 formats[n++] = map->pixel_formats[j].format; 325 } 326 327 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 328 DRM_PLANE_TYPE_OVERLAY; 329 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 330 &malidp_de_plane_funcs, formats, 331 n, plane_type, NULL); 332 if (ret < 0) 333 goto cleanup; 334 335 drm_plane_helper_add(&plane->base, 336 &malidp_de_plane_helper_funcs); 337 plane->hwdev = malidp->dev; 338 plane->layer = &map->layers[i]; 339 340 if (id == DE_SMART) { 341 /* 342 * Enable the first rectangle in the SMART layer to be 343 * able to use it as a drm plane. 344 */ 345 malidp_hw_write(malidp->dev, 1, 346 plane->layer->base + MALIDP550_LS_ENABLE); 347 /* Skip the features which the SMART layer doesn't have. */ 348 continue; 349 } 350 351 drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags); 352 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 353 plane->layer->base + MALIDP_LAYER_COMPOSE); 354 } 355 356 kfree(formats); 357 358 return 0; 359 360 cleanup: 361 malidp_de_planes_destroy(drm); 362 kfree(formats); 363 364 return ret; 365 } 366 367 void malidp_de_planes_destroy(struct drm_device *drm) 368 { 369 struct drm_plane *p, *pt; 370 371 list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) { 372 drm_plane_cleanup(p); 373 kfree(p); 374 } 375 } 376