1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 4 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 5 * 6 * ARM Mali DP plane manipulation routines. 7 */ 8 9 #include <linux/iommu.h> 10 #include <linux/platform_device.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_blend.h> 15 #include <drm/drm_drv.h> 16 #include <drm/drm_fb_dma_helper.h> 17 #include <drm/drm_fourcc.h> 18 #include <drm/drm_framebuffer.h> 19 #include <drm/drm_gem_dma_helper.h> 20 #include <drm/drm_gem_framebuffer_helper.h> 21 #include <drm/drm_print.h> 22 23 #include "malidp_hw.h" 24 #include "malidp_drv.h" 25 26 /* Layer specific register offsets */ 27 #define MALIDP_LAYER_FORMAT 0x000 28 #define LAYER_FORMAT_MASK 0x3f 29 #define MALIDP_LAYER_CONTROL 0x004 30 #define LAYER_ENABLE (1 << 0) 31 #define LAYER_FLOWCFG_MASK 7 32 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) 33 #define LAYER_FLOWCFG_SCALE_SE 3 34 #define LAYER_ROT_OFFSET 8 35 #define LAYER_H_FLIP (1 << 10) 36 #define LAYER_V_FLIP (1 << 11) 37 #define LAYER_ROT_MASK (0xf << 8) 38 #define LAYER_COMP_MASK (0x3 << 12) 39 #define LAYER_COMP_PIXEL (0x3 << 12) 40 #define LAYER_COMP_PLANE (0x2 << 12) 41 #define LAYER_PMUL_ENABLE (0x1 << 14) 42 #define LAYER_ALPHA_OFFSET (16) 43 #define LAYER_ALPHA_MASK (0xff) 44 #define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) 45 #define MALIDP_LAYER_COMPOSE 0x008 46 #define MALIDP_LAYER_SIZE 0x00c 47 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 48 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 49 #define MALIDP_LAYER_COMP_SIZE 0x010 50 #define MALIDP_LAYER_OFFSET 0x014 51 #define MALIDP550_LS_ENABLE 0x01c 52 #define MALIDP550_LS_R1_IN_SIZE 0x020 53 54 #define MODIFIERS_COUNT_MAX 15 55 56 /* 57 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 58 * for formats with 1- or 2-bit alpha channels. 59 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 60 * opacity for 2-bit formats. 61 */ 62 #define MALIDP_ALPHA_LUT 0xffaa5500 63 64 /* page sizes the MMU prefetcher can support */ 65 #define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K) 66 #define MALIDP_MMU_PREFETCH_FULL_PGSIZES (SZ_1M | SZ_2M) 67 68 /* readahead for partial-frame prefetch */ 69 #define MALIDP_MMU_PREFETCH_READAHEAD 8 70 71 static void malidp_de_plane_destroy(struct drm_plane *plane) 72 { 73 struct malidp_plane *mp = to_malidp_plane(plane); 74 75 drm_plane_cleanup(plane); 76 kfree(mp); 77 } 78 79 /* 80 * Replicate what the default ->reset hook does: free the state pointer and 81 * allocate a new empty object. We just need enough space to store 82 * a malidp_plane_state instead of a drm_plane_state. 83 */ 84 static void malidp_plane_reset(struct drm_plane *plane) 85 { 86 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); 87 88 if (state) 89 __drm_atomic_helper_plane_destroy_state(&state->base); 90 kfree(state); 91 plane->state = NULL; 92 state = kzalloc(sizeof(*state), GFP_KERNEL); 93 if (state) 94 __drm_atomic_helper_plane_reset(plane, &state->base); 95 } 96 97 static struct 98 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 99 { 100 struct malidp_plane_state *state, *m_state; 101 102 if (!plane->state) 103 return NULL; 104 105 state = kmalloc(sizeof(*state), GFP_KERNEL); 106 if (!state) 107 return NULL; 108 109 m_state = to_malidp_plane_state(plane->state); 110 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 111 state->rotmem_size = m_state->rotmem_size; 112 state->format = m_state->format; 113 state->n_planes = m_state->n_planes; 114 115 state->mmu_prefetch_mode = m_state->mmu_prefetch_mode; 116 state->mmu_prefetch_pgsize = m_state->mmu_prefetch_pgsize; 117 118 return &state->base; 119 } 120 121 static void malidp_destroy_plane_state(struct drm_plane *plane, 122 struct drm_plane_state *state) 123 { 124 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 125 126 __drm_atomic_helper_plane_destroy_state(state); 127 kfree(m_state); 128 } 129 130 static const char * const prefetch_mode_names[] = { 131 [MALIDP_PREFETCH_MODE_NONE] = "MMU_PREFETCH_NONE", 132 [MALIDP_PREFETCH_MODE_PARTIAL] = "MMU_PREFETCH_PARTIAL", 133 [MALIDP_PREFETCH_MODE_FULL] = "MMU_PREFETCH_FULL", 134 }; 135 136 static void malidp_plane_atomic_print_state(struct drm_printer *p, 137 const struct drm_plane_state *state) 138 { 139 struct malidp_plane_state *ms = to_malidp_plane_state(state); 140 141 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); 142 drm_printf(p, "\tformat_id=%u\n", ms->format); 143 drm_printf(p, "\tn_planes=%u\n", ms->n_planes); 144 drm_printf(p, "\tmmu_prefetch_mode=%s\n", 145 prefetch_mode_names[ms->mmu_prefetch_mode]); 146 drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize); 147 } 148 149 bool malidp_format_mod_supported(struct drm_device *drm, 150 u32 format, u64 modifier) 151 { 152 const struct drm_format_info *info; 153 const u64 *modifiers; 154 struct malidp_drm *malidp = drm->dev_private; 155 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 156 157 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) 158 return false; 159 160 /* Some pixel formats are supported without any modifier */ 161 if (modifier == DRM_FORMAT_MOD_LINEAR) { 162 /* 163 * However these pixel formats need to be supported with 164 * modifiers only 165 */ 166 return !malidp_hw_format_is_afbc_only(format); 167 } 168 169 if (!fourcc_mod_is_vendor(modifier, ARM)) { 170 DRM_ERROR("Unknown modifier (not Arm)\n"); 171 return false; 172 } 173 174 if (modifier & 175 ~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) { 176 DRM_DEBUG_KMS("Unsupported modifiers\n"); 177 return false; 178 } 179 180 modifiers = malidp_format_modifiers; 181 182 /* SPLIT buffers must use SPARSE layout */ 183 if (WARN_ON_ONCE((modifier & AFBC_SPLIT) && !(modifier & AFBC_SPARSE))) 184 return false; 185 186 /* CBR only applies to YUV formats, where YTR should be always 0 */ 187 if (WARN_ON_ONCE((modifier & AFBC_CBR) && (modifier & AFBC_YTR))) 188 return false; 189 190 while (*modifiers != DRM_FORMAT_MOD_INVALID) { 191 if (*modifiers == modifier) 192 break; 193 194 modifiers++; 195 } 196 197 /* return false, if the modifier was not found */ 198 if (*modifiers == DRM_FORMAT_MOD_INVALID) { 199 DRM_DEBUG_KMS("Unsupported modifier\n"); 200 return false; 201 } 202 203 info = drm_format_info(format); 204 205 if (info->num_planes != 1) { 206 DRM_DEBUG_KMS("AFBC buffers expect one plane\n"); 207 return false; 208 } 209 210 if (malidp_hw_format_is_linear_only(format) == true) { 211 DRM_DEBUG_KMS("Given format (0x%x) is supported is linear mode only\n", 212 format); 213 return false; 214 } 215 216 /* 217 * RGB formats need to provide YTR modifier and YUV formats should not 218 * provide YTR modifier. 219 */ 220 if (!(info->is_yuv) != !!(modifier & AFBC_FORMAT_MOD_YTR)) { 221 DRM_DEBUG_KMS("AFBC_FORMAT_MOD_YTR is %s for %s formats\n", 222 info->is_yuv ? "disallowed" : "mandatory", 223 info->is_yuv ? "YUV" : "RGB"); 224 return false; 225 } 226 227 if (modifier & AFBC_SPLIT) { 228 if (!info->is_yuv) { 229 if (info->cpp[0] <= 2) { 230 DRM_DEBUG_KMS("RGB formats <= 16bpp are not supported with SPLIT\n"); 231 return false; 232 } 233 } 234 235 if ((info->hsub != 1) || (info->vsub != 1)) { 236 if (!(format == DRM_FORMAT_YUV420_10BIT && 237 (map->features & MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT))) { 238 DRM_DEBUG_KMS("Formats which are sub-sampled should never be split\n"); 239 return false; 240 } 241 } 242 } 243 244 if (modifier & AFBC_CBR) { 245 if ((info->hsub == 1) || (info->vsub == 1)) { 246 DRM_DEBUG_KMS("Formats which are not sub-sampled should not have CBR set\n"); 247 return false; 248 } 249 } 250 251 return true; 252 } 253 254 static bool malidp_format_mod_supported_per_plane(struct drm_plane *plane, 255 u32 format, u64 modifier) 256 { 257 return malidp_format_mod_supported(plane->dev, format, modifier); 258 } 259 260 static const struct drm_plane_funcs malidp_de_plane_funcs = { 261 .update_plane = drm_atomic_helper_update_plane, 262 .disable_plane = drm_atomic_helper_disable_plane, 263 .destroy = malidp_de_plane_destroy, 264 .reset = malidp_plane_reset, 265 .atomic_duplicate_state = malidp_duplicate_plane_state, 266 .atomic_destroy_state = malidp_destroy_plane_state, 267 .atomic_print_state = malidp_plane_atomic_print_state, 268 .format_mod_supported = malidp_format_mod_supported_per_plane, 269 }; 270 271 static int malidp_se_check_scaling(struct malidp_plane *mp, 272 struct drm_plane_state *state) 273 { 274 struct drm_crtc_state *crtc_state = 275 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 276 struct malidp_crtc_state *mc; 277 u32 src_w, src_h; 278 int ret; 279 280 if (!crtc_state) 281 return -EINVAL; 282 283 mc = to_malidp_crtc_state(crtc_state); 284 285 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 286 0, INT_MAX, true, true); 287 if (ret) 288 return ret; 289 290 if (state->rotation & MALIDP_ROTATED_MASK) { 291 src_w = state->src_h >> 16; 292 src_h = state->src_w >> 16; 293 } else { 294 src_w = state->src_w >> 16; 295 src_h = state->src_h >> 16; 296 } 297 298 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { 299 /* Scaling not necessary for this plane. */ 300 mc->scaled_planes_mask &= ~(mp->layer->id); 301 return 0; 302 } 303 304 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) 305 return -EINVAL; 306 307 mc->scaled_planes_mask |= mp->layer->id; 308 /* Defer scaling requirements calculation to the crtc check. */ 309 return 0; 310 } 311 312 static u32 malidp_get_pgsize_bitmap(struct malidp_plane *mp) 313 { 314 struct iommu_domain *mmu_dom; 315 316 mmu_dom = iommu_get_domain_for_dev(mp->base.dev->dev); 317 if (mmu_dom) 318 return mmu_dom->pgsize_bitmap; 319 320 return 0; 321 } 322 323 /* 324 * Check if the framebuffer is entirely made up of pages at least pgsize in 325 * size. Only a heuristic: assumes that each scatterlist entry has been aligned 326 * to the largest page size smaller than its length and that the MMU maps to 327 * the largest page size possible. 328 */ 329 static bool malidp_check_pages_threshold(struct malidp_plane_state *ms, 330 u32 pgsize) 331 { 332 int i; 333 334 for (i = 0; i < ms->n_planes; i++) { 335 struct drm_gem_object *obj; 336 struct drm_gem_dma_object *dma_obj; 337 struct sg_table *sgt; 338 struct scatterlist *sgl; 339 340 obj = drm_gem_fb_get_obj(ms->base.fb, i); 341 dma_obj = to_drm_gem_dma_obj(obj); 342 343 if (dma_obj->sgt) 344 sgt = dma_obj->sgt; 345 else 346 sgt = obj->funcs->get_sg_table(obj); 347 348 if (IS_ERR(sgt)) 349 return false; 350 351 sgl = sgt->sgl; 352 353 while (sgl) { 354 if (sgl->length < pgsize) { 355 if (!dma_obj->sgt) 356 kfree(sgt); 357 return false; 358 } 359 360 sgl = sg_next(sgl); 361 } 362 if (!dma_obj->sgt) 363 kfree(sgt); 364 } 365 366 return true; 367 } 368 369 /* 370 * Check if it is possible to enable partial-frame MMU prefetch given the 371 * current format, AFBC state and rotation. 372 */ 373 static bool malidp_partial_prefetch_supported(u32 format, u64 modifier, 374 unsigned int rotation) 375 { 376 bool afbc, sparse; 377 378 /* rotation and horizontal flip not supported for partial prefetch */ 379 if (rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 380 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X)) 381 return false; 382 383 afbc = modifier & DRM_FORMAT_MOD_ARM_AFBC(0); 384 sparse = modifier & AFBC_FORMAT_MOD_SPARSE; 385 386 switch (format) { 387 case DRM_FORMAT_ARGB2101010: 388 case DRM_FORMAT_RGBA1010102: 389 case DRM_FORMAT_BGRA1010102: 390 case DRM_FORMAT_ARGB8888: 391 case DRM_FORMAT_RGBA8888: 392 case DRM_FORMAT_BGRA8888: 393 case DRM_FORMAT_XRGB8888: 394 case DRM_FORMAT_XBGR8888: 395 case DRM_FORMAT_RGBX8888: 396 case DRM_FORMAT_BGRX8888: 397 case DRM_FORMAT_RGB888: 398 case DRM_FORMAT_RGBA5551: 399 case DRM_FORMAT_RGB565: 400 /* always supported */ 401 return true; 402 403 case DRM_FORMAT_ABGR2101010: 404 case DRM_FORMAT_ABGR8888: 405 case DRM_FORMAT_ABGR1555: 406 case DRM_FORMAT_BGR565: 407 /* supported, but if AFBC then must be sparse mode */ 408 return (!afbc) || (afbc && sparse); 409 410 case DRM_FORMAT_BGR888: 411 /* supported, but not for AFBC */ 412 return !afbc; 413 414 case DRM_FORMAT_YUYV: 415 case DRM_FORMAT_UYVY: 416 case DRM_FORMAT_NV12: 417 case DRM_FORMAT_YUV420: 418 /* not supported */ 419 return false; 420 421 default: 422 return false; 423 } 424 } 425 426 /* 427 * Select the preferred MMU prefetch mode. Full-frame prefetch is preferred as 428 * long as the framebuffer is all large pages. Otherwise partial-frame prefetch 429 * is selected as long as it is supported for the current format. The selected 430 * page size for prefetch is returned in pgsize_bitmap. 431 */ 432 static enum mmu_prefetch_mode malidp_mmu_prefetch_select_mode 433 (struct malidp_plane_state *ms, u32 *pgsize_bitmap) 434 { 435 u32 pgsizes; 436 437 /* get the full-frame prefetch page size(s) supported by the MMU */ 438 pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_FULL_PGSIZES; 439 440 while (pgsizes) { 441 u32 largest_pgsize = 1 << __fls(pgsizes); 442 443 if (malidp_check_pages_threshold(ms, largest_pgsize)) { 444 *pgsize_bitmap = largest_pgsize; 445 return MALIDP_PREFETCH_MODE_FULL; 446 } 447 448 pgsizes -= largest_pgsize; 449 } 450 451 /* get the partial-frame prefetch page size(s) supported by the MMU */ 452 pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES; 453 454 if (malidp_partial_prefetch_supported(ms->base.fb->format->format, 455 ms->base.fb->modifier, 456 ms->base.rotation)) { 457 /* partial prefetch using the smallest page size */ 458 *pgsize_bitmap = 1 << __ffs(pgsizes); 459 return MALIDP_PREFETCH_MODE_PARTIAL; 460 } 461 *pgsize_bitmap = 0; 462 return MALIDP_PREFETCH_MODE_NONE; 463 } 464 465 static u32 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode, 466 u8 readahead, u8 n_planes, u32 pgsize) 467 { 468 u32 mmu_ctrl = 0; 469 470 if (mode != MALIDP_PREFETCH_MODE_NONE) { 471 mmu_ctrl |= MALIDP_MMU_CTRL_EN; 472 473 if (mode == MALIDP_PREFETCH_MODE_PARTIAL) { 474 mmu_ctrl |= MALIDP_MMU_CTRL_MODE; 475 mmu_ctrl |= MALIDP_MMU_CTRL_PP_NUM_REQ(readahead); 476 } 477 478 if (pgsize == SZ_64K || pgsize == SZ_2M) { 479 int i; 480 481 for (i = 0; i < n_planes; i++) 482 mmu_ctrl |= MALIDP_MMU_CTRL_PX_PS(i); 483 } 484 } 485 486 return mmu_ctrl; 487 } 488 489 static void malidp_de_prefetch_settings(struct malidp_plane *mp, 490 struct malidp_plane_state *ms) 491 { 492 if (!mp->layer->mmu_ctrl_offset) 493 return; 494 495 /* get the page sizes supported by the MMU */ 496 ms->mmu_prefetch_pgsize = malidp_get_pgsize_bitmap(mp); 497 ms->mmu_prefetch_mode = 498 malidp_mmu_prefetch_select_mode(ms, &ms->mmu_prefetch_pgsize); 499 } 500 501 static int malidp_de_plane_check(struct drm_plane *plane, 502 struct drm_atomic_state *state) 503 { 504 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 505 plane); 506 struct malidp_plane *mp = to_malidp_plane(plane); 507 struct malidp_plane_state *ms = to_malidp_plane_state(new_plane_state); 508 bool rotated = new_plane_state->rotation & MALIDP_ROTATED_MASK; 509 struct drm_framebuffer *fb; 510 u16 pixel_alpha = new_plane_state->pixel_blend_mode; 511 int i, ret; 512 unsigned int block_w, block_h; 513 514 if (!new_plane_state->crtc || WARN_ON(!new_plane_state->fb)) 515 return 0; 516 517 fb = new_plane_state->fb; 518 519 ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, 520 mp->layer->id, fb->format->format, 521 !!fb->modifier); 522 if (ms->format == MALIDP_INVALID_FORMAT_ID) 523 return -EINVAL; 524 525 ms->n_planes = fb->format->num_planes; 526 for (i = 0; i < ms->n_planes; i++) { 527 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); 528 529 if (((fb->pitches[i] * drm_format_info_block_height(fb->format, i)) 530 & (alignment - 1)) && !(fb->modifier)) { 531 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 532 fb->pitches[i], i); 533 return -EINVAL; 534 } 535 } 536 537 block_w = drm_format_info_block_width(fb->format, 0); 538 block_h = drm_format_info_block_height(fb->format, 0); 539 if (fb->width % block_w || fb->height % block_h) { 540 DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes"); 541 return -EINVAL; 542 } 543 if ((new_plane_state->src_x >> 16) % block_w || (new_plane_state->src_y >> 16) % block_h) { 544 DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes"); 545 return -EINVAL; 546 } 547 548 if ((new_plane_state->crtc_w > mp->hwdev->max_line_size) || 549 (new_plane_state->crtc_h > mp->hwdev->max_line_size) || 550 (new_plane_state->crtc_w < mp->hwdev->min_line_size) || 551 (new_plane_state->crtc_h < mp->hwdev->min_line_size)) 552 return -EINVAL; 553 554 /* 555 * DP550/650 video layers can accept 3 plane formats only if 556 * fb->pitches[1] == fb->pitches[2] since they don't have a 557 * third plane stride register. 558 */ 559 if (ms->n_planes == 3 && 560 !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 561 (new_plane_state->fb->pitches[1] != new_plane_state->fb->pitches[2])) 562 return -EINVAL; 563 564 ret = malidp_se_check_scaling(mp, new_plane_state); 565 if (ret) 566 return ret; 567 568 /* validate the rotation constraints for each layer */ 569 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) { 570 if (mp->layer->rot == ROTATE_NONE) 571 return -EINVAL; 572 if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier)) 573 return -EINVAL; 574 /* 575 * packed RGB888 / BGR888 can't be rotated or flipped 576 * unless they are stored in a compressed way 577 */ 578 if ((fb->format->format == DRM_FORMAT_RGB888 || 579 fb->format->format == DRM_FORMAT_BGR888) && !(fb->modifier)) 580 return -EINVAL; 581 } 582 583 /* SMART layer does not support AFBC */ 584 if (mp->layer->id == DE_SMART && fb->modifier) { 585 DRM_ERROR("AFBC framebuffer not supported in SMART layer"); 586 return -EINVAL; 587 } 588 589 ms->rotmem_size = 0; 590 if (new_plane_state->rotation & MALIDP_ROTATED_MASK) { 591 int val; 592 593 val = mp->hwdev->hw->rotmem_required(mp->hwdev, new_plane_state->crtc_w, 594 new_plane_state->crtc_h, 595 fb->format->format, 596 !!(fb->modifier)); 597 if (val < 0) 598 return val; 599 600 ms->rotmem_size = val; 601 } 602 603 /* HW can't support plane + pixel blending */ 604 if ((new_plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE) && 605 (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) && 606 fb->format->has_alpha) 607 return -EINVAL; 608 609 malidp_de_prefetch_settings(mp, ms); 610 611 return 0; 612 } 613 614 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 615 int num_planes, unsigned int pitches[3]) 616 { 617 int i; 618 int num_strides = num_planes; 619 620 if (!mp->layer->stride_offset) 621 return; 622 623 if (num_planes == 3) 624 num_strides = (mp->hwdev->hw->features & 625 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 626 627 /* 628 * The drm convention for pitch is that it needs to cover width * cpp, 629 * but our hardware wants the pitch/stride to cover all rows included 630 * in a tile. 631 */ 632 for (i = 0; i < num_strides; ++i) { 633 unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i); 634 635 malidp_hw_write(mp->hwdev, pitches[i] * block_h, 636 mp->layer->base + 637 mp->layer->stride_offset + i * 4); 638 } 639 } 640 641 static const s16 642 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = { 643 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 644 1192, 0, 1634, 645 1192, -401, -832, 646 1192, 2066, 0, 647 64, 512, 512 648 }, 649 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 650 1024, 0, 1436, 651 1024, -352, -731, 652 1024, 1815, 0, 653 0, 512, 512 654 }, 655 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 656 1192, 0, 1836, 657 1192, -218, -546, 658 1192, 2163, 0, 659 64, 512, 512 660 }, 661 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 662 1024, 0, 1613, 663 1024, -192, -479, 664 1024, 1900, 0, 665 0, 512, 512 666 }, 667 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 668 1024, 0, 1476, 669 1024, -165, -572, 670 1024, 1884, 0, 671 0, 512, 512 672 }, 673 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = { 674 1024, 0, 1510, 675 1024, -168, -585, 676 1024, 1927, 0, 677 0, 512, 512 678 } 679 }; 680 681 static void malidp_de_set_color_encoding(struct malidp_plane *plane, 682 enum drm_color_encoding enc, 683 enum drm_color_range range) 684 { 685 unsigned int i; 686 687 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) { 688 /* coefficients are signed, two's complement values */ 689 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], 690 plane->layer->base + plane->layer->yuv2rgb_offset + 691 i * 4); 692 } 693 } 694 695 static void malidp_de_set_mmu_control(struct malidp_plane *mp, 696 struct malidp_plane_state *ms) 697 { 698 u32 mmu_ctrl; 699 700 /* check hardware supports MMU prefetch */ 701 if (!mp->layer->mmu_ctrl_offset) 702 return; 703 704 mmu_ctrl = malidp_calc_mmu_control_value(ms->mmu_prefetch_mode, 705 MALIDP_MMU_PREFETCH_READAHEAD, 706 ms->n_planes, 707 ms->mmu_prefetch_pgsize); 708 709 malidp_hw_write(mp->hwdev, mmu_ctrl, 710 mp->layer->base + mp->layer->mmu_ctrl_offset); 711 } 712 713 static void malidp_set_plane_base_addr(struct drm_framebuffer *fb, 714 struct malidp_plane *mp, 715 int plane_index) 716 { 717 dma_addr_t dma_addr; 718 u16 ptr; 719 struct drm_plane *plane = &mp->base; 720 bool afbc = fb->modifier ? true : false; 721 722 ptr = mp->layer->ptr + (plane_index << 4); 723 724 /* 725 * drm_fb_dma_get_gem_addr() alters the physical base address of the 726 * framebuffer as per the plane's src_x, src_y co-ordinates (ie to 727 * take care of source cropping). 728 * For AFBC, this is not needed as the cropping is handled by _AD_CROP_H 729 * and _AD_CROP_V registers. 730 */ 731 if (!afbc) { 732 dma_addr = drm_fb_dma_get_gem_addr(fb, plane->state, 733 plane_index); 734 } else { 735 struct drm_gem_dma_object *obj; 736 737 obj = drm_fb_dma_get_gem_obj(fb, plane_index); 738 739 if (WARN_ON(!obj)) 740 return; 741 dma_addr = obj->dma_addr; 742 } 743 744 malidp_hw_write(mp->hwdev, lower_32_bits(dma_addr), ptr); 745 malidp_hw_write(mp->hwdev, upper_32_bits(dma_addr), ptr + 4); 746 } 747 748 static void malidp_de_set_plane_afbc(struct drm_plane *plane) 749 { 750 struct malidp_plane *mp; 751 u32 src_w, src_h, val = 0, src_x, src_y; 752 struct drm_framebuffer *fb = plane->state->fb; 753 754 mp = to_malidp_plane(plane); 755 756 /* no afbc_decoder_offset means AFBC is not supported on this plane */ 757 if (!mp->layer->afbc_decoder_offset) 758 return; 759 760 if (!fb->modifier) { 761 malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset); 762 return; 763 } 764 765 /* convert src values from Q16 fixed point to integer */ 766 src_w = plane->state->src_w >> 16; 767 src_h = plane->state->src_h >> 16; 768 src_x = plane->state->src_x >> 16; 769 src_y = plane->state->src_y >> 16; 770 771 val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) | 772 src_x; 773 malidp_hw_write(mp->hwdev, val, 774 mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_H); 775 776 val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) | 777 src_y; 778 malidp_hw_write(mp->hwdev, val, 779 mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_V); 780 781 val = MALIDP_AD_EN; 782 if (fb->modifier & AFBC_FORMAT_MOD_SPLIT) 783 val |= MALIDP_AD_BS; 784 if (fb->modifier & AFBC_FORMAT_MOD_YTR) 785 val |= MALIDP_AD_YTR; 786 787 malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset); 788 } 789 790 static void malidp_de_plane_update(struct drm_plane *plane, 791 struct drm_atomic_state *state) 792 { 793 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 794 plane); 795 struct malidp_plane *mp; 796 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 797 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 798 plane); 799 u16 pixel_alpha = new_state->pixel_blend_mode; 800 u8 plane_alpha = new_state->alpha >> 8; 801 u32 src_w, src_h, dest_w, dest_h, val; 802 int i; 803 struct drm_framebuffer *fb = plane->state->fb; 804 805 mp = to_malidp_plane(plane); 806 807 /* 808 * For AFBC framebuffer, use the framebuffer width and height for 809 * configuring layer input size register. 810 */ 811 if (fb->modifier) { 812 src_w = fb->width; 813 src_h = fb->height; 814 } else { 815 /* convert src values from Q16 fixed point to integer */ 816 src_w = new_state->src_w >> 16; 817 src_h = new_state->src_h >> 16; 818 } 819 820 dest_w = new_state->crtc_w; 821 dest_h = new_state->crtc_h; 822 823 val = malidp_hw_read(mp->hwdev, mp->layer->base); 824 val = (val & ~LAYER_FORMAT_MASK) | ms->format; 825 malidp_hw_write(mp->hwdev, val, mp->layer->base); 826 827 for (i = 0; i < ms->n_planes; i++) 828 malidp_set_plane_base_addr(fb, mp, i); 829 830 malidp_de_set_mmu_control(mp, ms); 831 832 malidp_de_set_plane_pitches(mp, ms->n_planes, 833 new_state->fb->pitches); 834 835 if ((plane->state->color_encoding != old_state->color_encoding) || 836 (plane->state->color_range != old_state->color_range)) 837 malidp_de_set_color_encoding(mp, plane->state->color_encoding, 838 plane->state->color_range); 839 840 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 841 mp->layer->base + MALIDP_LAYER_SIZE); 842 843 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 844 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 845 846 malidp_hw_write(mp->hwdev, LAYER_H_VAL(new_state->crtc_x) | 847 LAYER_V_VAL(new_state->crtc_y), 848 mp->layer->base + MALIDP_LAYER_OFFSET); 849 850 if (mp->layer->id == DE_SMART) { 851 /* 852 * Enable the first rectangle in the SMART layer to be 853 * able to use it as a drm plane. 854 */ 855 malidp_hw_write(mp->hwdev, 1, 856 mp->layer->base + MALIDP550_LS_ENABLE); 857 malidp_hw_write(mp->hwdev, 858 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 859 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 860 } 861 862 malidp_de_set_plane_afbc(plane); 863 864 /* first clear the rotation bits */ 865 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 866 val &= ~LAYER_ROT_MASK; 867 868 /* setup the rotation and axis flip bits */ 869 if (new_state->rotation & DRM_MODE_ROTATE_MASK) 870 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << 871 LAYER_ROT_OFFSET; 872 if (new_state->rotation & DRM_MODE_REFLECT_X) 873 val |= LAYER_H_FLIP; 874 if (new_state->rotation & DRM_MODE_REFLECT_Y) 875 val |= LAYER_V_FLIP; 876 877 val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff)); 878 879 if (new_state->alpha != DRM_BLEND_ALPHA_OPAQUE) { 880 val |= LAYER_COMP_PLANE; 881 } else if (new_state->fb->format->has_alpha) { 882 /* We only care about blend mode if the format has alpha */ 883 switch (pixel_alpha) { 884 case DRM_MODE_BLEND_PREMULTI: 885 val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE; 886 break; 887 case DRM_MODE_BLEND_COVERAGE: 888 val |= LAYER_COMP_PIXEL; 889 break; 890 } 891 } 892 val |= LAYER_ALPHA(plane_alpha); 893 894 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); 895 if (new_state->crtc) { 896 struct malidp_crtc_state *m = 897 to_malidp_crtc_state(new_state->crtc->state); 898 899 if (m->scaler_config.scale_enable && 900 m->scaler_config.plane_src_id == mp->layer->id) 901 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); 902 } 903 904 /* set the 'enable layer' bit */ 905 val |= LAYER_ENABLE; 906 907 malidp_hw_write(mp->hwdev, val, 908 mp->layer->base + MALIDP_LAYER_CONTROL); 909 } 910 911 static void malidp_de_plane_disable(struct drm_plane *plane, 912 struct drm_atomic_state *state) 913 { 914 struct malidp_plane *mp = to_malidp_plane(plane); 915 916 malidp_hw_clearbits(mp->hwdev, 917 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), 918 mp->layer->base + MALIDP_LAYER_CONTROL); 919 } 920 921 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 922 .atomic_check = malidp_de_plane_check, 923 .atomic_update = malidp_de_plane_update, 924 .atomic_disable = malidp_de_plane_disable, 925 }; 926 927 static const uint64_t linear_only_modifiers[] = { 928 DRM_FORMAT_MOD_LINEAR, 929 DRM_FORMAT_MOD_INVALID 930 }; 931 932 int malidp_de_planes_init(struct drm_device *drm) 933 { 934 struct malidp_drm *malidp = drm->dev_private; 935 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 936 struct malidp_plane *plane = NULL; 937 enum drm_plane_type plane_type; 938 unsigned long crtcs = BIT(drm->mode_config.num_crtc); 939 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 940 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 941 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 942 BIT(DRM_MODE_BLEND_PREMULTI) | 943 BIT(DRM_MODE_BLEND_COVERAGE); 944 u32 *formats; 945 int ret, i = 0, j = 0, n; 946 u64 supported_modifiers[MODIFIERS_COUNT_MAX]; 947 const u64 *modifiers; 948 949 modifiers = malidp_format_modifiers; 950 951 if (!(map->features & MALIDP_DEVICE_AFBC_SUPPORT_SPLIT)) { 952 /* 953 * Since our hardware does not support SPLIT, so build the list 954 * of supported modifiers excluding SPLIT ones. 955 */ 956 while (*modifiers != DRM_FORMAT_MOD_INVALID) { 957 if (!(*modifiers & AFBC_SPLIT)) 958 supported_modifiers[j++] = *modifiers; 959 960 modifiers++; 961 } 962 supported_modifiers[j++] = DRM_FORMAT_MOD_INVALID; 963 modifiers = supported_modifiers; 964 } 965 966 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 967 if (!formats) { 968 ret = -ENOMEM; 969 goto cleanup; 970 } 971 972 for (i = 0; i < map->n_layers; i++) { 973 u8 id = map->layers[i].id; 974 975 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 976 if (!plane) { 977 ret = -ENOMEM; 978 goto cleanup; 979 } 980 981 /* build the list of DRM supported formats based on the map */ 982 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 983 if ((map->pixel_formats[j].layer & id) == id) 984 formats[n++] = map->pixel_formats[j].format; 985 } 986 987 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 988 DRM_PLANE_TYPE_OVERLAY; 989 990 /* 991 * All the layers except smart layer supports AFBC modifiers. 992 */ 993 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 994 &malidp_de_plane_funcs, formats, n, 995 (id == DE_SMART) ? linear_only_modifiers : modifiers, 996 plane_type, NULL); 997 998 if (ret < 0) 999 goto cleanup; 1000 1001 drm_plane_helper_add(&plane->base, 1002 &malidp_de_plane_helper_funcs); 1003 plane->hwdev = malidp->dev; 1004 plane->layer = &map->layers[i]; 1005 1006 drm_plane_create_alpha_property(&plane->base); 1007 drm_plane_create_blend_mode_property(&plane->base, blend_caps); 1008 1009 if (id == DE_SMART) { 1010 /* Skip the features which the SMART layer doesn't have. */ 1011 continue; 1012 } 1013 1014 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); 1015 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 1016 plane->layer->base + MALIDP_LAYER_COMPOSE); 1017 1018 /* Attach the YUV->RGB property only to video layers */ 1019 if (id & (DE_VIDEO1 | DE_VIDEO2)) { 1020 /* default encoding for YUV->RGB is BT601 NARROW */ 1021 enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; 1022 enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; 1023 1024 ret = drm_plane_create_color_properties(&plane->base, 1025 BIT(DRM_COLOR_YCBCR_BT601) | \ 1026 BIT(DRM_COLOR_YCBCR_BT709) | \ 1027 BIT(DRM_COLOR_YCBCR_BT2020), 1028 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ 1029 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1030 enc, range); 1031 if (!ret) 1032 /* program the HW registers */ 1033 malidp_de_set_color_encoding(plane, enc, range); 1034 else 1035 DRM_WARN("Failed to create video layer %d color properties\n", id); 1036 } 1037 } 1038 1039 kfree(formats); 1040 1041 return 0; 1042 1043 cleanup: 1044 kfree(formats); 1045 1046 return ret; 1047 } 1048