1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_fb_cma_helper.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_plane_helper.h> 19 #include <drm/drm_print.h> 20 21 #include "malidp_hw.h" 22 #include "malidp_drv.h" 23 24 /* Layer specific register offsets */ 25 #define MALIDP_LAYER_FORMAT 0x000 26 #define LAYER_FORMAT_MASK 0x3f 27 #define MALIDP_LAYER_CONTROL 0x004 28 #define LAYER_ENABLE (1 << 0) 29 #define LAYER_FLOWCFG_MASK 7 30 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) 31 #define LAYER_FLOWCFG_SCALE_SE 3 32 #define LAYER_ROT_OFFSET 8 33 #define LAYER_H_FLIP (1 << 10) 34 #define LAYER_V_FLIP (1 << 11) 35 #define LAYER_ROT_MASK (0xf << 8) 36 #define LAYER_COMP_MASK (0x3 << 12) 37 #define LAYER_COMP_PIXEL (0x3 << 12) 38 #define LAYER_COMP_PLANE (0x2 << 12) 39 #define LAYER_PMUL_ENABLE (0x1 << 14) 40 #define LAYER_ALPHA_OFFSET (16) 41 #define LAYER_ALPHA_MASK (0xff) 42 #define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) 43 #define MALIDP_LAYER_COMPOSE 0x008 44 #define MALIDP_LAYER_SIZE 0x00c 45 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 46 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 47 #define MALIDP_LAYER_COMP_SIZE 0x010 48 #define MALIDP_LAYER_OFFSET 0x014 49 #define MALIDP550_LS_ENABLE 0x01c 50 #define MALIDP550_LS_R1_IN_SIZE 0x020 51 52 /* 53 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 54 * for formats with 1- or 2-bit alpha channels. 55 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 56 * opacity for 2-bit formats. 57 */ 58 #define MALIDP_ALPHA_LUT 0xffaa5500 59 60 static void malidp_de_plane_destroy(struct drm_plane *plane) 61 { 62 struct malidp_plane *mp = to_malidp_plane(plane); 63 64 drm_plane_cleanup(plane); 65 kfree(mp); 66 } 67 68 /* 69 * Replicate what the default ->reset hook does: free the state pointer and 70 * allocate a new empty object. We just need enough space to store 71 * a malidp_plane_state instead of a drm_plane_state. 72 */ 73 static void malidp_plane_reset(struct drm_plane *plane) 74 { 75 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); 76 77 if (state) 78 __drm_atomic_helper_plane_destroy_state(&state->base); 79 kfree(state); 80 plane->state = NULL; 81 state = kzalloc(sizeof(*state), GFP_KERNEL); 82 if (state) 83 __drm_atomic_helper_plane_reset(plane, &state->base); 84 } 85 86 static struct 87 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 88 { 89 struct malidp_plane_state *state, *m_state; 90 91 if (!plane->state) 92 return NULL; 93 94 state = kmalloc(sizeof(*state), GFP_KERNEL); 95 if (!state) 96 return NULL; 97 98 m_state = to_malidp_plane_state(plane->state); 99 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 100 state->rotmem_size = m_state->rotmem_size; 101 state->format = m_state->format; 102 state->n_planes = m_state->n_planes; 103 104 return &state->base; 105 } 106 107 static void malidp_destroy_plane_state(struct drm_plane *plane, 108 struct drm_plane_state *state) 109 { 110 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 111 112 __drm_atomic_helper_plane_destroy_state(state); 113 kfree(m_state); 114 } 115 116 static void malidp_plane_atomic_print_state(struct drm_printer *p, 117 const struct drm_plane_state *state) 118 { 119 struct malidp_plane_state *ms = to_malidp_plane_state(state); 120 121 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); 122 drm_printf(p, "\tformat_id=%u\n", ms->format); 123 drm_printf(p, "\tn_planes=%u\n", ms->n_planes); 124 } 125 126 static const struct drm_plane_funcs malidp_de_plane_funcs = { 127 .update_plane = drm_atomic_helper_update_plane, 128 .disable_plane = drm_atomic_helper_disable_plane, 129 .destroy = malidp_de_plane_destroy, 130 .reset = malidp_plane_reset, 131 .atomic_duplicate_state = malidp_duplicate_plane_state, 132 .atomic_destroy_state = malidp_destroy_plane_state, 133 .atomic_print_state = malidp_plane_atomic_print_state, 134 }; 135 136 static int malidp_se_check_scaling(struct malidp_plane *mp, 137 struct drm_plane_state *state) 138 { 139 struct drm_crtc_state *crtc_state = 140 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 141 struct malidp_crtc_state *mc; 142 u32 src_w, src_h; 143 int ret; 144 145 if (!crtc_state) 146 return -EINVAL; 147 148 mc = to_malidp_crtc_state(crtc_state); 149 150 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 151 0, INT_MAX, true, true); 152 if (ret) 153 return ret; 154 155 if (state->rotation & MALIDP_ROTATED_MASK) { 156 src_w = state->src_h >> 16; 157 src_h = state->src_w >> 16; 158 } else { 159 src_w = state->src_w >> 16; 160 src_h = state->src_h >> 16; 161 } 162 163 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { 164 /* Scaling not necessary for this plane. */ 165 mc->scaled_planes_mask &= ~(mp->layer->id); 166 return 0; 167 } 168 169 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) 170 return -EINVAL; 171 172 mc->scaled_planes_mask |= mp->layer->id; 173 /* Defer scaling requirements calculation to the crtc check. */ 174 return 0; 175 } 176 177 static int malidp_de_plane_check(struct drm_plane *plane, 178 struct drm_plane_state *state) 179 { 180 struct malidp_plane *mp = to_malidp_plane(plane); 181 struct malidp_plane_state *ms = to_malidp_plane_state(state); 182 bool rotated = state->rotation & MALIDP_ROTATED_MASK; 183 struct drm_framebuffer *fb; 184 u16 pixel_alpha = state->pixel_blend_mode; 185 int i, ret; 186 187 if (!state->crtc || !state->fb) 188 return 0; 189 190 fb = state->fb; 191 192 ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, 193 mp->layer->id, 194 fb->format->format); 195 if (ms->format == MALIDP_INVALID_FORMAT_ID) 196 return -EINVAL; 197 198 ms->n_planes = fb->format->num_planes; 199 for (i = 0; i < ms->n_planes; i++) { 200 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); 201 if (fb->pitches[i] & (alignment - 1)) { 202 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 203 fb->pitches[i], i); 204 return -EINVAL; 205 } 206 } 207 208 if ((state->crtc_w > mp->hwdev->max_line_size) || 209 (state->crtc_h > mp->hwdev->max_line_size) || 210 (state->crtc_w < mp->hwdev->min_line_size) || 211 (state->crtc_h < mp->hwdev->min_line_size)) 212 return -EINVAL; 213 214 /* 215 * DP550/650 video layers can accept 3 plane formats only if 216 * fb->pitches[1] == fb->pitches[2] since they don't have a 217 * third plane stride register. 218 */ 219 if (ms->n_planes == 3 && 220 !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 221 (state->fb->pitches[1] != state->fb->pitches[2])) 222 return -EINVAL; 223 224 ret = malidp_se_check_scaling(mp, state); 225 if (ret) 226 return ret; 227 228 /* packed RGB888 / BGR888 can't be rotated or flipped */ 229 if (state->rotation != DRM_MODE_ROTATE_0 && 230 (fb->format->format == DRM_FORMAT_RGB888 || 231 fb->format->format == DRM_FORMAT_BGR888)) 232 return -EINVAL; 233 234 ms->rotmem_size = 0; 235 if (state->rotation & MALIDP_ROTATED_MASK) { 236 int val; 237 238 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, 239 state->crtc_h, 240 fb->format->format); 241 if (val < 0) 242 return val; 243 244 ms->rotmem_size = val; 245 } 246 247 /* HW can't support plane + pixel blending */ 248 if ((state->alpha != DRM_BLEND_ALPHA_OPAQUE) && 249 (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) && 250 fb->format->has_alpha) 251 return -EINVAL; 252 253 return 0; 254 } 255 256 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 257 int num_planes, unsigned int pitches[3]) 258 { 259 int i; 260 int num_strides = num_planes; 261 262 if (!mp->layer->stride_offset) 263 return; 264 265 if (num_planes == 3) 266 num_strides = (mp->hwdev->hw->features & 267 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 268 269 for (i = 0; i < num_strides; ++i) 270 malidp_hw_write(mp->hwdev, pitches[i], 271 mp->layer->base + 272 mp->layer->stride_offset + i * 4); 273 } 274 275 static const s16 276 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = { 277 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 278 1192, 0, 1634, 279 1192, -401, -832, 280 1192, 2066, 0, 281 64, 512, 512 282 }, 283 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 284 1024, 0, 1436, 285 1024, -352, -731, 286 1024, 1815, 0, 287 0, 512, 512 288 }, 289 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 290 1192, 0, 1836, 291 1192, -218, -546, 292 1192, 2163, 0, 293 64, 512, 512 294 }, 295 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 296 1024, 0, 1613, 297 1024, -192, -479, 298 1024, 1900, 0, 299 0, 512, 512 300 }, 301 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 302 1024, 0, 1476, 303 1024, -165, -572, 304 1024, 1884, 0, 305 0, 512, 512 306 }, 307 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = { 308 1024, 0, 1510, 309 1024, -168, -585, 310 1024, 1927, 0, 311 0, 512, 512 312 } 313 }; 314 315 static void malidp_de_set_color_encoding(struct malidp_plane *plane, 316 enum drm_color_encoding enc, 317 enum drm_color_range range) 318 { 319 unsigned int i; 320 321 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) { 322 /* coefficients are signed, two's complement values */ 323 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], 324 plane->layer->base + plane->layer->yuv2rgb_offset + 325 i * 4); 326 } 327 } 328 329 static void malidp_de_plane_update(struct drm_plane *plane, 330 struct drm_plane_state *old_state) 331 { 332 struct malidp_plane *mp; 333 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 334 struct drm_plane_state *state = plane->state; 335 u16 pixel_alpha = state->pixel_blend_mode; 336 u8 plane_alpha = state->alpha >> 8; 337 u32 src_w, src_h, dest_w, dest_h, val; 338 int i; 339 340 mp = to_malidp_plane(plane); 341 342 /* convert src values from Q16 fixed point to integer */ 343 src_w = state->src_w >> 16; 344 src_h = state->src_h >> 16; 345 dest_w = state->crtc_w; 346 dest_h = state->crtc_h; 347 348 val = malidp_hw_read(mp->hwdev, mp->layer->base); 349 val = (val & ~LAYER_FORMAT_MASK) | ms->format; 350 malidp_hw_write(mp->hwdev, val, mp->layer->base); 351 352 for (i = 0; i < ms->n_planes; i++) { 353 /* calculate the offset for the layer's plane registers */ 354 u16 ptr = mp->layer->ptr + (i << 4); 355 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(state->fb, 356 state, i); 357 358 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr); 359 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4); 360 } 361 malidp_de_set_plane_pitches(mp, ms->n_planes, 362 state->fb->pitches); 363 364 if ((plane->state->color_encoding != old_state->color_encoding) || 365 (plane->state->color_range != old_state->color_range)) 366 malidp_de_set_color_encoding(mp, plane->state->color_encoding, 367 plane->state->color_range); 368 369 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 370 mp->layer->base + MALIDP_LAYER_SIZE); 371 372 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 373 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 374 375 malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) | 376 LAYER_V_VAL(state->crtc_y), 377 mp->layer->base + MALIDP_LAYER_OFFSET); 378 379 if (mp->layer->id == DE_SMART) { 380 /* 381 * Enable the first rectangle in the SMART layer to be 382 * able to use it as a drm plane. 383 */ 384 malidp_hw_write(mp->hwdev, 1, 385 mp->layer->base + MALIDP550_LS_ENABLE); 386 malidp_hw_write(mp->hwdev, 387 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 388 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 389 } 390 391 /* first clear the rotation bits */ 392 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 393 val &= ~LAYER_ROT_MASK; 394 395 /* setup the rotation and axis flip bits */ 396 if (state->rotation & DRM_MODE_ROTATE_MASK) 397 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << 398 LAYER_ROT_OFFSET; 399 if (state->rotation & DRM_MODE_REFLECT_X) 400 val |= LAYER_H_FLIP; 401 if (state->rotation & DRM_MODE_REFLECT_Y) 402 val |= LAYER_V_FLIP; 403 404 val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff)); 405 406 if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) { 407 val |= LAYER_COMP_PLANE; 408 } else if (state->fb->format->has_alpha) { 409 /* We only care about blend mode if the format has alpha */ 410 switch (pixel_alpha) { 411 case DRM_MODE_BLEND_PREMULTI: 412 val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE; 413 break; 414 case DRM_MODE_BLEND_COVERAGE: 415 val |= LAYER_COMP_PIXEL; 416 break; 417 } 418 } 419 val |= LAYER_ALPHA(plane_alpha); 420 421 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); 422 if (state->crtc) { 423 struct malidp_crtc_state *m = 424 to_malidp_crtc_state(state->crtc->state); 425 426 if (m->scaler_config.scale_enable && 427 m->scaler_config.plane_src_id == mp->layer->id) 428 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); 429 } 430 431 /* set the 'enable layer' bit */ 432 val |= LAYER_ENABLE; 433 434 malidp_hw_write(mp->hwdev, val, 435 mp->layer->base + MALIDP_LAYER_CONTROL); 436 } 437 438 static void malidp_de_plane_disable(struct drm_plane *plane, 439 struct drm_plane_state *state) 440 { 441 struct malidp_plane *mp = to_malidp_plane(plane); 442 443 malidp_hw_clearbits(mp->hwdev, 444 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), 445 mp->layer->base + MALIDP_LAYER_CONTROL); 446 } 447 448 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 449 .atomic_check = malidp_de_plane_check, 450 .atomic_update = malidp_de_plane_update, 451 .atomic_disable = malidp_de_plane_disable, 452 }; 453 454 int malidp_de_planes_init(struct drm_device *drm) 455 { 456 struct malidp_drm *malidp = drm->dev_private; 457 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 458 struct malidp_plane *plane = NULL; 459 enum drm_plane_type plane_type; 460 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 461 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 462 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 463 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 464 BIT(DRM_MODE_BLEND_PREMULTI) | 465 BIT(DRM_MODE_BLEND_COVERAGE); 466 u32 *formats; 467 int ret, i, j, n; 468 469 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 470 if (!formats) { 471 ret = -ENOMEM; 472 goto cleanup; 473 } 474 475 for (i = 0; i < map->n_layers; i++) { 476 u8 id = map->layers[i].id; 477 478 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 479 if (!plane) { 480 ret = -ENOMEM; 481 goto cleanup; 482 } 483 484 /* build the list of DRM supported formats based on the map */ 485 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 486 if ((map->pixel_formats[j].layer & id) == id) 487 formats[n++] = map->pixel_formats[j].format; 488 } 489 490 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 491 DRM_PLANE_TYPE_OVERLAY; 492 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 493 &malidp_de_plane_funcs, formats, 494 n, NULL, plane_type, NULL); 495 if (ret < 0) 496 goto cleanup; 497 498 drm_plane_helper_add(&plane->base, 499 &malidp_de_plane_helper_funcs); 500 plane->hwdev = malidp->dev; 501 plane->layer = &map->layers[i]; 502 503 drm_plane_create_alpha_property(&plane->base); 504 drm_plane_create_blend_mode_property(&plane->base, blend_caps); 505 506 if (id == DE_SMART) { 507 /* Skip the features which the SMART layer doesn't have. */ 508 continue; 509 } 510 511 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); 512 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 513 plane->layer->base + MALIDP_LAYER_COMPOSE); 514 515 /* Attach the YUV->RGB property only to video layers */ 516 if (id & (DE_VIDEO1 | DE_VIDEO2)) { 517 /* default encoding for YUV->RGB is BT601 NARROW */ 518 enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; 519 enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; 520 521 ret = drm_plane_create_color_properties(&plane->base, 522 BIT(DRM_COLOR_YCBCR_BT601) | \ 523 BIT(DRM_COLOR_YCBCR_BT709) | \ 524 BIT(DRM_COLOR_YCBCR_BT2020), 525 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ 526 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 527 enc, range); 528 if (!ret) 529 /* program the HW registers */ 530 malidp_de_set_color_encoding(plane, enc, range); 531 else 532 DRM_WARN("Failed to create video layer %d color properties\n", id); 533 } 534 } 535 536 kfree(formats); 537 538 return 0; 539 540 cleanup: 541 kfree(formats); 542 543 return ret; 544 } 545