1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP plane manipulation routines. 11 */ 12 13 #include <linux/iommu.h> 14 15 #include <drm/drmP.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_fb_cma_helper.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_gem_framebuffer_helper.h> 21 #include <drm/drm_plane_helper.h> 22 #include <drm/drm_print.h> 23 24 #include "malidp_hw.h" 25 #include "malidp_drv.h" 26 27 /* Layer specific register offsets */ 28 #define MALIDP_LAYER_FORMAT 0x000 29 #define LAYER_FORMAT_MASK 0x3f 30 #define MALIDP_LAYER_CONTROL 0x004 31 #define LAYER_ENABLE (1 << 0) 32 #define LAYER_FLOWCFG_MASK 7 33 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) 34 #define LAYER_FLOWCFG_SCALE_SE 3 35 #define LAYER_ROT_OFFSET 8 36 #define LAYER_H_FLIP (1 << 10) 37 #define LAYER_V_FLIP (1 << 11) 38 #define LAYER_ROT_MASK (0xf << 8) 39 #define LAYER_COMP_MASK (0x3 << 12) 40 #define LAYER_COMP_PIXEL (0x3 << 12) 41 #define LAYER_COMP_PLANE (0x2 << 12) 42 #define LAYER_PMUL_ENABLE (0x1 << 14) 43 #define LAYER_ALPHA_OFFSET (16) 44 #define LAYER_ALPHA_MASK (0xff) 45 #define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) 46 #define MALIDP_LAYER_COMPOSE 0x008 47 #define MALIDP_LAYER_SIZE 0x00c 48 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) 49 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) 50 #define MALIDP_LAYER_COMP_SIZE 0x010 51 #define MALIDP_LAYER_OFFSET 0x014 52 #define MALIDP550_LS_ENABLE 0x01c 53 #define MALIDP550_LS_R1_IN_SIZE 0x020 54 55 #define MODIFIERS_COUNT_MAX 15 56 57 /* 58 * This 4-entry look-up-table is used to determine the full 8-bit alpha value 59 * for formats with 1- or 2-bit alpha channels. 60 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% 61 * opacity for 2-bit formats. 62 */ 63 #define MALIDP_ALPHA_LUT 0xffaa5500 64 65 /* page sizes the MMU prefetcher can support */ 66 #define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K) 67 #define MALIDP_MMU_PREFETCH_FULL_PGSIZES (SZ_1M | SZ_2M) 68 69 /* readahead for partial-frame prefetch */ 70 #define MALIDP_MMU_PREFETCH_READAHEAD 8 71 72 static void malidp_de_plane_destroy(struct drm_plane *plane) 73 { 74 struct malidp_plane *mp = to_malidp_plane(plane); 75 76 drm_plane_cleanup(plane); 77 kfree(mp); 78 } 79 80 /* 81 * Replicate what the default ->reset hook does: free the state pointer and 82 * allocate a new empty object. We just need enough space to store 83 * a malidp_plane_state instead of a drm_plane_state. 84 */ 85 static void malidp_plane_reset(struct drm_plane *plane) 86 { 87 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); 88 89 if (state) 90 __drm_atomic_helper_plane_destroy_state(&state->base); 91 kfree(state); 92 plane->state = NULL; 93 state = kzalloc(sizeof(*state), GFP_KERNEL); 94 if (state) 95 __drm_atomic_helper_plane_reset(plane, &state->base); 96 } 97 98 static struct 99 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 100 { 101 struct malidp_plane_state *state, *m_state; 102 103 if (!plane->state) 104 return NULL; 105 106 state = kmalloc(sizeof(*state), GFP_KERNEL); 107 if (!state) 108 return NULL; 109 110 m_state = to_malidp_plane_state(plane->state); 111 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); 112 state->rotmem_size = m_state->rotmem_size; 113 state->format = m_state->format; 114 state->n_planes = m_state->n_planes; 115 116 state->mmu_prefetch_mode = m_state->mmu_prefetch_mode; 117 state->mmu_prefetch_pgsize = m_state->mmu_prefetch_pgsize; 118 119 return &state->base; 120 } 121 122 static void malidp_destroy_plane_state(struct drm_plane *plane, 123 struct drm_plane_state *state) 124 { 125 struct malidp_plane_state *m_state = to_malidp_plane_state(state); 126 127 __drm_atomic_helper_plane_destroy_state(state); 128 kfree(m_state); 129 } 130 131 static const char * const prefetch_mode_names[] = { 132 [MALIDP_PREFETCH_MODE_NONE] = "MMU_PREFETCH_NONE", 133 [MALIDP_PREFETCH_MODE_PARTIAL] = "MMU_PREFETCH_PARTIAL", 134 [MALIDP_PREFETCH_MODE_FULL] = "MMU_PREFETCH_FULL", 135 }; 136 137 static void malidp_plane_atomic_print_state(struct drm_printer *p, 138 const struct drm_plane_state *state) 139 { 140 struct malidp_plane_state *ms = to_malidp_plane_state(state); 141 142 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); 143 drm_printf(p, "\tformat_id=%u\n", ms->format); 144 drm_printf(p, "\tn_planes=%u\n", ms->n_planes); 145 drm_printf(p, "\tmmu_prefetch_mode=%s\n", 146 prefetch_mode_names[ms->mmu_prefetch_mode]); 147 drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize); 148 } 149 150 bool malidp_format_mod_supported(struct drm_device *drm, 151 u32 format, u64 modifier) 152 { 153 const struct drm_format_info *info; 154 const u64 *modifiers; 155 struct malidp_drm *malidp = drm->dev_private; 156 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 157 158 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) 159 return false; 160 161 /* Some pixel formats are supported without any modifier */ 162 if (modifier == DRM_FORMAT_MOD_LINEAR) { 163 /* 164 * However these pixel formats need to be supported with 165 * modifiers only 166 */ 167 return !malidp_hw_format_is_afbc_only(format); 168 } 169 170 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_ARM) { 171 DRM_ERROR("Unknown modifier (not Arm)\n"); 172 return false; 173 } 174 175 if (modifier & 176 ~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) { 177 DRM_DEBUG_KMS("Unsupported modifiers\n"); 178 return false; 179 } 180 181 modifiers = malidp_format_modifiers; 182 183 /* SPLIT buffers must use SPARSE layout */ 184 if (WARN_ON_ONCE((modifier & AFBC_SPLIT) && !(modifier & AFBC_SPARSE))) 185 return false; 186 187 /* CBR only applies to YUV formats, where YTR should be always 0 */ 188 if (WARN_ON_ONCE((modifier & AFBC_CBR) && (modifier & AFBC_YTR))) 189 return false; 190 191 while (*modifiers != DRM_FORMAT_MOD_INVALID) { 192 if (*modifiers == modifier) 193 break; 194 195 modifiers++; 196 } 197 198 /* return false, if the modifier was not found */ 199 if (*modifiers == DRM_FORMAT_MOD_INVALID) { 200 DRM_DEBUG_KMS("Unsupported modifier\n"); 201 return false; 202 } 203 204 info = drm_format_info(format); 205 206 if (info->num_planes != 1) { 207 DRM_DEBUG_KMS("AFBC buffers expect one plane\n"); 208 return false; 209 } 210 211 if (malidp_hw_format_is_linear_only(format) == true) { 212 DRM_DEBUG_KMS("Given format (0x%x) is supported is linear mode only\n", 213 format); 214 return false; 215 } 216 217 /* 218 * RGB formats need to provide YTR modifier and YUV formats should not 219 * provide YTR modifier. 220 */ 221 if (!(info->is_yuv) != !!(modifier & AFBC_FORMAT_MOD_YTR)) { 222 DRM_DEBUG_KMS("AFBC_FORMAT_MOD_YTR is %s for %s formats\n", 223 info->is_yuv ? "disallowed" : "mandatory", 224 info->is_yuv ? "YUV" : "RGB"); 225 return false; 226 } 227 228 if (modifier & AFBC_SPLIT) { 229 if (!info->is_yuv) { 230 if (drm_format_plane_cpp(format, 0) <= 2) { 231 DRM_DEBUG_KMS("RGB formats <= 16bpp are not supported with SPLIT\n"); 232 return false; 233 } 234 } 235 236 if ((drm_format_horz_chroma_subsampling(format) != 1) || 237 (drm_format_vert_chroma_subsampling(format) != 1)) { 238 if (!(format == DRM_FORMAT_YUV420_10BIT && 239 (map->features & MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT))) { 240 DRM_DEBUG_KMS("Formats which are sub-sampled should never be split\n"); 241 return false; 242 } 243 } 244 } 245 246 if (modifier & AFBC_CBR) { 247 if ((drm_format_horz_chroma_subsampling(format) == 1) || 248 (drm_format_vert_chroma_subsampling(format) == 1)) { 249 DRM_DEBUG_KMS("Formats which are not sub-sampled should not have CBR set\n"); 250 return false; 251 } 252 } 253 254 return true; 255 } 256 257 static bool malidp_format_mod_supported_per_plane(struct drm_plane *plane, 258 u32 format, u64 modifier) 259 { 260 return malidp_format_mod_supported(plane->dev, format, modifier); 261 } 262 263 static const struct drm_plane_funcs malidp_de_plane_funcs = { 264 .update_plane = drm_atomic_helper_update_plane, 265 .disable_plane = drm_atomic_helper_disable_plane, 266 .destroy = malidp_de_plane_destroy, 267 .reset = malidp_plane_reset, 268 .atomic_duplicate_state = malidp_duplicate_plane_state, 269 .atomic_destroy_state = malidp_destroy_plane_state, 270 .atomic_print_state = malidp_plane_atomic_print_state, 271 .format_mod_supported = malidp_format_mod_supported_per_plane, 272 }; 273 274 static int malidp_se_check_scaling(struct malidp_plane *mp, 275 struct drm_plane_state *state) 276 { 277 struct drm_crtc_state *crtc_state = 278 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 279 struct malidp_crtc_state *mc; 280 u32 src_w, src_h; 281 int ret; 282 283 if (!crtc_state) 284 return -EINVAL; 285 286 mc = to_malidp_crtc_state(crtc_state); 287 288 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 289 0, INT_MAX, true, true); 290 if (ret) 291 return ret; 292 293 if (state->rotation & MALIDP_ROTATED_MASK) { 294 src_w = state->src_h >> 16; 295 src_h = state->src_w >> 16; 296 } else { 297 src_w = state->src_w >> 16; 298 src_h = state->src_h >> 16; 299 } 300 301 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { 302 /* Scaling not necessary for this plane. */ 303 mc->scaled_planes_mask &= ~(mp->layer->id); 304 return 0; 305 } 306 307 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) 308 return -EINVAL; 309 310 mc->scaled_planes_mask |= mp->layer->id; 311 /* Defer scaling requirements calculation to the crtc check. */ 312 return 0; 313 } 314 315 static u32 malidp_get_pgsize_bitmap(struct malidp_plane *mp) 316 { 317 u32 pgsize_bitmap = 0; 318 319 if (iommu_present(&platform_bus_type)) { 320 struct iommu_domain *mmu_dom = 321 iommu_get_domain_for_dev(mp->base.dev->dev); 322 323 if (mmu_dom) 324 pgsize_bitmap = mmu_dom->pgsize_bitmap; 325 } 326 327 return pgsize_bitmap; 328 } 329 330 /* 331 * Check if the framebuffer is entirely made up of pages at least pgsize in 332 * size. Only a heuristic: assumes that each scatterlist entry has been aligned 333 * to the largest page size smaller than its length and that the MMU maps to 334 * the largest page size possible. 335 */ 336 static bool malidp_check_pages_threshold(struct malidp_plane_state *ms, 337 u32 pgsize) 338 { 339 int i; 340 341 for (i = 0; i < ms->n_planes; i++) { 342 struct drm_gem_object *obj; 343 struct drm_gem_cma_object *cma_obj; 344 struct sg_table *sgt; 345 struct scatterlist *sgl; 346 347 obj = drm_gem_fb_get_obj(ms->base.fb, i); 348 cma_obj = to_drm_gem_cma_obj(obj); 349 350 if (cma_obj->sgt) 351 sgt = cma_obj->sgt; 352 else 353 sgt = obj->dev->driver->gem_prime_get_sg_table(obj); 354 355 if (!sgt) 356 return false; 357 358 sgl = sgt->sgl; 359 360 while (sgl) { 361 if (sgl->length < pgsize) { 362 if (!cma_obj->sgt) 363 kfree(sgt); 364 return false; 365 } 366 367 sgl = sg_next(sgl); 368 } 369 if (!cma_obj->sgt) 370 kfree(sgt); 371 } 372 373 return true; 374 } 375 376 /* 377 * Check if it is possible to enable partial-frame MMU prefetch given the 378 * current format, AFBC state and rotation. 379 */ 380 static bool malidp_partial_prefetch_supported(u32 format, u64 modifier, 381 unsigned int rotation) 382 { 383 bool afbc, sparse; 384 385 /* rotation and horizontal flip not supported for partial prefetch */ 386 if (rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 387 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X)) 388 return false; 389 390 afbc = modifier & DRM_FORMAT_MOD_ARM_AFBC(0); 391 sparse = modifier & AFBC_FORMAT_MOD_SPARSE; 392 393 switch (format) { 394 case DRM_FORMAT_ARGB2101010: 395 case DRM_FORMAT_RGBA1010102: 396 case DRM_FORMAT_BGRA1010102: 397 case DRM_FORMAT_ARGB8888: 398 case DRM_FORMAT_RGBA8888: 399 case DRM_FORMAT_BGRA8888: 400 case DRM_FORMAT_XRGB8888: 401 case DRM_FORMAT_XBGR8888: 402 case DRM_FORMAT_RGBX8888: 403 case DRM_FORMAT_BGRX8888: 404 case DRM_FORMAT_RGB888: 405 case DRM_FORMAT_RGBA5551: 406 case DRM_FORMAT_RGB565: 407 /* always supported */ 408 return true; 409 410 case DRM_FORMAT_ABGR2101010: 411 case DRM_FORMAT_ABGR8888: 412 case DRM_FORMAT_ABGR1555: 413 case DRM_FORMAT_BGR565: 414 /* supported, but if AFBC then must be sparse mode */ 415 return (!afbc) || (afbc && sparse); 416 417 case DRM_FORMAT_BGR888: 418 /* supported, but not for AFBC */ 419 return !afbc; 420 421 case DRM_FORMAT_YUYV: 422 case DRM_FORMAT_UYVY: 423 case DRM_FORMAT_NV12: 424 case DRM_FORMAT_YUV420: 425 /* not supported */ 426 return false; 427 428 default: 429 return false; 430 } 431 } 432 433 /* 434 * Select the preferred MMU prefetch mode. Full-frame prefetch is preferred as 435 * long as the framebuffer is all large pages. Otherwise partial-frame prefetch 436 * is selected as long as it is supported for the current format. The selected 437 * page size for prefetch is returned in pgsize_bitmap. 438 */ 439 static enum mmu_prefetch_mode malidp_mmu_prefetch_select_mode 440 (struct malidp_plane_state *ms, u32 *pgsize_bitmap) 441 { 442 u32 pgsizes; 443 444 /* get the full-frame prefetch page size(s) supported by the MMU */ 445 pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_FULL_PGSIZES; 446 447 while (pgsizes) { 448 u32 largest_pgsize = 1 << __fls(pgsizes); 449 450 if (malidp_check_pages_threshold(ms, largest_pgsize)) { 451 *pgsize_bitmap = largest_pgsize; 452 return MALIDP_PREFETCH_MODE_FULL; 453 } 454 455 pgsizes -= largest_pgsize; 456 } 457 458 /* get the partial-frame prefetch page size(s) supported by the MMU */ 459 pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES; 460 461 if (malidp_partial_prefetch_supported(ms->base.fb->format->format, 462 ms->base.fb->modifier, 463 ms->base.rotation)) { 464 /* partial prefetch using the smallest page size */ 465 *pgsize_bitmap = 1 << __ffs(pgsizes); 466 return MALIDP_PREFETCH_MODE_PARTIAL; 467 } 468 *pgsize_bitmap = 0; 469 return MALIDP_PREFETCH_MODE_NONE; 470 } 471 472 static u32 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode, 473 u8 readahead, u8 n_planes, u32 pgsize) 474 { 475 u32 mmu_ctrl = 0; 476 477 if (mode != MALIDP_PREFETCH_MODE_NONE) { 478 mmu_ctrl |= MALIDP_MMU_CTRL_EN; 479 480 if (mode == MALIDP_PREFETCH_MODE_PARTIAL) { 481 mmu_ctrl |= MALIDP_MMU_CTRL_MODE; 482 mmu_ctrl |= MALIDP_MMU_CTRL_PP_NUM_REQ(readahead); 483 } 484 485 if (pgsize == SZ_64K || pgsize == SZ_2M) { 486 int i; 487 488 for (i = 0; i < n_planes; i++) 489 mmu_ctrl |= MALIDP_MMU_CTRL_PX_PS(i); 490 } 491 } 492 493 return mmu_ctrl; 494 } 495 496 static void malidp_de_prefetch_settings(struct malidp_plane *mp, 497 struct malidp_plane_state *ms) 498 { 499 if (!mp->layer->mmu_ctrl_offset) 500 return; 501 502 /* get the page sizes supported by the MMU */ 503 ms->mmu_prefetch_pgsize = malidp_get_pgsize_bitmap(mp); 504 ms->mmu_prefetch_mode = 505 malidp_mmu_prefetch_select_mode(ms, &ms->mmu_prefetch_pgsize); 506 } 507 508 static int malidp_de_plane_check(struct drm_plane *plane, 509 struct drm_plane_state *state) 510 { 511 struct malidp_plane *mp = to_malidp_plane(plane); 512 struct malidp_plane_state *ms = to_malidp_plane_state(state); 513 bool rotated = state->rotation & MALIDP_ROTATED_MASK; 514 struct drm_framebuffer *fb; 515 u16 pixel_alpha = state->pixel_blend_mode; 516 int i, ret; 517 unsigned int block_w, block_h; 518 519 if (!state->crtc || !state->fb) 520 return 0; 521 522 fb = state->fb; 523 524 ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, 525 mp->layer->id, fb->format->format, 526 !!fb->modifier); 527 if (ms->format == MALIDP_INVALID_FORMAT_ID) 528 return -EINVAL; 529 530 ms->n_planes = fb->format->num_planes; 531 for (i = 0; i < ms->n_planes; i++) { 532 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); 533 534 if (((fb->pitches[i] * drm_format_info_block_height(fb->format, i)) 535 & (alignment - 1)) && !(fb->modifier)) { 536 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", 537 fb->pitches[i], i); 538 return -EINVAL; 539 } 540 } 541 542 block_w = drm_format_info_block_width(fb->format, 0); 543 block_h = drm_format_info_block_height(fb->format, 0); 544 if (fb->width % block_w || fb->height % block_h) { 545 DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes"); 546 return -EINVAL; 547 } 548 if ((state->src_x >> 16) % block_w || (state->src_y >> 16) % block_h) { 549 DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes"); 550 return -EINVAL; 551 } 552 553 if ((state->crtc_w > mp->hwdev->max_line_size) || 554 (state->crtc_h > mp->hwdev->max_line_size) || 555 (state->crtc_w < mp->hwdev->min_line_size) || 556 (state->crtc_h < mp->hwdev->min_line_size)) 557 return -EINVAL; 558 559 /* 560 * DP550/650 video layers can accept 3 plane formats only if 561 * fb->pitches[1] == fb->pitches[2] since they don't have a 562 * third plane stride register. 563 */ 564 if (ms->n_planes == 3 && 565 !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && 566 (state->fb->pitches[1] != state->fb->pitches[2])) 567 return -EINVAL; 568 569 ret = malidp_se_check_scaling(mp, state); 570 if (ret) 571 return ret; 572 573 /* validate the rotation constraints for each layer */ 574 if (state->rotation != DRM_MODE_ROTATE_0) { 575 if (mp->layer->rot == ROTATE_NONE) 576 return -EINVAL; 577 if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier)) 578 return -EINVAL; 579 /* 580 * packed RGB888 / BGR888 can't be rotated or flipped 581 * unless they are stored in a compressed way 582 */ 583 if ((fb->format->format == DRM_FORMAT_RGB888 || 584 fb->format->format == DRM_FORMAT_BGR888) && !(fb->modifier)) 585 return -EINVAL; 586 } 587 588 /* SMART layer does not support AFBC */ 589 if (mp->layer->id == DE_SMART && fb->modifier) { 590 DRM_ERROR("AFBC framebuffer not supported in SMART layer"); 591 return -EINVAL; 592 } 593 594 ms->rotmem_size = 0; 595 if (state->rotation & MALIDP_ROTATED_MASK) { 596 int val; 597 598 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, 599 state->crtc_h, 600 fb->format->format, 601 !!(fb->modifier)); 602 if (val < 0) 603 return val; 604 605 ms->rotmem_size = val; 606 } 607 608 /* HW can't support plane + pixel blending */ 609 if ((state->alpha != DRM_BLEND_ALPHA_OPAQUE) && 610 (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) && 611 fb->format->has_alpha) 612 return -EINVAL; 613 614 malidp_de_prefetch_settings(mp, ms); 615 616 return 0; 617 } 618 619 static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 620 int num_planes, unsigned int pitches[3]) 621 { 622 int i; 623 int num_strides = num_planes; 624 625 if (!mp->layer->stride_offset) 626 return; 627 628 if (num_planes == 3) 629 num_strides = (mp->hwdev->hw->features & 630 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; 631 632 /* 633 * The drm convention for pitch is that it needs to cover width * cpp, 634 * but our hardware wants the pitch/stride to cover all rows included 635 * in a tile. 636 */ 637 for (i = 0; i < num_strides; ++i) { 638 unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i); 639 640 malidp_hw_write(mp->hwdev, pitches[i] * block_h, 641 mp->layer->base + 642 mp->layer->stride_offset + i * 4); 643 } 644 } 645 646 static const s16 647 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = { 648 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 649 1192, 0, 1634, 650 1192, -401, -832, 651 1192, 2066, 0, 652 64, 512, 512 653 }, 654 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 655 1024, 0, 1436, 656 1024, -352, -731, 657 1024, 1815, 0, 658 0, 512, 512 659 }, 660 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 661 1192, 0, 1836, 662 1192, -218, -546, 663 1192, 2163, 0, 664 64, 512, 512 665 }, 666 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 667 1024, 0, 1613, 668 1024, -192, -479, 669 1024, 1900, 0, 670 0, 512, 512 671 }, 672 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 673 1024, 0, 1476, 674 1024, -165, -572, 675 1024, 1884, 0, 676 0, 512, 512 677 }, 678 [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = { 679 1024, 0, 1510, 680 1024, -168, -585, 681 1024, 1927, 0, 682 0, 512, 512 683 } 684 }; 685 686 static void malidp_de_set_color_encoding(struct malidp_plane *plane, 687 enum drm_color_encoding enc, 688 enum drm_color_range range) 689 { 690 unsigned int i; 691 692 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) { 693 /* coefficients are signed, two's complement values */ 694 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], 695 plane->layer->base + plane->layer->yuv2rgb_offset + 696 i * 4); 697 } 698 } 699 700 static void malidp_de_set_mmu_control(struct malidp_plane *mp, 701 struct malidp_plane_state *ms) 702 { 703 u32 mmu_ctrl; 704 705 /* check hardware supports MMU prefetch */ 706 if (!mp->layer->mmu_ctrl_offset) 707 return; 708 709 mmu_ctrl = malidp_calc_mmu_control_value(ms->mmu_prefetch_mode, 710 MALIDP_MMU_PREFETCH_READAHEAD, 711 ms->n_planes, 712 ms->mmu_prefetch_pgsize); 713 714 malidp_hw_write(mp->hwdev, mmu_ctrl, 715 mp->layer->base + mp->layer->mmu_ctrl_offset); 716 } 717 718 static void malidp_set_plane_base_addr(struct drm_framebuffer *fb, 719 struct malidp_plane *mp, 720 int plane_index) 721 { 722 dma_addr_t paddr; 723 u16 ptr; 724 struct drm_plane *plane = &mp->base; 725 bool afbc = fb->modifier ? true : false; 726 727 ptr = mp->layer->ptr + (plane_index << 4); 728 729 /* 730 * drm_fb_cma_get_gem_addr() alters the physical base address of the 731 * framebuffer as per the plane's src_x, src_y co-ordinates (ie to 732 * take care of source cropping). 733 * For AFBC, this is not needed as the cropping is handled by _AD_CROP_H 734 * and _AD_CROP_V registers. 735 */ 736 if (!afbc) { 737 paddr = drm_fb_cma_get_gem_addr(fb, plane->state, 738 plane_index); 739 } else { 740 struct drm_gem_cma_object *obj; 741 742 obj = drm_fb_cma_get_gem_obj(fb, plane_index); 743 744 if (WARN_ON(!obj)) 745 return; 746 paddr = obj->paddr; 747 } 748 749 malidp_hw_write(mp->hwdev, lower_32_bits(paddr), ptr); 750 malidp_hw_write(mp->hwdev, upper_32_bits(paddr), ptr + 4); 751 } 752 753 static void malidp_de_set_plane_afbc(struct drm_plane *plane) 754 { 755 struct malidp_plane *mp; 756 u32 src_w, src_h, val = 0, src_x, src_y; 757 struct drm_framebuffer *fb = plane->state->fb; 758 759 mp = to_malidp_plane(plane); 760 761 /* no afbc_decoder_offset means AFBC is not supported on this plane */ 762 if (!mp->layer->afbc_decoder_offset) 763 return; 764 765 if (!fb->modifier) { 766 malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset); 767 return; 768 } 769 770 /* convert src values from Q16 fixed point to integer */ 771 src_w = plane->state->src_w >> 16; 772 src_h = plane->state->src_h >> 16; 773 src_x = plane->state->src_x >> 16; 774 src_y = plane->state->src_y >> 16; 775 776 val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) | 777 src_x; 778 malidp_hw_write(mp->hwdev, val, 779 mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_H); 780 781 val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) | 782 src_y; 783 malidp_hw_write(mp->hwdev, val, 784 mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_V); 785 786 val = MALIDP_AD_EN; 787 if (fb->modifier & AFBC_FORMAT_MOD_SPLIT) 788 val |= MALIDP_AD_BS; 789 if (fb->modifier & AFBC_FORMAT_MOD_YTR) 790 val |= MALIDP_AD_YTR; 791 792 malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset); 793 } 794 795 static void malidp_de_plane_update(struct drm_plane *plane, 796 struct drm_plane_state *old_state) 797 { 798 struct malidp_plane *mp; 799 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); 800 struct drm_plane_state *state = plane->state; 801 u16 pixel_alpha = state->pixel_blend_mode; 802 u8 plane_alpha = state->alpha >> 8; 803 u32 src_w, src_h, dest_w, dest_h, val; 804 int i; 805 struct drm_framebuffer *fb = plane->state->fb; 806 807 mp = to_malidp_plane(plane); 808 809 /* 810 * For AFBC framebuffer, use the framebuffer width and height for 811 * configuring layer input size register. 812 */ 813 if (fb->modifier) { 814 src_w = fb->width; 815 src_h = fb->height; 816 } else { 817 /* convert src values from Q16 fixed point to integer */ 818 src_w = state->src_w >> 16; 819 src_h = state->src_h >> 16; 820 } 821 822 dest_w = state->crtc_w; 823 dest_h = state->crtc_h; 824 825 val = malidp_hw_read(mp->hwdev, mp->layer->base); 826 val = (val & ~LAYER_FORMAT_MASK) | ms->format; 827 malidp_hw_write(mp->hwdev, val, mp->layer->base); 828 829 for (i = 0; i < ms->n_planes; i++) 830 malidp_set_plane_base_addr(fb, mp, i); 831 832 malidp_de_set_mmu_control(mp, ms); 833 834 malidp_de_set_plane_pitches(mp, ms->n_planes, 835 state->fb->pitches); 836 837 if ((plane->state->color_encoding != old_state->color_encoding) || 838 (plane->state->color_range != old_state->color_range)) 839 malidp_de_set_color_encoding(mp, plane->state->color_encoding, 840 plane->state->color_range); 841 842 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 843 mp->layer->base + MALIDP_LAYER_SIZE); 844 845 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), 846 mp->layer->base + MALIDP_LAYER_COMP_SIZE); 847 848 malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) | 849 LAYER_V_VAL(state->crtc_y), 850 mp->layer->base + MALIDP_LAYER_OFFSET); 851 852 if (mp->layer->id == DE_SMART) { 853 /* 854 * Enable the first rectangle in the SMART layer to be 855 * able to use it as a drm plane. 856 */ 857 malidp_hw_write(mp->hwdev, 1, 858 mp->layer->base + MALIDP550_LS_ENABLE); 859 malidp_hw_write(mp->hwdev, 860 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), 861 mp->layer->base + MALIDP550_LS_R1_IN_SIZE); 862 } 863 864 malidp_de_set_plane_afbc(plane); 865 866 /* first clear the rotation bits */ 867 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); 868 val &= ~LAYER_ROT_MASK; 869 870 /* setup the rotation and axis flip bits */ 871 if (state->rotation & DRM_MODE_ROTATE_MASK) 872 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << 873 LAYER_ROT_OFFSET; 874 if (state->rotation & DRM_MODE_REFLECT_X) 875 val |= LAYER_H_FLIP; 876 if (state->rotation & DRM_MODE_REFLECT_Y) 877 val |= LAYER_V_FLIP; 878 879 val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff)); 880 881 if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) { 882 val |= LAYER_COMP_PLANE; 883 } else if (state->fb->format->has_alpha) { 884 /* We only care about blend mode if the format has alpha */ 885 switch (pixel_alpha) { 886 case DRM_MODE_BLEND_PREMULTI: 887 val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE; 888 break; 889 case DRM_MODE_BLEND_COVERAGE: 890 val |= LAYER_COMP_PIXEL; 891 break; 892 } 893 } 894 val |= LAYER_ALPHA(plane_alpha); 895 896 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); 897 if (state->crtc) { 898 struct malidp_crtc_state *m = 899 to_malidp_crtc_state(state->crtc->state); 900 901 if (m->scaler_config.scale_enable && 902 m->scaler_config.plane_src_id == mp->layer->id) 903 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); 904 } 905 906 /* set the 'enable layer' bit */ 907 val |= LAYER_ENABLE; 908 909 malidp_hw_write(mp->hwdev, val, 910 mp->layer->base + MALIDP_LAYER_CONTROL); 911 } 912 913 static void malidp_de_plane_disable(struct drm_plane *plane, 914 struct drm_plane_state *state) 915 { 916 struct malidp_plane *mp = to_malidp_plane(plane); 917 918 malidp_hw_clearbits(mp->hwdev, 919 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), 920 mp->layer->base + MALIDP_LAYER_CONTROL); 921 } 922 923 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { 924 .atomic_check = malidp_de_plane_check, 925 .atomic_update = malidp_de_plane_update, 926 .atomic_disable = malidp_de_plane_disable, 927 }; 928 929 int malidp_de_planes_init(struct drm_device *drm) 930 { 931 struct malidp_drm *malidp = drm->dev_private; 932 const struct malidp_hw_regmap *map = &malidp->dev->hw->map; 933 struct malidp_plane *plane = NULL; 934 enum drm_plane_type plane_type; 935 unsigned long crtcs = 1 << drm->mode_config.num_crtc; 936 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | 937 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 938 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 939 BIT(DRM_MODE_BLEND_PREMULTI) | 940 BIT(DRM_MODE_BLEND_COVERAGE); 941 u32 *formats; 942 int ret, i, j, n; 943 944 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); 945 if (!formats) { 946 ret = -ENOMEM; 947 goto cleanup; 948 } 949 950 for (i = 0; i < map->n_layers; i++) { 951 u8 id = map->layers[i].id; 952 953 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 954 if (!plane) { 955 ret = -ENOMEM; 956 goto cleanup; 957 } 958 959 /* build the list of DRM supported formats based on the map */ 960 for (n = 0, j = 0; j < map->n_pixel_formats; j++) { 961 if ((map->pixel_formats[j].layer & id) == id) 962 formats[n++] = map->pixel_formats[j].format; 963 } 964 965 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 966 DRM_PLANE_TYPE_OVERLAY; 967 ret = drm_universal_plane_init(drm, &plane->base, crtcs, 968 &malidp_de_plane_funcs, formats, 969 n, NULL, plane_type, NULL); 970 if (ret < 0) 971 goto cleanup; 972 973 drm_plane_helper_add(&plane->base, 974 &malidp_de_plane_helper_funcs); 975 plane->hwdev = malidp->dev; 976 plane->layer = &map->layers[i]; 977 978 drm_plane_create_alpha_property(&plane->base); 979 drm_plane_create_blend_mode_property(&plane->base, blend_caps); 980 981 if (id == DE_SMART) { 982 /* Skip the features which the SMART layer doesn't have. */ 983 continue; 984 } 985 986 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); 987 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, 988 plane->layer->base + MALIDP_LAYER_COMPOSE); 989 990 /* Attach the YUV->RGB property only to video layers */ 991 if (id & (DE_VIDEO1 | DE_VIDEO2)) { 992 /* default encoding for YUV->RGB is BT601 NARROW */ 993 enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; 994 enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; 995 996 ret = drm_plane_create_color_properties(&plane->base, 997 BIT(DRM_COLOR_YCBCR_BT601) | \ 998 BIT(DRM_COLOR_YCBCR_BT709) | \ 999 BIT(DRM_COLOR_YCBCR_BT2020), 1000 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ 1001 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1002 enc, range); 1003 if (!ret) 1004 /* program the HW registers */ 1005 malidp_de_set_color_encoding(plane, enc, range); 1006 else 1007 DRM_WARN("Failed to create video layer %d color properties\n", id); 1008 } 1009 } 1010 1011 kfree(formats); 1012 1013 return 0; 1014 1015 cleanup: 1016 kfree(formats); 1017 1018 return ret; 1019 } 1020