1 /* 2 * 3 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP hardware manipulation routines. 11 */ 12 13 #ifndef __MALIDP_HW_H__ 14 #define __MALIDP_HW_H__ 15 16 #include <linux/bitops.h> 17 #include "malidp_regs.h" 18 19 struct videomode; 20 struct clk; 21 22 /* Mali DP IP blocks */ 23 enum { 24 MALIDP_DE_BLOCK = 0, 25 MALIDP_SE_BLOCK, 26 MALIDP_DC_BLOCK 27 }; 28 29 /* Mali DP layer IDs */ 30 enum { 31 DE_VIDEO1 = BIT(0), 32 DE_GRAPHICS1 = BIT(1), 33 DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34 DE_VIDEO2 = BIT(3), 35 DE_SMART = BIT(4), 36 }; 37 38 struct malidp_format_id { 39 u32 format; /* DRM fourcc */ 40 u8 layer; /* bitmask of layers supporting it */ 41 u8 id; /* used internally */ 42 }; 43 44 #define MALIDP_INVALID_FORMAT_ID 0xff 45 46 /* 47 * hide the differences between register maps 48 * by using a common structure to hold the 49 * base register offsets 50 */ 51 52 struct malidp_irq_map { 53 u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 54 u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 55 }; 56 57 struct malidp_layer { 58 u16 id; /* layer ID */ 59 u16 base; /* address offset for the register bank */ 60 u16 ptr; /* address offset for the pointer register */ 61 u16 stride_offset; /* Offset to the first stride register. */ 62 }; 63 64 /* regmap features */ 65 #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0) 66 67 struct malidp_hw_regmap { 68 /* address offset of the DE register bank */ 69 /* is always 0x0000 */ 70 /* address offset of the SE registers bank */ 71 const u16 se_base; 72 /* address offset of the DC registers bank */ 73 const u16 dc_base; 74 75 /* address offset for the output depth register */ 76 const u16 out_depth_base; 77 78 /* bitmap with register map features */ 79 const u8 features; 80 81 /* list of supported layers */ 82 const u8 n_layers; 83 const struct malidp_layer *layers; 84 85 const struct malidp_irq_map de_irq_map; 86 const struct malidp_irq_map se_irq_map; 87 const struct malidp_irq_map dc_irq_map; 88 89 /* list of supported pixel formats for each layer */ 90 const struct malidp_format_id *pixel_formats; 91 const u8 n_pixel_formats; 92 93 /* pitch alignment requirement in bytes */ 94 const u8 bus_align_bytes; 95 }; 96 97 /* device features */ 98 /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ 99 #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) 100 101 struct malidp_hw_device { 102 const struct malidp_hw_regmap map; 103 void __iomem *regs; 104 105 /* APB clock */ 106 struct clk *pclk; 107 /* AXI clock */ 108 struct clk *aclk; 109 /* main clock for display core */ 110 struct clk *mclk; 111 /* pixel clock for display core */ 112 struct clk *pxlclk; 113 114 /* 115 * Validate the driver instance against the hardware bits 116 */ 117 int (*query_hw)(struct malidp_hw_device *hwdev); 118 119 /* 120 * Set the hardware into config mode, ready to accept mode changes 121 */ 122 void (*enter_config_mode)(struct malidp_hw_device *hwdev); 123 124 /* 125 * Tell hardware to exit configuration mode 126 */ 127 void (*leave_config_mode)(struct malidp_hw_device *hwdev); 128 129 /* 130 * Query if hardware is in configuration mode 131 */ 132 bool (*in_config_mode)(struct malidp_hw_device *hwdev); 133 134 /* 135 * Set configuration valid flag for hardware parameters that can 136 * be changed outside the configuration mode. Hardware will use 137 * the new settings when config valid is set after the end of the 138 * current buffer scanout 139 */ 140 void (*set_config_valid)(struct malidp_hw_device *hwdev); 141 142 /* 143 * Set a new mode in hardware. Requires the hardware to be in 144 * configuration mode before this function is called. 145 */ 146 void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 147 148 /* 149 * Calculate the required rotation memory given the active area 150 * and the buffer format. 151 */ 152 int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); 153 154 u8 features; 155 156 u8 min_line_size; 157 u16 max_line_size; 158 159 /* size of memory used for rotating layers, up to two banks available */ 160 u32 rotation_memory[2]; 161 }; 162 163 /* Supported variants of the hardware */ 164 enum { 165 MALIDP_500 = 0, 166 MALIDP_550, 167 MALIDP_650, 168 /* keep the next entry last */ 169 MALIDP_MAX_DEVICES 170 }; 171 172 extern const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES]; 173 174 static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 175 { 176 return readl(hwdev->regs + reg); 177 } 178 179 static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 180 u32 value, u32 reg) 181 { 182 writel(value, hwdev->regs + reg); 183 } 184 185 static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 186 u32 mask, u32 reg) 187 { 188 u32 data = malidp_hw_read(hwdev, reg); 189 190 data |= mask; 191 malidp_hw_write(hwdev, data, reg); 192 } 193 194 static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 195 u32 mask, u32 reg) 196 { 197 u32 data = malidp_hw_read(hwdev, reg); 198 199 data &= ~mask; 200 malidp_hw_write(hwdev, data, reg); 201 } 202 203 static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 204 u8 block) 205 { 206 switch (block) { 207 case MALIDP_SE_BLOCK: 208 return hwdev->map.se_base; 209 case MALIDP_DC_BLOCK: 210 return hwdev->map.dc_base; 211 } 212 213 return 0; 214 } 215 216 static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 217 u8 block, u32 irq) 218 { 219 u32 base = malidp_get_block_base(hwdev, block); 220 221 malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 222 } 223 224 static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 225 u8 block, u32 irq) 226 { 227 u32 base = malidp_get_block_base(hwdev, block); 228 229 malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 230 } 231 232 int malidp_de_irq_init(struct drm_device *drm, int irq); 233 void malidp_de_irq_fini(struct drm_device *drm); 234 int malidp_se_irq_init(struct drm_device *drm, int irq); 235 void malidp_se_irq_fini(struct drm_device *drm); 236 237 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 238 u8 layer_id, u32 format); 239 240 static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev, 241 unsigned int pitch) 242 { 243 return !(pitch & (hwdev->map.bus_align_bytes - 1)); 244 } 245 246 /* 247 * background color components are defined as 12bits values, 248 * they will be shifted right when stored on hardware that 249 * supports only 8bits per channel 250 */ 251 #define MALIDP_BGND_COLOR_R 0x000 252 #define MALIDP_BGND_COLOR_G 0x000 253 #define MALIDP_BGND_COLOR_B 0x000 254 255 #endif /* __MALIDP_HW_H__ */ 256