1 /* 2 * 3 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP hardware manipulation routines. 11 */ 12 13 #ifndef __MALIDP_HW_H__ 14 #define __MALIDP_HW_H__ 15 16 #include <linux/bitops.h> 17 #include "malidp_regs.h" 18 19 struct videomode; 20 struct clk; 21 22 /* Mali DP IP blocks */ 23 enum { 24 MALIDP_DE_BLOCK = 0, 25 MALIDP_SE_BLOCK, 26 MALIDP_DC_BLOCK 27 }; 28 29 /* Mali DP layer IDs */ 30 enum { 31 DE_VIDEO1 = BIT(0), 32 DE_GRAPHICS1 = BIT(1), 33 DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34 DE_VIDEO2 = BIT(3), 35 DE_SMART = BIT(4), 36 SE_MEMWRITE = BIT(5), 37 }; 38 39 enum rotation_features { 40 ROTATE_NONE, /* does not support rotation at all */ 41 ROTATE_ANY, /* supports rotation on any buffers */ 42 ROTATE_COMPRESSED, /* supports rotation only on compressed buffers */ 43 }; 44 45 struct malidp_format_id { 46 u32 format; /* DRM fourcc */ 47 u8 layer; /* bitmask of layers supporting it */ 48 u8 id; /* used internally */ 49 }; 50 51 #define MALIDP_INVALID_FORMAT_ID 0xff 52 53 /* 54 * hide the differences between register maps 55 * by using a common structure to hold the 56 * base register offsets 57 */ 58 59 struct malidp_irq_map { 60 u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 61 u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 62 u32 err_mask; /* mask of bits that represent errors */ 63 }; 64 65 struct malidp_layer { 66 u16 id; /* layer ID */ 67 u16 base; /* address offset for the register bank */ 68 u16 ptr; /* address offset for the pointer register */ 69 u16 stride_offset; /* offset to the first stride register. */ 70 s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */ 71 u16 mmu_ctrl_offset; /* offset to the MMU control register */ 72 enum rotation_features rot; /* type of rotation supported */ 73 }; 74 75 enum malidp_scaling_coeff_set { 76 MALIDP_UPSCALING_COEFFS = 1, 77 MALIDP_DOWNSCALING_1_5_COEFFS = 2, 78 MALIDP_DOWNSCALING_2_COEFFS = 3, 79 MALIDP_DOWNSCALING_2_75_COEFFS = 4, 80 MALIDP_DOWNSCALING_4_COEFFS = 5, 81 }; 82 83 struct malidp_se_config { 84 u8 scale_enable : 1; 85 u8 enhancer_enable : 1; 86 u8 hcoeff : 3; 87 u8 vcoeff : 3; 88 u8 plane_src_id; 89 u16 input_w, input_h; 90 u16 output_w, output_h; 91 u32 h_init_phase, h_delta_phase; 92 u32 v_init_phase, v_delta_phase; 93 }; 94 95 /* regmap features */ 96 #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0) 97 98 struct malidp_hw_regmap { 99 /* address offset of the DE register bank */ 100 /* is always 0x0000 */ 101 /* address offset of the DE coefficients registers */ 102 const u16 coeffs_base; 103 /* address offset of the SE registers bank */ 104 const u16 se_base; 105 /* address offset of the DC registers bank */ 106 const u16 dc_base; 107 108 /* address offset for the output depth register */ 109 const u16 out_depth_base; 110 111 /* bitmap with register map features */ 112 const u8 features; 113 114 /* list of supported layers */ 115 const u8 n_layers; 116 const struct malidp_layer *layers; 117 118 const struct malidp_irq_map de_irq_map; 119 const struct malidp_irq_map se_irq_map; 120 const struct malidp_irq_map dc_irq_map; 121 122 /* list of supported pixel formats for each layer */ 123 const struct malidp_format_id *pixel_formats; 124 const u8 n_pixel_formats; 125 126 /* pitch alignment requirement in bytes */ 127 const u8 bus_align_bytes; 128 }; 129 130 /* device features */ 131 /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ 132 #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) 133 134 struct malidp_hw_device; 135 136 /* 137 * Static structure containing hardware specific data and pointers to 138 * functions that behave differently between various versions of the IP. 139 */ 140 struct malidp_hw { 141 const struct malidp_hw_regmap map; 142 143 /* 144 * Validate the driver instance against the hardware bits 145 */ 146 int (*query_hw)(struct malidp_hw_device *hwdev); 147 148 /* 149 * Set the hardware into config mode, ready to accept mode changes 150 */ 151 void (*enter_config_mode)(struct malidp_hw_device *hwdev); 152 153 /* 154 * Tell hardware to exit configuration mode 155 */ 156 void (*leave_config_mode)(struct malidp_hw_device *hwdev); 157 158 /* 159 * Query if hardware is in configuration mode 160 */ 161 bool (*in_config_mode)(struct malidp_hw_device *hwdev); 162 163 /* 164 * Set/clear configuration valid flag for hardware parameters that can 165 * be changed outside the configuration mode to the given value. 166 * Hardware will use the new settings when config valid is set, 167 * after the end of the current buffer scanout, and will ignore 168 * any new values for those parameters if config valid flag is cleared 169 */ 170 void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value); 171 172 /* 173 * Set a new mode in hardware. Requires the hardware to be in 174 * configuration mode before this function is called. 175 */ 176 void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 177 178 /* 179 * Calculate the required rotation memory given the active area 180 * and the buffer format. 181 */ 182 int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); 183 184 int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev, 185 struct malidp_se_config *se_config, 186 struct malidp_se_config *old_config); 187 188 long (*se_calc_mclk)(struct malidp_hw_device *hwdev, 189 struct malidp_se_config *se_config, 190 struct videomode *vm); 191 /* 192 * Enable writing to memory the content of the next frame 193 * @param hwdev - malidp_hw_device structure containing the HW description 194 * @param addrs - array of addresses for each plane 195 * @param pitches - array of pitches for each plane 196 * @param num_planes - number of planes to be written 197 * @param w - width of the output frame 198 * @param h - height of the output frame 199 * @param fmt_id - internal format ID of output buffer 200 */ 201 int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, 202 s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id, 203 const s16 *rgb2yuv_coeffs); 204 205 /* 206 * Disable the writing to memory of the next frame's content. 207 */ 208 void (*disable_memwrite)(struct malidp_hw_device *hwdev); 209 210 u8 features; 211 }; 212 213 /* Supported variants of the hardware */ 214 enum { 215 MALIDP_500 = 0, 216 MALIDP_550, 217 MALIDP_650, 218 /* keep the next entry last */ 219 MALIDP_MAX_DEVICES 220 }; 221 222 extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES]; 223 224 /* 225 * Structure used by the driver during runtime operation. 226 */ 227 struct malidp_hw_device { 228 struct malidp_hw *hw; 229 void __iomem *regs; 230 231 /* APB clock */ 232 struct clk *pclk; 233 /* AXI clock */ 234 struct clk *aclk; 235 /* main clock for display core */ 236 struct clk *mclk; 237 /* pixel clock for display core */ 238 struct clk *pxlclk; 239 240 u8 min_line_size; 241 u16 max_line_size; 242 u32 output_color_depth; 243 244 /* track the device PM state */ 245 bool pm_suspended; 246 247 /* track the SE memory writeback state */ 248 u8 mw_state; 249 250 /* size of memory used for rotating layers, up to two banks available */ 251 u32 rotation_memory[2]; 252 }; 253 254 static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 255 { 256 WARN_ON(hwdev->pm_suspended); 257 return readl(hwdev->regs + reg); 258 } 259 260 static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 261 u32 value, u32 reg) 262 { 263 WARN_ON(hwdev->pm_suspended); 264 writel(value, hwdev->regs + reg); 265 } 266 267 static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 268 u32 mask, u32 reg) 269 { 270 u32 data = malidp_hw_read(hwdev, reg); 271 272 data |= mask; 273 malidp_hw_write(hwdev, data, reg); 274 } 275 276 static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 277 u32 mask, u32 reg) 278 { 279 u32 data = malidp_hw_read(hwdev, reg); 280 281 data &= ~mask; 282 malidp_hw_write(hwdev, data, reg); 283 } 284 285 static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 286 u8 block) 287 { 288 switch (block) { 289 case MALIDP_SE_BLOCK: 290 return hwdev->hw->map.se_base; 291 case MALIDP_DC_BLOCK: 292 return hwdev->hw->map.dc_base; 293 } 294 295 return 0; 296 } 297 298 static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 299 u8 block, u32 irq) 300 { 301 u32 base = malidp_get_block_base(hwdev, block); 302 303 malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 304 } 305 306 static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 307 u8 block, u32 irq) 308 { 309 u32 base = malidp_get_block_base(hwdev, block); 310 311 malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 312 } 313 314 int malidp_de_irq_init(struct drm_device *drm, int irq); 315 void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev); 316 void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev); 317 void malidp_de_irq_fini(struct malidp_hw_device *hwdev); 318 int malidp_se_irq_init(struct drm_device *drm, int irq); 319 void malidp_se_irq_fini(struct malidp_hw_device *hwdev); 320 321 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 322 u8 layer_id, u32 format); 323 324 static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated) 325 { 326 /* 327 * only hardware that cannot do 8 bytes bus alignments have further 328 * constraints on rotated planes 329 */ 330 if (hwdev->hw->map.bus_align_bytes == 8) 331 return 8; 332 else 333 return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0); 334 } 335 336 /* U16.16 */ 337 #define FP_1_00000 0x00010000 /* 1.0 */ 338 #define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */ 339 #define FP_0_50000 0x00008000 /* 0.5 = 1/2 */ 340 #define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */ 341 #define FP_0_25000 0x00004000 /* 0.25 = 1/4 */ 342 343 static inline enum malidp_scaling_coeff_set 344 malidp_se_select_coeffs(u32 upscale_factor) 345 { 346 return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS : 347 (upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS : 348 (upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS : 349 (upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS : 350 MALIDP_DOWNSCALING_4_COEFFS; 351 } 352 353 #undef FP_0_25000 354 #undef FP_0_36363 355 #undef FP_0_50000 356 #undef FP_0_66667 357 #undef FP_1_00000 358 359 static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) 360 { 361 static const s32 enhancer_coeffs[] = { 362 -8, -8, -8, -8, 128, -8, -8, -8, -8 363 }; 364 u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) | 365 MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL); 366 u32 image_enh = hwdev->hw->map.se_base + 367 ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 368 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH; 369 u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0; 370 int i; 371 372 malidp_hw_write(hwdev, val, image_enh); 373 for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i) 374 malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4); 375 } 376 377 /* 378 * background color components are defined as 12bits values, 379 * they will be shifted right when stored on hardware that 380 * supports only 8bits per channel 381 */ 382 #define MALIDP_BGND_COLOR_R 0x000 383 #define MALIDP_BGND_COLOR_G 0x000 384 #define MALIDP_BGND_COLOR_B 0x000 385 386 #define MALIDP_COLORADJ_NUM_COEFFS 12 387 #define MALIDP_COEFFTAB_NUM_COEFFS 64 388 389 #define MALIDP_GAMMA_LUT_SIZE 4096 390 391 #define AFBC_MOD_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_MASK | \ 392 AFBC_FORMAT_MOD_YTR | AFBC_FORMAT_MOD_SPLIT | \ 393 AFBC_FORMAT_MOD_SPARSE | AFBC_FORMAT_MOD_CBR | \ 394 AFBC_FORMAT_MOD_TILED | AFBC_FORMAT_MOD_SC) 395 396 #endif /* __MALIDP_HW_H__ */ 397