1 /* 2 * 3 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP hardware manipulation routines. 11 */ 12 13 #ifndef __MALIDP_HW_H__ 14 #define __MALIDP_HW_H__ 15 16 #include <linux/bitops.h> 17 #include "malidp_regs.h" 18 19 struct videomode; 20 struct clk; 21 22 /* Mali DP IP blocks */ 23 enum { 24 MALIDP_DE_BLOCK = 0, 25 MALIDP_SE_BLOCK, 26 MALIDP_DC_BLOCK 27 }; 28 29 /* Mali DP layer IDs */ 30 enum { 31 DE_VIDEO1 = BIT(0), 32 DE_GRAPHICS1 = BIT(1), 33 DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34 DE_VIDEO2 = BIT(3), 35 DE_SMART = BIT(4), 36 SE_MEMWRITE = BIT(5), 37 }; 38 39 enum rotation_features { 40 ROTATE_NONE, /* does not support rotation at all */ 41 ROTATE_ANY, /* supports rotation on any buffers */ 42 ROTATE_COMPRESSED, /* supports rotation only on compressed buffers */ 43 }; 44 45 struct malidp_format_id { 46 u32 format; /* DRM fourcc */ 47 u8 layer; /* bitmask of layers supporting it */ 48 u8 id; /* used internally */ 49 }; 50 51 #define MALIDP_INVALID_FORMAT_ID 0xff 52 53 /* 54 * hide the differences between register maps 55 * by using a common structure to hold the 56 * base register offsets 57 */ 58 59 struct malidp_irq_map { 60 u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 61 u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 62 u32 err_mask; /* mask of bits that represent errors */ 63 }; 64 65 struct malidp_layer { 66 u16 id; /* layer ID */ 67 u16 base; /* address offset for the register bank */ 68 u16 ptr; /* address offset for the pointer register */ 69 u16 stride_offset; /* offset to the first stride register. */ 70 s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */ 71 u16 mmu_ctrl_offset; /* offset to the MMU control register */ 72 enum rotation_features rot; /* type of rotation supported */ 73 /* address offset for the AFBC decoder registers */ 74 u16 afbc_decoder_offset; 75 }; 76 77 enum malidp_scaling_coeff_set { 78 MALIDP_UPSCALING_COEFFS = 1, 79 MALIDP_DOWNSCALING_1_5_COEFFS = 2, 80 MALIDP_DOWNSCALING_2_COEFFS = 3, 81 MALIDP_DOWNSCALING_2_75_COEFFS = 4, 82 MALIDP_DOWNSCALING_4_COEFFS = 5, 83 }; 84 85 struct malidp_se_config { 86 u8 scale_enable : 1; 87 u8 enhancer_enable : 1; 88 u8 hcoeff : 3; 89 u8 vcoeff : 3; 90 u8 plane_src_id; 91 u16 input_w, input_h; 92 u16 output_w, output_h; 93 u32 h_init_phase, h_delta_phase; 94 u32 v_init_phase, v_delta_phase; 95 }; 96 97 /* regmap features */ 98 #define MALIDP_REGMAP_HAS_CLEARIRQ BIT(0) 99 #define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT BIT(1) 100 #define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT BIT(2) 101 #define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2 BIT(3) 102 103 struct malidp_hw_regmap { 104 /* address offset of the DE register bank */ 105 /* is always 0x0000 */ 106 /* address offset of the DE coefficients registers */ 107 const u16 coeffs_base; 108 /* address offset of the SE registers bank */ 109 const u16 se_base; 110 /* address offset of the DC registers bank */ 111 const u16 dc_base; 112 113 /* address offset for the output depth register */ 114 const u16 out_depth_base; 115 116 /* bitmap with register map features */ 117 const u8 features; 118 119 /* list of supported layers */ 120 const u8 n_layers; 121 const struct malidp_layer *layers; 122 123 const struct malidp_irq_map de_irq_map; 124 const struct malidp_irq_map se_irq_map; 125 const struct malidp_irq_map dc_irq_map; 126 127 /* list of supported pixel formats for each layer */ 128 const struct malidp_format_id *pixel_formats; 129 const u8 n_pixel_formats; 130 131 /* pitch alignment requirement in bytes */ 132 const u8 bus_align_bytes; 133 }; 134 135 /* device features */ 136 /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ 137 #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) 138 139 struct malidp_hw_device; 140 141 /* 142 * Static structure containing hardware specific data and pointers to 143 * functions that behave differently between various versions of the IP. 144 */ 145 struct malidp_hw { 146 const struct malidp_hw_regmap map; 147 148 /* 149 * Validate the driver instance against the hardware bits 150 */ 151 int (*query_hw)(struct malidp_hw_device *hwdev); 152 153 /* 154 * Set the hardware into config mode, ready to accept mode changes 155 */ 156 void (*enter_config_mode)(struct malidp_hw_device *hwdev); 157 158 /* 159 * Tell hardware to exit configuration mode 160 */ 161 void (*leave_config_mode)(struct malidp_hw_device *hwdev); 162 163 /* 164 * Query if hardware is in configuration mode 165 */ 166 bool (*in_config_mode)(struct malidp_hw_device *hwdev); 167 168 /* 169 * Set/clear configuration valid flag for hardware parameters that can 170 * be changed outside the configuration mode to the given value. 171 * Hardware will use the new settings when config valid is set, 172 * after the end of the current buffer scanout, and will ignore 173 * any new values for those parameters if config valid flag is cleared 174 */ 175 void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value); 176 177 /* 178 * Set a new mode in hardware. Requires the hardware to be in 179 * configuration mode before this function is called. 180 */ 181 void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 182 183 /* 184 * Calculate the required rotation memory given the active area 185 * and the buffer format. 186 */ 187 int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, 188 u32 fmt, bool has_modifier); 189 190 int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev, 191 struct malidp_se_config *se_config, 192 struct malidp_se_config *old_config); 193 194 long (*se_calc_mclk)(struct malidp_hw_device *hwdev, 195 struct malidp_se_config *se_config, 196 struct videomode *vm); 197 /* 198 * Enable writing to memory the content of the next frame 199 * @param hwdev - malidp_hw_device structure containing the HW description 200 * @param addrs - array of addresses for each plane 201 * @param pitches - array of pitches for each plane 202 * @param num_planes - number of planes to be written 203 * @param w - width of the output frame 204 * @param h - height of the output frame 205 * @param fmt_id - internal format ID of output buffer 206 */ 207 int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, 208 s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id, 209 const s16 *rgb2yuv_coeffs); 210 211 /* 212 * Disable the writing to memory of the next frame's content. 213 */ 214 void (*disable_memwrite)(struct malidp_hw_device *hwdev); 215 216 u8 features; 217 }; 218 219 /* Supported variants of the hardware */ 220 enum { 221 MALIDP_500 = 0, 222 MALIDP_550, 223 MALIDP_650, 224 /* keep the next entry last */ 225 MALIDP_MAX_DEVICES 226 }; 227 228 extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES]; 229 230 /* 231 * Structure used by the driver during runtime operation. 232 */ 233 struct malidp_hw_device { 234 struct malidp_hw *hw; 235 void __iomem *regs; 236 237 /* APB clock */ 238 struct clk *pclk; 239 /* AXI clock */ 240 struct clk *aclk; 241 /* main clock for display core */ 242 struct clk *mclk; 243 /* pixel clock for display core */ 244 struct clk *pxlclk; 245 246 u8 min_line_size; 247 u16 max_line_size; 248 u32 output_color_depth; 249 250 /* track the device PM state */ 251 bool pm_suspended; 252 253 /* track the SE memory writeback state */ 254 u8 mw_state; 255 256 /* size of memory used for rotating layers, up to two banks available */ 257 u32 rotation_memory[2]; 258 }; 259 260 static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 261 { 262 WARN_ON(hwdev->pm_suspended); 263 return readl(hwdev->regs + reg); 264 } 265 266 static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 267 u32 value, u32 reg) 268 { 269 WARN_ON(hwdev->pm_suspended); 270 writel(value, hwdev->regs + reg); 271 } 272 273 static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 274 u32 mask, u32 reg) 275 { 276 u32 data = malidp_hw_read(hwdev, reg); 277 278 data |= mask; 279 malidp_hw_write(hwdev, data, reg); 280 } 281 282 static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 283 u32 mask, u32 reg) 284 { 285 u32 data = malidp_hw_read(hwdev, reg); 286 287 data &= ~mask; 288 malidp_hw_write(hwdev, data, reg); 289 } 290 291 static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 292 u8 block) 293 { 294 switch (block) { 295 case MALIDP_SE_BLOCK: 296 return hwdev->hw->map.se_base; 297 case MALIDP_DC_BLOCK: 298 return hwdev->hw->map.dc_base; 299 } 300 301 return 0; 302 } 303 304 static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 305 u8 block, u32 irq) 306 { 307 u32 base = malidp_get_block_base(hwdev, block); 308 309 malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 310 } 311 312 static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 313 u8 block, u32 irq) 314 { 315 u32 base = malidp_get_block_base(hwdev, block); 316 317 malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 318 } 319 320 int malidp_de_irq_init(struct drm_device *drm, int irq); 321 void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev); 322 void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev); 323 void malidp_de_irq_fini(struct malidp_hw_device *hwdev); 324 int malidp_se_irq_init(struct drm_device *drm, int irq); 325 void malidp_se_irq_fini(struct malidp_hw_device *hwdev); 326 327 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 328 u8 layer_id, u32 format, bool has_modifier); 329 330 int malidp_format_get_bpp(u32 fmt); 331 332 static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated) 333 { 334 /* 335 * only hardware that cannot do 8 bytes bus alignments have further 336 * constraints on rotated planes 337 */ 338 if (hwdev->hw->map.bus_align_bytes == 8) 339 return 8; 340 else 341 return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0); 342 } 343 344 /* U16.16 */ 345 #define FP_1_00000 0x00010000 /* 1.0 */ 346 #define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */ 347 #define FP_0_50000 0x00008000 /* 0.5 = 1/2 */ 348 #define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */ 349 #define FP_0_25000 0x00004000 /* 0.25 = 1/4 */ 350 351 static inline enum malidp_scaling_coeff_set 352 malidp_se_select_coeffs(u32 upscale_factor) 353 { 354 return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS : 355 (upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS : 356 (upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS : 357 (upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS : 358 MALIDP_DOWNSCALING_4_COEFFS; 359 } 360 361 #undef FP_0_25000 362 #undef FP_0_36363 363 #undef FP_0_50000 364 #undef FP_0_66667 365 #undef FP_1_00000 366 367 static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) 368 { 369 static const s32 enhancer_coeffs[] = { 370 -8, -8, -8, -8, 128, -8, -8, -8, -8 371 }; 372 u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) | 373 MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL); 374 u32 image_enh = hwdev->hw->map.se_base + 375 ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 376 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH; 377 u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0; 378 int i; 379 380 malidp_hw_write(hwdev, val, image_enh); 381 for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i) 382 malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4); 383 } 384 385 /* 386 * background color components are defined as 12bits values, 387 * they will be shifted right when stored on hardware that 388 * supports only 8bits per channel 389 */ 390 #define MALIDP_BGND_COLOR_R 0x000 391 #define MALIDP_BGND_COLOR_G 0x000 392 #define MALIDP_BGND_COLOR_B 0x000 393 394 #define MALIDP_COLORADJ_NUM_COEFFS 12 395 #define MALIDP_COEFFTAB_NUM_COEFFS 64 396 397 #define MALIDP_GAMMA_LUT_SIZE 4096 398 399 #define AFBC_SIZE_MASK AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 400 #define AFBC_SIZE_16X16 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 401 #define AFBC_YTR AFBC_FORMAT_MOD_YTR 402 #define AFBC_SPARSE AFBC_FORMAT_MOD_SPARSE 403 #define AFBC_CBR AFBC_FORMAT_MOD_CBR 404 #define AFBC_SPLIT AFBC_FORMAT_MOD_SPLIT 405 #define AFBC_TILED AFBC_FORMAT_MOD_TILED 406 #define AFBC_SC AFBC_FORMAT_MOD_SC 407 408 #define AFBC_MOD_VALID_BITS (AFBC_SIZE_MASK | AFBC_YTR | AFBC_SPLIT | \ 409 AFBC_SPARSE | AFBC_CBR | AFBC_TILED | AFBC_SC) 410 411 extern const u64 malidp_format_modifiers[]; 412 413 #endif /* __MALIDP_HW_H__ */ 414