1 /* 2 * 3 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP hardware manipulation routines. 11 */ 12 13 #ifndef __MALIDP_HW_H__ 14 #define __MALIDP_HW_H__ 15 16 #include <linux/bitops.h> 17 #include "malidp_regs.h" 18 19 struct videomode; 20 struct clk; 21 22 /* Mali DP IP blocks */ 23 enum { 24 MALIDP_DE_BLOCK = 0, 25 MALIDP_SE_BLOCK, 26 MALIDP_DC_BLOCK 27 }; 28 29 /* Mali DP layer IDs */ 30 enum { 31 DE_VIDEO1 = BIT(0), 32 DE_GRAPHICS1 = BIT(1), 33 DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34 DE_VIDEO2 = BIT(3), 35 DE_SMART = BIT(4), 36 }; 37 38 struct malidp_input_format { 39 u32 format; /* DRM fourcc */ 40 u8 layer; /* bitmask of layers supporting it */ 41 u8 id; /* used internally */ 42 }; 43 44 #define MALIDP_INVALID_FORMAT_ID 0xff 45 46 /* 47 * hide the differences between register maps 48 * by using a common structure to hold the 49 * base register offsets 50 */ 51 52 struct malidp_irq_map { 53 u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 54 u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 55 }; 56 57 struct malidp_layer { 58 u16 id; /* layer ID */ 59 u16 base; /* address offset for the register bank */ 60 u16 ptr; /* address offset for the pointer register */ 61 }; 62 63 /* regmap features */ 64 #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0) 65 66 struct malidp_hw_regmap { 67 /* address offset of the DE register bank */ 68 /* is always 0x0000 */ 69 /* address offset of the SE registers bank */ 70 const u16 se_base; 71 /* address offset of the DC registers bank */ 72 const u16 dc_base; 73 74 /* address offset for the output depth register */ 75 const u16 out_depth_base; 76 77 /* bitmap with register map features */ 78 const u8 features; 79 80 /* list of supported layers */ 81 const u8 n_layers; 82 const struct malidp_layer *layers; 83 84 const struct malidp_irq_map de_irq_map; 85 const struct malidp_irq_map se_irq_map; 86 const struct malidp_irq_map dc_irq_map; 87 88 /* list of supported input formats for each layer */ 89 const struct malidp_input_format *input_formats; 90 const u8 n_input_formats; 91 }; 92 93 struct malidp_hw_device { 94 const struct malidp_hw_regmap map; 95 void __iomem *regs; 96 97 /* APB clock */ 98 struct clk *pclk; 99 /* AXI clock */ 100 struct clk *aclk; 101 /* main clock for display core */ 102 struct clk *mclk; 103 /* pixel clock for display core */ 104 struct clk *pxlclk; 105 106 /* 107 * Validate the driver instance against the hardware bits 108 */ 109 int (*query_hw)(struct malidp_hw_device *hwdev); 110 111 /* 112 * Set the hardware into config mode, ready to accept mode changes 113 */ 114 void (*enter_config_mode)(struct malidp_hw_device *hwdev); 115 116 /* 117 * Tell hardware to exit configuration mode 118 */ 119 void (*leave_config_mode)(struct malidp_hw_device *hwdev); 120 121 /* 122 * Query if hardware is in configuration mode 123 */ 124 bool (*in_config_mode)(struct malidp_hw_device *hwdev); 125 126 /* 127 * Set configuration valid flag for hardware parameters that can 128 * be changed outside the configuration mode. Hardware will use 129 * the new settings when config valid is set after the end of the 130 * current buffer scanout 131 */ 132 void (*set_config_valid)(struct malidp_hw_device *hwdev); 133 134 /* 135 * Set a new mode in hardware. Requires the hardware to be in 136 * configuration mode before this function is called. 137 */ 138 void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 139 140 /* 141 * Calculate the required rotation memory given the active area 142 * and the buffer format. 143 */ 144 int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); 145 146 u8 features; 147 148 u8 min_line_size; 149 u16 max_line_size; 150 151 /* size of memory used for rotating layers, up to two banks available */ 152 u32 rotation_memory[2]; 153 }; 154 155 /* Supported variants of the hardware */ 156 enum { 157 MALIDP_500 = 0, 158 MALIDP_550, 159 MALIDP_650, 160 /* keep the next entry last */ 161 MALIDP_MAX_DEVICES 162 }; 163 164 extern const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES]; 165 166 static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 167 { 168 return readl(hwdev->regs + reg); 169 } 170 171 static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 172 u32 value, u32 reg) 173 { 174 writel(value, hwdev->regs + reg); 175 } 176 177 static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 178 u32 mask, u32 reg) 179 { 180 u32 data = malidp_hw_read(hwdev, reg); 181 182 data |= mask; 183 malidp_hw_write(hwdev, data, reg); 184 } 185 186 static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 187 u32 mask, u32 reg) 188 { 189 u32 data = malidp_hw_read(hwdev, reg); 190 191 data &= ~mask; 192 malidp_hw_write(hwdev, data, reg); 193 } 194 195 static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 196 u8 block) 197 { 198 switch (block) { 199 case MALIDP_SE_BLOCK: 200 return hwdev->map.se_base; 201 case MALIDP_DC_BLOCK: 202 return hwdev->map.dc_base; 203 } 204 205 return 0; 206 } 207 208 static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 209 u8 block, u32 irq) 210 { 211 u32 base = malidp_get_block_base(hwdev, block); 212 213 malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 214 } 215 216 static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 217 u8 block, u32 irq) 218 { 219 u32 base = malidp_get_block_base(hwdev, block); 220 221 malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 222 } 223 224 int malidp_de_irq_init(struct drm_device *drm, int irq); 225 void malidp_de_irq_fini(struct drm_device *drm); 226 int malidp_se_irq_init(struct drm_device *drm, int irq); 227 void malidp_se_irq_fini(struct drm_device *drm); 228 229 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 230 u8 layer_id, u32 format); 231 232 /* 233 * background color components are defined as 12bits values, 234 * they will be shifted right when stored on hardware that 235 * supports only 8bits per channel 236 */ 237 #define MALIDP_BGND_COLOR_R 0x000 238 #define MALIDP_BGND_COLOR_G 0x000 239 #define MALIDP_BGND_COLOR_B 0x000 240 241 #endif /* __MALIDP_HW_H__ */ 242