1ad49f860SLiviu Dudau /* 2ad49f860SLiviu Dudau * 3ad49f860SLiviu Dudau * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4ad49f860SLiviu Dudau * 5ad49f860SLiviu Dudau * This program is free software and is provided to you under the terms of the 6ad49f860SLiviu Dudau * GNU General Public License version 2 as published by the Free Software 7ad49f860SLiviu Dudau * Foundation, and any use by you of this program is subject to the terms 8ad49f860SLiviu Dudau * of such GNU licence. 9ad49f860SLiviu Dudau * 10ad49f860SLiviu Dudau * ARM Mali DP hardware manipulation routines. 11ad49f860SLiviu Dudau */ 12ad49f860SLiviu Dudau 13ad49f860SLiviu Dudau #ifndef __MALIDP_HW_H__ 14ad49f860SLiviu Dudau #define __MALIDP_HW_H__ 15ad49f860SLiviu Dudau 16ad49f860SLiviu Dudau #include <linux/bitops.h> 17ad49f860SLiviu Dudau #include "malidp_regs.h" 18ad49f860SLiviu Dudau 19ad49f860SLiviu Dudau struct videomode; 20ad49f860SLiviu Dudau struct clk; 21ad49f860SLiviu Dudau 22ad49f860SLiviu Dudau /* Mali DP IP blocks */ 23ad49f860SLiviu Dudau enum { 24ad49f860SLiviu Dudau MALIDP_DE_BLOCK = 0, 25ad49f860SLiviu Dudau MALIDP_SE_BLOCK, 26ad49f860SLiviu Dudau MALIDP_DC_BLOCK 27ad49f860SLiviu Dudau }; 28ad49f860SLiviu Dudau 29ad49f860SLiviu Dudau /* Mali DP layer IDs */ 30ad49f860SLiviu Dudau enum { 31ad49f860SLiviu Dudau DE_VIDEO1 = BIT(0), 32ad49f860SLiviu Dudau DE_GRAPHICS1 = BIT(1), 33ad49f860SLiviu Dudau DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34ad49f860SLiviu Dudau DE_VIDEO2 = BIT(3), 35ad49f860SLiviu Dudau DE_SMART = BIT(4), 36ad49f860SLiviu Dudau }; 37ad49f860SLiviu Dudau 386211b486SBrian Starkey struct malidp_format_id { 39ad49f860SLiviu Dudau u32 format; /* DRM fourcc */ 40ad49f860SLiviu Dudau u8 layer; /* bitmask of layers supporting it */ 41ad49f860SLiviu Dudau u8 id; /* used internally */ 42ad49f860SLiviu Dudau }; 43ad49f860SLiviu Dudau 44ad49f860SLiviu Dudau #define MALIDP_INVALID_FORMAT_ID 0xff 45ad49f860SLiviu Dudau 46ad49f860SLiviu Dudau /* 47ad49f860SLiviu Dudau * hide the differences between register maps 48ad49f860SLiviu Dudau * by using a common structure to hold the 49ad49f860SLiviu Dudau * base register offsets 50ad49f860SLiviu Dudau */ 51ad49f860SLiviu Dudau 52ad49f860SLiviu Dudau struct malidp_irq_map { 53ad49f860SLiviu Dudau u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 54ad49f860SLiviu Dudau u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 55ad49f860SLiviu Dudau }; 56ad49f860SLiviu Dudau 57ad49f860SLiviu Dudau struct malidp_layer { 58ad49f860SLiviu Dudau u16 id; /* layer ID */ 59ad49f860SLiviu Dudau u16 base; /* address offset for the register bank */ 60ad49f860SLiviu Dudau u16 ptr; /* address offset for the pointer register */ 6183d642eeSMihail Atanassov u16 stride_offset; /* Offset to the first stride register. */ 62ad49f860SLiviu Dudau }; 63ad49f860SLiviu Dudau 6428ce675bSMihail Atanassov enum malidp_scaling_coeff_set { 6528ce675bSMihail Atanassov MALIDP_UPSCALING_COEFFS = 1, 6628ce675bSMihail Atanassov MALIDP_DOWNSCALING_1_5_COEFFS = 2, 6728ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_COEFFS = 3, 6828ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_75_COEFFS = 4, 6928ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS = 5, 7028ce675bSMihail Atanassov }; 7128ce675bSMihail Atanassov 7228ce675bSMihail Atanassov struct malidp_se_config { 7328ce675bSMihail Atanassov u8 scale_enable : 1; 740274e6a0SMihail Atanassov u8 enhancer_enable : 1; 7528ce675bSMihail Atanassov u8 hcoeff : 3; 7628ce675bSMihail Atanassov u8 vcoeff : 3; 7728ce675bSMihail Atanassov u8 plane_src_id; 7828ce675bSMihail Atanassov u16 input_w, input_h; 7928ce675bSMihail Atanassov u16 output_w, output_h; 8028ce675bSMihail Atanassov u32 h_init_phase, h_delta_phase; 8128ce675bSMihail Atanassov u32 v_init_phase, v_delta_phase; 8228ce675bSMihail Atanassov }; 8328ce675bSMihail Atanassov 84ad49f860SLiviu Dudau /* regmap features */ 85ad49f860SLiviu Dudau #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0) 86ad49f860SLiviu Dudau 87ad49f860SLiviu Dudau struct malidp_hw_regmap { 88ad49f860SLiviu Dudau /* address offset of the DE register bank */ 89ad49f860SLiviu Dudau /* is always 0x0000 */ 9002725d31SMihail Atanassov /* address offset of the DE coefficients registers */ 9102725d31SMihail Atanassov const u16 coeffs_base; 92ad49f860SLiviu Dudau /* address offset of the SE registers bank */ 93ad49f860SLiviu Dudau const u16 se_base; 94ad49f860SLiviu Dudau /* address offset of the DC registers bank */ 95ad49f860SLiviu Dudau const u16 dc_base; 96ad49f860SLiviu Dudau 97ad49f860SLiviu Dudau /* address offset for the output depth register */ 98ad49f860SLiviu Dudau const u16 out_depth_base; 99ad49f860SLiviu Dudau 100ad49f860SLiviu Dudau /* bitmap with register map features */ 101ad49f860SLiviu Dudau const u8 features; 102ad49f860SLiviu Dudau 103ad49f860SLiviu Dudau /* list of supported layers */ 104ad49f860SLiviu Dudau const u8 n_layers; 105ad49f860SLiviu Dudau const struct malidp_layer *layers; 106ad49f860SLiviu Dudau 107ad49f860SLiviu Dudau const struct malidp_irq_map de_irq_map; 108ad49f860SLiviu Dudau const struct malidp_irq_map se_irq_map; 109ad49f860SLiviu Dudau const struct malidp_irq_map dc_irq_map; 110ad49f860SLiviu Dudau 1116211b486SBrian Starkey /* list of supported pixel formats for each layer */ 1126211b486SBrian Starkey const struct malidp_format_id *pixel_formats; 1136211b486SBrian Starkey const u8 n_pixel_formats; 114a228062cSBrian Starkey 115a228062cSBrian Starkey /* pitch alignment requirement in bytes */ 116a228062cSBrian Starkey const u8 bus_align_bytes; 117ad49f860SLiviu Dudau }; 118ad49f860SLiviu Dudau 11983d642eeSMihail Atanassov /* device features */ 12083d642eeSMihail Atanassov /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ 12183d642eeSMihail Atanassov #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) 12283d642eeSMihail Atanassov 123ad49f860SLiviu Dudau struct malidp_hw_device { 124ad49f860SLiviu Dudau const struct malidp_hw_regmap map; 125ad49f860SLiviu Dudau void __iomem *regs; 126ad49f860SLiviu Dudau 127ad49f860SLiviu Dudau /* APB clock */ 128ad49f860SLiviu Dudau struct clk *pclk; 129ad49f860SLiviu Dudau /* AXI clock */ 130ad49f860SLiviu Dudau struct clk *aclk; 131ad49f860SLiviu Dudau /* main clock for display core */ 132ad49f860SLiviu Dudau struct clk *mclk; 133ad49f860SLiviu Dudau /* pixel clock for display core */ 134ad49f860SLiviu Dudau struct clk *pxlclk; 135ad49f860SLiviu Dudau 136ad49f860SLiviu Dudau /* 137ad49f860SLiviu Dudau * Validate the driver instance against the hardware bits 138ad49f860SLiviu Dudau */ 139ad49f860SLiviu Dudau int (*query_hw)(struct malidp_hw_device *hwdev); 140ad49f860SLiviu Dudau 141ad49f860SLiviu Dudau /* 142ad49f860SLiviu Dudau * Set the hardware into config mode, ready to accept mode changes 143ad49f860SLiviu Dudau */ 144ad49f860SLiviu Dudau void (*enter_config_mode)(struct malidp_hw_device *hwdev); 145ad49f860SLiviu Dudau 146ad49f860SLiviu Dudau /* 147ad49f860SLiviu Dudau * Tell hardware to exit configuration mode 148ad49f860SLiviu Dudau */ 149ad49f860SLiviu Dudau void (*leave_config_mode)(struct malidp_hw_device *hwdev); 150ad49f860SLiviu Dudau 151ad49f860SLiviu Dudau /* 152ad49f860SLiviu Dudau * Query if hardware is in configuration mode 153ad49f860SLiviu Dudau */ 154ad49f860SLiviu Dudau bool (*in_config_mode)(struct malidp_hw_device *hwdev); 155ad49f860SLiviu Dudau 156ad49f860SLiviu Dudau /* 157ad49f860SLiviu Dudau * Set configuration valid flag for hardware parameters that can 158ad49f860SLiviu Dudau * be changed outside the configuration mode. Hardware will use 159ad49f860SLiviu Dudau * the new settings when config valid is set after the end of the 160ad49f860SLiviu Dudau * current buffer scanout 161ad49f860SLiviu Dudau */ 162ad49f860SLiviu Dudau void (*set_config_valid)(struct malidp_hw_device *hwdev); 163ad49f860SLiviu Dudau 164ad49f860SLiviu Dudau /* 165ad49f860SLiviu Dudau * Set a new mode in hardware. Requires the hardware to be in 166ad49f860SLiviu Dudau * configuration mode before this function is called. 167ad49f860SLiviu Dudau */ 168ad49f860SLiviu Dudau void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 169ad49f860SLiviu Dudau 170ad49f860SLiviu Dudau /* 171ad49f860SLiviu Dudau * Calculate the required rotation memory given the active area 172ad49f860SLiviu Dudau * and the buffer format. 173ad49f860SLiviu Dudau */ 174ad49f860SLiviu Dudau int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); 175ad49f860SLiviu Dudau 17628ce675bSMihail Atanassov int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev, 17728ce675bSMihail Atanassov struct malidp_se_config *se_config, 17828ce675bSMihail Atanassov struct malidp_se_config *old_config); 17928ce675bSMihail Atanassov 180c2e7f82dSMihail Atanassov long (*se_calc_mclk)(struct malidp_hw_device *hwdev, 181c2e7f82dSMihail Atanassov struct malidp_se_config *se_config, 182c2e7f82dSMihail Atanassov struct videomode *vm); 183c2e7f82dSMihail Atanassov 184ad49f860SLiviu Dudau u8 features; 185ad49f860SLiviu Dudau 186ad49f860SLiviu Dudau u8 min_line_size; 187ad49f860SLiviu Dudau u16 max_line_size; 188ad49f860SLiviu Dudau 18985f64218SLiviu Dudau /* track the device PM state */ 19085f64218SLiviu Dudau bool pm_suspended; 19185f64218SLiviu Dudau 192ad49f860SLiviu Dudau /* size of memory used for rotating layers, up to two banks available */ 193ad49f860SLiviu Dudau u32 rotation_memory[2]; 194ad49f860SLiviu Dudau }; 195ad49f860SLiviu Dudau 196ad49f860SLiviu Dudau /* Supported variants of the hardware */ 197ad49f860SLiviu Dudau enum { 198ad49f860SLiviu Dudau MALIDP_500 = 0, 199ad49f860SLiviu Dudau MALIDP_550, 200ad49f860SLiviu Dudau MALIDP_650, 201ad49f860SLiviu Dudau /* keep the next entry last */ 202ad49f860SLiviu Dudau MALIDP_MAX_DEVICES 203ad49f860SLiviu Dudau }; 204ad49f860SLiviu Dudau 205ad49f860SLiviu Dudau extern const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES]; 206ad49f860SLiviu Dudau 207ad49f860SLiviu Dudau static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 208ad49f860SLiviu Dudau { 20985f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 210ad49f860SLiviu Dudau return readl(hwdev->regs + reg); 211ad49f860SLiviu Dudau } 212ad49f860SLiviu Dudau 213ad49f860SLiviu Dudau static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 214ad49f860SLiviu Dudau u32 value, u32 reg) 215ad49f860SLiviu Dudau { 21685f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 217ad49f860SLiviu Dudau writel(value, hwdev->regs + reg); 218ad49f860SLiviu Dudau } 219ad49f860SLiviu Dudau 220ad49f860SLiviu Dudau static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 221ad49f860SLiviu Dudau u32 mask, u32 reg) 222ad49f860SLiviu Dudau { 223ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 224ad49f860SLiviu Dudau 225ad49f860SLiviu Dudau data |= mask; 226ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 227ad49f860SLiviu Dudau } 228ad49f860SLiviu Dudau 229ad49f860SLiviu Dudau static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 230ad49f860SLiviu Dudau u32 mask, u32 reg) 231ad49f860SLiviu Dudau { 232ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 233ad49f860SLiviu Dudau 234ad49f860SLiviu Dudau data &= ~mask; 235ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 236ad49f860SLiviu Dudau } 237ad49f860SLiviu Dudau 238ad49f860SLiviu Dudau static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 239ad49f860SLiviu Dudau u8 block) 240ad49f860SLiviu Dudau { 241ad49f860SLiviu Dudau switch (block) { 242ad49f860SLiviu Dudau case MALIDP_SE_BLOCK: 243ad49f860SLiviu Dudau return hwdev->map.se_base; 244ad49f860SLiviu Dudau case MALIDP_DC_BLOCK: 245ad49f860SLiviu Dudau return hwdev->map.dc_base; 246ad49f860SLiviu Dudau } 247ad49f860SLiviu Dudau 248ad49f860SLiviu Dudau return 0; 249ad49f860SLiviu Dudau } 250ad49f860SLiviu Dudau 251ad49f860SLiviu Dudau static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 252ad49f860SLiviu Dudau u8 block, u32 irq) 253ad49f860SLiviu Dudau { 254ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 255ad49f860SLiviu Dudau 256ad49f860SLiviu Dudau malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 257ad49f860SLiviu Dudau } 258ad49f860SLiviu Dudau 259ad49f860SLiviu Dudau static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 260ad49f860SLiviu Dudau u8 block, u32 irq) 261ad49f860SLiviu Dudau { 262ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 263ad49f860SLiviu Dudau 264ad49f860SLiviu Dudau malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 265ad49f860SLiviu Dudau } 266ad49f860SLiviu Dudau 267ad49f860SLiviu Dudau int malidp_de_irq_init(struct drm_device *drm, int irq); 268ad49f860SLiviu Dudau void malidp_de_irq_fini(struct drm_device *drm); 269ad49f860SLiviu Dudau int malidp_se_irq_init(struct drm_device *drm, int irq); 270ad49f860SLiviu Dudau void malidp_se_irq_fini(struct drm_device *drm); 271ad49f860SLiviu Dudau 272ad49f860SLiviu Dudau u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 273ad49f860SLiviu Dudau u8 layer_id, u32 format); 274ad49f860SLiviu Dudau 275a228062cSBrian Starkey static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev, 276a228062cSBrian Starkey unsigned int pitch) 277a228062cSBrian Starkey { 278a228062cSBrian Starkey return !(pitch & (hwdev->map.bus_align_bytes - 1)); 279a228062cSBrian Starkey } 280a228062cSBrian Starkey 28128ce675bSMihail Atanassov /* U16.16 */ 28228ce675bSMihail Atanassov #define FP_1_00000 0x00010000 /* 1.0 */ 28328ce675bSMihail Atanassov #define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */ 28428ce675bSMihail Atanassov #define FP_0_50000 0x00008000 /* 0.5 = 1/2 */ 28528ce675bSMihail Atanassov #define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */ 28628ce675bSMihail Atanassov #define FP_0_25000 0x00004000 /* 0.25 = 1/4 */ 28728ce675bSMihail Atanassov 28828ce675bSMihail Atanassov static inline enum malidp_scaling_coeff_set 28928ce675bSMihail Atanassov malidp_se_select_coeffs(u32 upscale_factor) 29028ce675bSMihail Atanassov { 29128ce675bSMihail Atanassov return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS : 29228ce675bSMihail Atanassov (upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS : 29328ce675bSMihail Atanassov (upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS : 29428ce675bSMihail Atanassov (upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS : 29528ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS; 29628ce675bSMihail Atanassov } 29728ce675bSMihail Atanassov 29828ce675bSMihail Atanassov #undef FP_0_25000 29928ce675bSMihail Atanassov #undef FP_0_36363 30028ce675bSMihail Atanassov #undef FP_0_50000 30128ce675bSMihail Atanassov #undef FP_0_66667 30228ce675bSMihail Atanassov #undef FP_1_00000 3030274e6a0SMihail Atanassov 3040274e6a0SMihail Atanassov static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) 3050274e6a0SMihail Atanassov { 3060274e6a0SMihail Atanassov static const s32 enhancer_coeffs[] = { 3070274e6a0SMihail Atanassov -8, -8, -8, -8, 128, -8, -8, -8, -8 3080274e6a0SMihail Atanassov }; 3090274e6a0SMihail Atanassov u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) | 3100274e6a0SMihail Atanassov MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL); 3110274e6a0SMihail Atanassov u32 image_enh = hwdev->map.se_base + 3120274e6a0SMihail Atanassov ((hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 3130274e6a0SMihail Atanassov 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH; 3140274e6a0SMihail Atanassov u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0; 3150274e6a0SMihail Atanassov int i; 3160274e6a0SMihail Atanassov 3170274e6a0SMihail Atanassov malidp_hw_write(hwdev, val, image_enh); 3180274e6a0SMihail Atanassov for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i) 3190274e6a0SMihail Atanassov malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4); 3200274e6a0SMihail Atanassov } 3210274e6a0SMihail Atanassov 322ad49f860SLiviu Dudau /* 323ad49f860SLiviu Dudau * background color components are defined as 12bits values, 324ad49f860SLiviu Dudau * they will be shifted right when stored on hardware that 325ad49f860SLiviu Dudau * supports only 8bits per channel 326ad49f860SLiviu Dudau */ 327ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_R 0x000 328ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_G 0x000 329ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_B 0x000 330ad49f860SLiviu Dudau 3316954f245SMihail Atanassov #define MALIDP_COLORADJ_NUM_COEFFS 12 33202725d31SMihail Atanassov #define MALIDP_COEFFTAB_NUM_COEFFS 64 33302725d31SMihail Atanassov 33402725d31SMihail Atanassov #define MALIDP_GAMMA_LUT_SIZE 4096 33502725d31SMihail Atanassov 336ad49f860SLiviu Dudau #endif /* __MALIDP_HW_H__ */ 337