1ad49f860SLiviu Dudau /* 2ad49f860SLiviu Dudau * 3ad49f860SLiviu Dudau * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4ad49f860SLiviu Dudau * 5ad49f860SLiviu Dudau * This program is free software and is provided to you under the terms of the 6ad49f860SLiviu Dudau * GNU General Public License version 2 as published by the Free Software 7ad49f860SLiviu Dudau * Foundation, and any use by you of this program is subject to the terms 8ad49f860SLiviu Dudau * of such GNU licence. 9ad49f860SLiviu Dudau * 10ad49f860SLiviu Dudau * ARM Mali DP hardware manipulation routines. 11ad49f860SLiviu Dudau */ 12ad49f860SLiviu Dudau 13ad49f860SLiviu Dudau #ifndef __MALIDP_HW_H__ 14ad49f860SLiviu Dudau #define __MALIDP_HW_H__ 15ad49f860SLiviu Dudau 16ad49f860SLiviu Dudau #include <linux/bitops.h> 17ad49f860SLiviu Dudau #include "malidp_regs.h" 18ad49f860SLiviu Dudau 19ad49f860SLiviu Dudau struct videomode; 20ad49f860SLiviu Dudau struct clk; 21ad49f860SLiviu Dudau 22ad49f860SLiviu Dudau /* Mali DP IP blocks */ 23ad49f860SLiviu Dudau enum { 24ad49f860SLiviu Dudau MALIDP_DE_BLOCK = 0, 25ad49f860SLiviu Dudau MALIDP_SE_BLOCK, 26ad49f860SLiviu Dudau MALIDP_DC_BLOCK 27ad49f860SLiviu Dudau }; 28ad49f860SLiviu Dudau 29ad49f860SLiviu Dudau /* Mali DP layer IDs */ 30ad49f860SLiviu Dudau enum { 31ad49f860SLiviu Dudau DE_VIDEO1 = BIT(0), 32ad49f860SLiviu Dudau DE_GRAPHICS1 = BIT(1), 33ad49f860SLiviu Dudau DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34ad49f860SLiviu Dudau DE_VIDEO2 = BIT(3), 35ad49f860SLiviu Dudau DE_SMART = BIT(4), 36a67bbbe2SBrian Starkey SE_MEMWRITE = BIT(5), 37ad49f860SLiviu Dudau }; 38ad49f860SLiviu Dudau 396211b486SBrian Starkey struct malidp_format_id { 40ad49f860SLiviu Dudau u32 format; /* DRM fourcc */ 41ad49f860SLiviu Dudau u8 layer; /* bitmask of layers supporting it */ 42ad49f860SLiviu Dudau u8 id; /* used internally */ 43ad49f860SLiviu Dudau }; 44ad49f860SLiviu Dudau 45ad49f860SLiviu Dudau #define MALIDP_INVALID_FORMAT_ID 0xff 46ad49f860SLiviu Dudau 47ad49f860SLiviu Dudau /* 48ad49f860SLiviu Dudau * hide the differences between register maps 49ad49f860SLiviu Dudau * by using a common structure to hold the 50ad49f860SLiviu Dudau * base register offsets 51ad49f860SLiviu Dudau */ 52ad49f860SLiviu Dudau 53ad49f860SLiviu Dudau struct malidp_irq_map { 54ad49f860SLiviu Dudau u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 55ad49f860SLiviu Dudau u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 56ad49f860SLiviu Dudau }; 57ad49f860SLiviu Dudau 58ad49f860SLiviu Dudau struct malidp_layer { 59ad49f860SLiviu Dudau u16 id; /* layer ID */ 60ad49f860SLiviu Dudau u16 base; /* address offset for the register bank */ 61ad49f860SLiviu Dudau u16 ptr; /* address offset for the pointer register */ 626e810eb5SMihail Atanassov u16 stride_offset; /* offset to the first stride register. */ 636e810eb5SMihail Atanassov s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */ 64ad49f860SLiviu Dudau }; 65ad49f860SLiviu Dudau 6628ce675bSMihail Atanassov enum malidp_scaling_coeff_set { 6728ce675bSMihail Atanassov MALIDP_UPSCALING_COEFFS = 1, 6828ce675bSMihail Atanassov MALIDP_DOWNSCALING_1_5_COEFFS = 2, 6928ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_COEFFS = 3, 7028ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_75_COEFFS = 4, 7128ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS = 5, 7228ce675bSMihail Atanassov }; 7328ce675bSMihail Atanassov 7428ce675bSMihail Atanassov struct malidp_se_config { 7528ce675bSMihail Atanassov u8 scale_enable : 1; 760274e6a0SMihail Atanassov u8 enhancer_enable : 1; 7728ce675bSMihail Atanassov u8 hcoeff : 3; 7828ce675bSMihail Atanassov u8 vcoeff : 3; 7928ce675bSMihail Atanassov u8 plane_src_id; 8028ce675bSMihail Atanassov u16 input_w, input_h; 8128ce675bSMihail Atanassov u16 output_w, output_h; 8228ce675bSMihail Atanassov u32 h_init_phase, h_delta_phase; 8328ce675bSMihail Atanassov u32 v_init_phase, v_delta_phase; 8428ce675bSMihail Atanassov }; 8528ce675bSMihail Atanassov 86ad49f860SLiviu Dudau /* regmap features */ 87ad49f860SLiviu Dudau #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0) 88ad49f860SLiviu Dudau 89ad49f860SLiviu Dudau struct malidp_hw_regmap { 90ad49f860SLiviu Dudau /* address offset of the DE register bank */ 91ad49f860SLiviu Dudau /* is always 0x0000 */ 9202725d31SMihail Atanassov /* address offset of the DE coefficients registers */ 9302725d31SMihail Atanassov const u16 coeffs_base; 94ad49f860SLiviu Dudau /* address offset of the SE registers bank */ 95ad49f860SLiviu Dudau const u16 se_base; 96ad49f860SLiviu Dudau /* address offset of the DC registers bank */ 97ad49f860SLiviu Dudau const u16 dc_base; 98ad49f860SLiviu Dudau 99ad49f860SLiviu Dudau /* address offset for the output depth register */ 100ad49f860SLiviu Dudau const u16 out_depth_base; 101ad49f860SLiviu Dudau 102ad49f860SLiviu Dudau /* bitmap with register map features */ 103ad49f860SLiviu Dudau const u8 features; 104ad49f860SLiviu Dudau 105ad49f860SLiviu Dudau /* list of supported layers */ 106ad49f860SLiviu Dudau const u8 n_layers; 107ad49f860SLiviu Dudau const struct malidp_layer *layers; 108ad49f860SLiviu Dudau 109ad49f860SLiviu Dudau const struct malidp_irq_map de_irq_map; 110ad49f860SLiviu Dudau const struct malidp_irq_map se_irq_map; 111ad49f860SLiviu Dudau const struct malidp_irq_map dc_irq_map; 112ad49f860SLiviu Dudau 1136211b486SBrian Starkey /* list of supported pixel formats for each layer */ 1146211b486SBrian Starkey const struct malidp_format_id *pixel_formats; 1156211b486SBrian Starkey const u8 n_pixel_formats; 116a228062cSBrian Starkey 117a228062cSBrian Starkey /* pitch alignment requirement in bytes */ 118a228062cSBrian Starkey const u8 bus_align_bytes; 119ad49f860SLiviu Dudau }; 120ad49f860SLiviu Dudau 12183d642eeSMihail Atanassov /* device features */ 12283d642eeSMihail Atanassov /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ 12383d642eeSMihail Atanassov #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) 12483d642eeSMihail Atanassov 125a6993b21SLiviu Dudau struct malidp_hw_device; 126ad49f860SLiviu Dudau 127a6993b21SLiviu Dudau /* 128a6993b21SLiviu Dudau * Static structure containing hardware specific data and pointers to 129a6993b21SLiviu Dudau * functions that behave differently between various versions of the IP. 130a6993b21SLiviu Dudau */ 131a6993b21SLiviu Dudau struct malidp_hw { 132a6993b21SLiviu Dudau const struct malidp_hw_regmap map; 133ad49f860SLiviu Dudau 134ad49f860SLiviu Dudau /* 135ad49f860SLiviu Dudau * Validate the driver instance against the hardware bits 136ad49f860SLiviu Dudau */ 137ad49f860SLiviu Dudau int (*query_hw)(struct malidp_hw_device *hwdev); 138ad49f860SLiviu Dudau 139ad49f860SLiviu Dudau /* 140ad49f860SLiviu Dudau * Set the hardware into config mode, ready to accept mode changes 141ad49f860SLiviu Dudau */ 142ad49f860SLiviu Dudau void (*enter_config_mode)(struct malidp_hw_device *hwdev); 143ad49f860SLiviu Dudau 144ad49f860SLiviu Dudau /* 145ad49f860SLiviu Dudau * Tell hardware to exit configuration mode 146ad49f860SLiviu Dudau */ 147ad49f860SLiviu Dudau void (*leave_config_mode)(struct malidp_hw_device *hwdev); 148ad49f860SLiviu Dudau 149ad49f860SLiviu Dudau /* 150ad49f860SLiviu Dudau * Query if hardware is in configuration mode 151ad49f860SLiviu Dudau */ 152ad49f860SLiviu Dudau bool (*in_config_mode)(struct malidp_hw_device *hwdev); 153ad49f860SLiviu Dudau 154ad49f860SLiviu Dudau /* 155ad49f860SLiviu Dudau * Set configuration valid flag for hardware parameters that can 156ad49f860SLiviu Dudau * be changed outside the configuration mode. Hardware will use 157ad49f860SLiviu Dudau * the new settings when config valid is set after the end of the 158ad49f860SLiviu Dudau * current buffer scanout 159ad49f860SLiviu Dudau */ 160ad49f860SLiviu Dudau void (*set_config_valid)(struct malidp_hw_device *hwdev); 161ad49f860SLiviu Dudau 162ad49f860SLiviu Dudau /* 163ad49f860SLiviu Dudau * Set a new mode in hardware. Requires the hardware to be in 164ad49f860SLiviu Dudau * configuration mode before this function is called. 165ad49f860SLiviu Dudau */ 166ad49f860SLiviu Dudau void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 167ad49f860SLiviu Dudau 168ad49f860SLiviu Dudau /* 169ad49f860SLiviu Dudau * Calculate the required rotation memory given the active area 170ad49f860SLiviu Dudau * and the buffer format. 171ad49f860SLiviu Dudau */ 172ad49f860SLiviu Dudau int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); 173ad49f860SLiviu Dudau 17428ce675bSMihail Atanassov int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev, 17528ce675bSMihail Atanassov struct malidp_se_config *se_config, 17628ce675bSMihail Atanassov struct malidp_se_config *old_config); 17728ce675bSMihail Atanassov 178c2e7f82dSMihail Atanassov long (*se_calc_mclk)(struct malidp_hw_device *hwdev, 179c2e7f82dSMihail Atanassov struct malidp_se_config *se_config, 180c2e7f82dSMihail Atanassov struct videomode *vm); 181846c87a0SLiviu Dudau /** 182846c87a0SLiviu Dudau * Enable writing to memory the content of the next frame 183846c87a0SLiviu Dudau * @param hwdev - malidp_hw_device structure containing the HW description 184846c87a0SLiviu Dudau * @param addrs - array of addresses for each plane 185846c87a0SLiviu Dudau * @param pitches - array of pitches for each plane 186846c87a0SLiviu Dudau * @param num_planes - number of planes to be written 187846c87a0SLiviu Dudau * @param w - width of the output frame 188846c87a0SLiviu Dudau * @param h - height of the output frame 189846c87a0SLiviu Dudau * @param fmt_id - internal format ID of output buffer 190846c87a0SLiviu Dudau */ 191846c87a0SLiviu Dudau int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, 192846c87a0SLiviu Dudau s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id); 193846c87a0SLiviu Dudau 194846c87a0SLiviu Dudau /* 195846c87a0SLiviu Dudau * Disable the writing to memory of the next frame's content. 196846c87a0SLiviu Dudau */ 197846c87a0SLiviu Dudau void (*disable_memwrite)(struct malidp_hw_device *hwdev); 198c2e7f82dSMihail Atanassov 199ad49f860SLiviu Dudau u8 features; 200ad49f860SLiviu Dudau }; 201ad49f860SLiviu Dudau 202ad49f860SLiviu Dudau /* Supported variants of the hardware */ 203ad49f860SLiviu Dudau enum { 204ad49f860SLiviu Dudau MALIDP_500 = 0, 205ad49f860SLiviu Dudau MALIDP_550, 206ad49f860SLiviu Dudau MALIDP_650, 207ad49f860SLiviu Dudau /* keep the next entry last */ 208ad49f860SLiviu Dudau MALIDP_MAX_DEVICES 209ad49f860SLiviu Dudau }; 210ad49f860SLiviu Dudau 211a6993b21SLiviu Dudau extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES]; 212a6993b21SLiviu Dudau 213a6993b21SLiviu Dudau /* 214a6993b21SLiviu Dudau * Structure used by the driver during runtime operation. 215a6993b21SLiviu Dudau */ 216a6993b21SLiviu Dudau struct malidp_hw_device { 217a6993b21SLiviu Dudau struct malidp_hw *hw; 218a6993b21SLiviu Dudau void __iomem *regs; 219a6993b21SLiviu Dudau 220a6993b21SLiviu Dudau /* APB clock */ 221a6993b21SLiviu Dudau struct clk *pclk; 222a6993b21SLiviu Dudau /* AXI clock */ 223a6993b21SLiviu Dudau struct clk *aclk; 224a6993b21SLiviu Dudau /* main clock for display core */ 225a6993b21SLiviu Dudau struct clk *mclk; 226a6993b21SLiviu Dudau /* pixel clock for display core */ 227a6993b21SLiviu Dudau struct clk *pxlclk; 228a6993b21SLiviu Dudau 229a6993b21SLiviu Dudau u8 min_line_size; 230a6993b21SLiviu Dudau u16 max_line_size; 231a6993b21SLiviu Dudau 232a6993b21SLiviu Dudau /* track the device PM state */ 233a6993b21SLiviu Dudau bool pm_suspended; 234a6993b21SLiviu Dudau 235a6993b21SLiviu Dudau /* size of memory used for rotating layers, up to two banks available */ 236a6993b21SLiviu Dudau u32 rotation_memory[2]; 237a6993b21SLiviu Dudau }; 238ad49f860SLiviu Dudau 239ad49f860SLiviu Dudau static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 240ad49f860SLiviu Dudau { 24185f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 242ad49f860SLiviu Dudau return readl(hwdev->regs + reg); 243ad49f860SLiviu Dudau } 244ad49f860SLiviu Dudau 245ad49f860SLiviu Dudau static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 246ad49f860SLiviu Dudau u32 value, u32 reg) 247ad49f860SLiviu Dudau { 24885f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 249ad49f860SLiviu Dudau writel(value, hwdev->regs + reg); 250ad49f860SLiviu Dudau } 251ad49f860SLiviu Dudau 252ad49f860SLiviu Dudau static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 253ad49f860SLiviu Dudau u32 mask, u32 reg) 254ad49f860SLiviu Dudau { 255ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 256ad49f860SLiviu Dudau 257ad49f860SLiviu Dudau data |= mask; 258ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 259ad49f860SLiviu Dudau } 260ad49f860SLiviu Dudau 261ad49f860SLiviu Dudau static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 262ad49f860SLiviu Dudau u32 mask, u32 reg) 263ad49f860SLiviu Dudau { 264ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 265ad49f860SLiviu Dudau 266ad49f860SLiviu Dudau data &= ~mask; 267ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 268ad49f860SLiviu Dudau } 269ad49f860SLiviu Dudau 270ad49f860SLiviu Dudau static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 271ad49f860SLiviu Dudau u8 block) 272ad49f860SLiviu Dudau { 273ad49f860SLiviu Dudau switch (block) { 274ad49f860SLiviu Dudau case MALIDP_SE_BLOCK: 275a6993b21SLiviu Dudau return hwdev->hw->map.se_base; 276ad49f860SLiviu Dudau case MALIDP_DC_BLOCK: 277a6993b21SLiviu Dudau return hwdev->hw->map.dc_base; 278ad49f860SLiviu Dudau } 279ad49f860SLiviu Dudau 280ad49f860SLiviu Dudau return 0; 281ad49f860SLiviu Dudau } 282ad49f860SLiviu Dudau 283ad49f860SLiviu Dudau static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 284ad49f860SLiviu Dudau u8 block, u32 irq) 285ad49f860SLiviu Dudau { 286ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 287ad49f860SLiviu Dudau 288ad49f860SLiviu Dudau malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 289ad49f860SLiviu Dudau } 290ad49f860SLiviu Dudau 291ad49f860SLiviu Dudau static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 292ad49f860SLiviu Dudau u8 block, u32 irq) 293ad49f860SLiviu Dudau { 294ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 295ad49f860SLiviu Dudau 296ad49f860SLiviu Dudau malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 297ad49f860SLiviu Dudau } 298ad49f860SLiviu Dudau 299ad49f860SLiviu Dudau int malidp_de_irq_init(struct drm_device *drm, int irq); 300ad49f860SLiviu Dudau void malidp_de_irq_fini(struct drm_device *drm); 301ad49f860SLiviu Dudau int malidp_se_irq_init(struct drm_device *drm, int irq); 302ad49f860SLiviu Dudau void malidp_se_irq_fini(struct drm_device *drm); 303ad49f860SLiviu Dudau 304ad49f860SLiviu Dudau u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 305ad49f860SLiviu Dudau u8 layer_id, u32 format); 306ad49f860SLiviu Dudau 307fcad73b9SLiviu Dudau static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated) 308a228062cSBrian Starkey { 309fcad73b9SLiviu Dudau /* 310fcad73b9SLiviu Dudau * only hardware that cannot do 8 bytes bus alignments have further 311fcad73b9SLiviu Dudau * constraints on rotated planes 312fcad73b9SLiviu Dudau */ 313fcad73b9SLiviu Dudau if (hwdev->hw->map.bus_align_bytes == 8) 314fcad73b9SLiviu Dudau return 8; 315fcad73b9SLiviu Dudau else 316fcad73b9SLiviu Dudau return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0); 317a228062cSBrian Starkey } 318a228062cSBrian Starkey 31928ce675bSMihail Atanassov /* U16.16 */ 32028ce675bSMihail Atanassov #define FP_1_00000 0x00010000 /* 1.0 */ 32128ce675bSMihail Atanassov #define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */ 32228ce675bSMihail Atanassov #define FP_0_50000 0x00008000 /* 0.5 = 1/2 */ 32328ce675bSMihail Atanassov #define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */ 32428ce675bSMihail Atanassov #define FP_0_25000 0x00004000 /* 0.25 = 1/4 */ 32528ce675bSMihail Atanassov 32628ce675bSMihail Atanassov static inline enum malidp_scaling_coeff_set 32728ce675bSMihail Atanassov malidp_se_select_coeffs(u32 upscale_factor) 32828ce675bSMihail Atanassov { 32928ce675bSMihail Atanassov return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS : 33028ce675bSMihail Atanassov (upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS : 33128ce675bSMihail Atanassov (upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS : 33228ce675bSMihail Atanassov (upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS : 33328ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS; 33428ce675bSMihail Atanassov } 33528ce675bSMihail Atanassov 33628ce675bSMihail Atanassov #undef FP_0_25000 33728ce675bSMihail Atanassov #undef FP_0_36363 33828ce675bSMihail Atanassov #undef FP_0_50000 33928ce675bSMihail Atanassov #undef FP_0_66667 34028ce675bSMihail Atanassov #undef FP_1_00000 3410274e6a0SMihail Atanassov 3420274e6a0SMihail Atanassov static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) 3430274e6a0SMihail Atanassov { 3440274e6a0SMihail Atanassov static const s32 enhancer_coeffs[] = { 3450274e6a0SMihail Atanassov -8, -8, -8, -8, 128, -8, -8, -8, -8 3460274e6a0SMihail Atanassov }; 3470274e6a0SMihail Atanassov u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) | 3480274e6a0SMihail Atanassov MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL); 349a6993b21SLiviu Dudau u32 image_enh = hwdev->hw->map.se_base + 350a6993b21SLiviu Dudau ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 3510274e6a0SMihail Atanassov 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH; 3520274e6a0SMihail Atanassov u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0; 3530274e6a0SMihail Atanassov int i; 3540274e6a0SMihail Atanassov 3550274e6a0SMihail Atanassov malidp_hw_write(hwdev, val, image_enh); 3560274e6a0SMihail Atanassov for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i) 3570274e6a0SMihail Atanassov malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4); 3580274e6a0SMihail Atanassov } 3590274e6a0SMihail Atanassov 360ad49f860SLiviu Dudau /* 361ad49f860SLiviu Dudau * background color components are defined as 12bits values, 362ad49f860SLiviu Dudau * they will be shifted right when stored on hardware that 363ad49f860SLiviu Dudau * supports only 8bits per channel 364ad49f860SLiviu Dudau */ 365ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_R 0x000 366ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_G 0x000 367ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_B 0x000 368ad49f860SLiviu Dudau 3696954f245SMihail Atanassov #define MALIDP_COLORADJ_NUM_COEFFS 12 37002725d31SMihail Atanassov #define MALIDP_COEFFTAB_NUM_COEFFS 64 37102725d31SMihail Atanassov 37202725d31SMihail Atanassov #define MALIDP_GAMMA_LUT_SIZE 4096 37302725d31SMihail Atanassov 374ad49f860SLiviu Dudau #endif /* __MALIDP_HW_H__ */ 375