1ad49f860SLiviu Dudau /* 2ad49f860SLiviu Dudau * 3ad49f860SLiviu Dudau * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4ad49f860SLiviu Dudau * 5ad49f860SLiviu Dudau * This program is free software and is provided to you under the terms of the 6ad49f860SLiviu Dudau * GNU General Public License version 2 as published by the Free Software 7ad49f860SLiviu Dudau * Foundation, and any use by you of this program is subject to the terms 8ad49f860SLiviu Dudau * of such GNU licence. 9ad49f860SLiviu Dudau * 10ad49f860SLiviu Dudau * ARM Mali DP hardware manipulation routines. 11ad49f860SLiviu Dudau */ 12ad49f860SLiviu Dudau 13ad49f860SLiviu Dudau #ifndef __MALIDP_HW_H__ 14ad49f860SLiviu Dudau #define __MALIDP_HW_H__ 15ad49f860SLiviu Dudau 16ad49f860SLiviu Dudau #include <linux/bitops.h> 17ad49f860SLiviu Dudau #include "malidp_regs.h" 18ad49f860SLiviu Dudau 19ad49f860SLiviu Dudau struct videomode; 20ad49f860SLiviu Dudau struct clk; 21ad49f860SLiviu Dudau 22ad49f860SLiviu Dudau /* Mali DP IP blocks */ 23ad49f860SLiviu Dudau enum { 24ad49f860SLiviu Dudau MALIDP_DE_BLOCK = 0, 25ad49f860SLiviu Dudau MALIDP_SE_BLOCK, 26ad49f860SLiviu Dudau MALIDP_DC_BLOCK 27ad49f860SLiviu Dudau }; 28ad49f860SLiviu Dudau 29ad49f860SLiviu Dudau /* Mali DP layer IDs */ 30ad49f860SLiviu Dudau enum { 31ad49f860SLiviu Dudau DE_VIDEO1 = BIT(0), 32ad49f860SLiviu Dudau DE_GRAPHICS1 = BIT(1), 33ad49f860SLiviu Dudau DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34ad49f860SLiviu Dudau DE_VIDEO2 = BIT(3), 35ad49f860SLiviu Dudau DE_SMART = BIT(4), 36a67bbbe2SBrian Starkey SE_MEMWRITE = BIT(5), 37ad49f860SLiviu Dudau }; 38ad49f860SLiviu Dudau 3966da13a5SLiviu Dudau enum rotation_features { 4066da13a5SLiviu Dudau ROTATE_NONE, /* does not support rotation at all */ 4166da13a5SLiviu Dudau ROTATE_ANY, /* supports rotation on any buffers */ 4266da13a5SLiviu Dudau ROTATE_COMPRESSED, /* supports rotation only on compressed buffers */ 4366da13a5SLiviu Dudau }; 4466da13a5SLiviu Dudau 456211b486SBrian Starkey struct malidp_format_id { 46ad49f860SLiviu Dudau u32 format; /* DRM fourcc */ 47ad49f860SLiviu Dudau u8 layer; /* bitmask of layers supporting it */ 48ad49f860SLiviu Dudau u8 id; /* used internally */ 49ad49f860SLiviu Dudau }; 50ad49f860SLiviu Dudau 51ad49f860SLiviu Dudau #define MALIDP_INVALID_FORMAT_ID 0xff 52ad49f860SLiviu Dudau 53ad49f860SLiviu Dudau /* 54ad49f860SLiviu Dudau * hide the differences between register maps 55ad49f860SLiviu Dudau * by using a common structure to hold the 56ad49f860SLiviu Dudau * base register offsets 57ad49f860SLiviu Dudau */ 58ad49f860SLiviu Dudau 59ad49f860SLiviu Dudau struct malidp_irq_map { 60ad49f860SLiviu Dudau u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 61ad49f860SLiviu Dudau u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 62613c5c7fSAlexandru Gheorghe u32 err_mask; /* mask of bits that represent errors */ 63ad49f860SLiviu Dudau }; 64ad49f860SLiviu Dudau 65ad49f860SLiviu Dudau struct malidp_layer { 66ad49f860SLiviu Dudau u16 id; /* layer ID */ 67ad49f860SLiviu Dudau u16 base; /* address offset for the register bank */ 68ad49f860SLiviu Dudau u16 ptr; /* address offset for the pointer register */ 696e810eb5SMihail Atanassov u16 stride_offset; /* offset to the first stride register. */ 706e810eb5SMihail Atanassov s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */ 711f23a56aSJamie Fox u16 mmu_ctrl_offset; /* offset to the MMU control register */ 7266da13a5SLiviu Dudau enum rotation_features rot; /* type of rotation supported */ 73ad49f860SLiviu Dudau }; 74ad49f860SLiviu Dudau 7528ce675bSMihail Atanassov enum malidp_scaling_coeff_set { 7628ce675bSMihail Atanassov MALIDP_UPSCALING_COEFFS = 1, 7728ce675bSMihail Atanassov MALIDP_DOWNSCALING_1_5_COEFFS = 2, 7828ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_COEFFS = 3, 7928ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_75_COEFFS = 4, 8028ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS = 5, 8128ce675bSMihail Atanassov }; 8228ce675bSMihail Atanassov 8328ce675bSMihail Atanassov struct malidp_se_config { 8428ce675bSMihail Atanassov u8 scale_enable : 1; 850274e6a0SMihail Atanassov u8 enhancer_enable : 1; 8628ce675bSMihail Atanassov u8 hcoeff : 3; 8728ce675bSMihail Atanassov u8 vcoeff : 3; 8828ce675bSMihail Atanassov u8 plane_src_id; 8928ce675bSMihail Atanassov u16 input_w, input_h; 9028ce675bSMihail Atanassov u16 output_w, output_h; 9128ce675bSMihail Atanassov u32 h_init_phase, h_delta_phase; 9228ce675bSMihail Atanassov u32 v_init_phase, v_delta_phase; 9328ce675bSMihail Atanassov }; 9428ce675bSMihail Atanassov 95ad49f860SLiviu Dudau /* regmap features */ 96ad49f860SLiviu Dudau #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0) 97ad49f860SLiviu Dudau 98ad49f860SLiviu Dudau struct malidp_hw_regmap { 99ad49f860SLiviu Dudau /* address offset of the DE register bank */ 100ad49f860SLiviu Dudau /* is always 0x0000 */ 10102725d31SMihail Atanassov /* address offset of the DE coefficients registers */ 10202725d31SMihail Atanassov const u16 coeffs_base; 103ad49f860SLiviu Dudau /* address offset of the SE registers bank */ 104ad49f860SLiviu Dudau const u16 se_base; 105ad49f860SLiviu Dudau /* address offset of the DC registers bank */ 106ad49f860SLiviu Dudau const u16 dc_base; 107ad49f860SLiviu Dudau 108ad49f860SLiviu Dudau /* address offset for the output depth register */ 109ad49f860SLiviu Dudau const u16 out_depth_base; 110ad49f860SLiviu Dudau 111ad49f860SLiviu Dudau /* bitmap with register map features */ 112ad49f860SLiviu Dudau const u8 features; 113ad49f860SLiviu Dudau 114ad49f860SLiviu Dudau /* list of supported layers */ 115ad49f860SLiviu Dudau const u8 n_layers; 116ad49f860SLiviu Dudau const struct malidp_layer *layers; 117ad49f860SLiviu Dudau 118ad49f860SLiviu Dudau const struct malidp_irq_map de_irq_map; 119ad49f860SLiviu Dudau const struct malidp_irq_map se_irq_map; 120ad49f860SLiviu Dudau const struct malidp_irq_map dc_irq_map; 121ad49f860SLiviu Dudau 1226211b486SBrian Starkey /* list of supported pixel formats for each layer */ 1236211b486SBrian Starkey const struct malidp_format_id *pixel_formats; 1246211b486SBrian Starkey const u8 n_pixel_formats; 125a228062cSBrian Starkey 126a228062cSBrian Starkey /* pitch alignment requirement in bytes */ 127a228062cSBrian Starkey const u8 bus_align_bytes; 128ad49f860SLiviu Dudau }; 129ad49f860SLiviu Dudau 13083d642eeSMihail Atanassov /* device features */ 13183d642eeSMihail Atanassov /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ 13283d642eeSMihail Atanassov #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) 13383d642eeSMihail Atanassov 134a6993b21SLiviu Dudau struct malidp_hw_device; 135ad49f860SLiviu Dudau 136a6993b21SLiviu Dudau /* 137a6993b21SLiviu Dudau * Static structure containing hardware specific data and pointers to 138a6993b21SLiviu Dudau * functions that behave differently between various versions of the IP. 139a6993b21SLiviu Dudau */ 140a6993b21SLiviu Dudau struct malidp_hw { 141a6993b21SLiviu Dudau const struct malidp_hw_regmap map; 142ad49f860SLiviu Dudau 143ad49f860SLiviu Dudau /* 144ad49f860SLiviu Dudau * Validate the driver instance against the hardware bits 145ad49f860SLiviu Dudau */ 146ad49f860SLiviu Dudau int (*query_hw)(struct malidp_hw_device *hwdev); 147ad49f860SLiviu Dudau 148ad49f860SLiviu Dudau /* 149ad49f860SLiviu Dudau * Set the hardware into config mode, ready to accept mode changes 150ad49f860SLiviu Dudau */ 151ad49f860SLiviu Dudau void (*enter_config_mode)(struct malidp_hw_device *hwdev); 152ad49f860SLiviu Dudau 153ad49f860SLiviu Dudau /* 154ad49f860SLiviu Dudau * Tell hardware to exit configuration mode 155ad49f860SLiviu Dudau */ 156ad49f860SLiviu Dudau void (*leave_config_mode)(struct malidp_hw_device *hwdev); 157ad49f860SLiviu Dudau 158ad49f860SLiviu Dudau /* 159ad49f860SLiviu Dudau * Query if hardware is in configuration mode 160ad49f860SLiviu Dudau */ 161ad49f860SLiviu Dudau bool (*in_config_mode)(struct malidp_hw_device *hwdev); 162ad49f860SLiviu Dudau 163ad49f860SLiviu Dudau /* 1640735cfdfSLiviu Dudau * Set/clear configuration valid flag for hardware parameters that can 1650735cfdfSLiviu Dudau * be changed outside the configuration mode to the given value. 1660735cfdfSLiviu Dudau * Hardware will use the new settings when config valid is set, 1670735cfdfSLiviu Dudau * after the end of the current buffer scanout, and will ignore 1680735cfdfSLiviu Dudau * any new values for those parameters if config valid flag is cleared 169ad49f860SLiviu Dudau */ 1700735cfdfSLiviu Dudau void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value); 171ad49f860SLiviu Dudau 172ad49f860SLiviu Dudau /* 173ad49f860SLiviu Dudau * Set a new mode in hardware. Requires the hardware to be in 174ad49f860SLiviu Dudau * configuration mode before this function is called. 175ad49f860SLiviu Dudau */ 176ad49f860SLiviu Dudau void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 177ad49f860SLiviu Dudau 178ad49f860SLiviu Dudau /* 179ad49f860SLiviu Dudau * Calculate the required rotation memory given the active area 180ad49f860SLiviu Dudau * and the buffer format. 181ad49f860SLiviu Dudau */ 182ad49f860SLiviu Dudau int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); 183ad49f860SLiviu Dudau 18428ce675bSMihail Atanassov int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev, 18528ce675bSMihail Atanassov struct malidp_se_config *se_config, 18628ce675bSMihail Atanassov struct malidp_se_config *old_config); 18728ce675bSMihail Atanassov 188c2e7f82dSMihail Atanassov long (*se_calc_mclk)(struct malidp_hw_device *hwdev, 189c2e7f82dSMihail Atanassov struct malidp_se_config *se_config, 190c2e7f82dSMihail Atanassov struct videomode *vm); 1911cb3cbe7SLiviu Dudau /* 192846c87a0SLiviu Dudau * Enable writing to memory the content of the next frame 193846c87a0SLiviu Dudau * @param hwdev - malidp_hw_device structure containing the HW description 194846c87a0SLiviu Dudau * @param addrs - array of addresses for each plane 195846c87a0SLiviu Dudau * @param pitches - array of pitches for each plane 196846c87a0SLiviu Dudau * @param num_planes - number of planes to be written 197846c87a0SLiviu Dudau * @param w - width of the output frame 198846c87a0SLiviu Dudau * @param h - height of the output frame 199846c87a0SLiviu Dudau * @param fmt_id - internal format ID of output buffer 200846c87a0SLiviu Dudau */ 201846c87a0SLiviu Dudau int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, 202b1150781SAlexandru Gheorghe s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id, 203b1150781SAlexandru Gheorghe const s16 *rgb2yuv_coeffs); 204846c87a0SLiviu Dudau 205846c87a0SLiviu Dudau /* 206846c87a0SLiviu Dudau * Disable the writing to memory of the next frame's content. 207846c87a0SLiviu Dudau */ 208846c87a0SLiviu Dudau void (*disable_memwrite)(struct malidp_hw_device *hwdev); 209c2e7f82dSMihail Atanassov 210ad49f860SLiviu Dudau u8 features; 211ad49f860SLiviu Dudau }; 212ad49f860SLiviu Dudau 213ad49f860SLiviu Dudau /* Supported variants of the hardware */ 214ad49f860SLiviu Dudau enum { 215ad49f860SLiviu Dudau MALIDP_500 = 0, 216ad49f860SLiviu Dudau MALIDP_550, 217ad49f860SLiviu Dudau MALIDP_650, 218ad49f860SLiviu Dudau /* keep the next entry last */ 219ad49f860SLiviu Dudau MALIDP_MAX_DEVICES 220ad49f860SLiviu Dudau }; 221ad49f860SLiviu Dudau 222a6993b21SLiviu Dudau extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES]; 223a6993b21SLiviu Dudau 224a6993b21SLiviu Dudau /* 225a6993b21SLiviu Dudau * Structure used by the driver during runtime operation. 226a6993b21SLiviu Dudau */ 227a6993b21SLiviu Dudau struct malidp_hw_device { 228a6993b21SLiviu Dudau struct malidp_hw *hw; 229a6993b21SLiviu Dudau void __iomem *regs; 230a6993b21SLiviu Dudau 231a6993b21SLiviu Dudau /* APB clock */ 232a6993b21SLiviu Dudau struct clk *pclk; 233a6993b21SLiviu Dudau /* AXI clock */ 234a6993b21SLiviu Dudau struct clk *aclk; 235a6993b21SLiviu Dudau /* main clock for display core */ 236a6993b21SLiviu Dudau struct clk *mclk; 237a6993b21SLiviu Dudau /* pixel clock for display core */ 238a6993b21SLiviu Dudau struct clk *pxlclk; 239a6993b21SLiviu Dudau 240a6993b21SLiviu Dudau u8 min_line_size; 241a6993b21SLiviu Dudau u16 max_line_size; 242f877006dSAyan Kumar Halder u32 output_color_depth; 243a6993b21SLiviu Dudau 244a6993b21SLiviu Dudau /* track the device PM state */ 245a6993b21SLiviu Dudau bool pm_suspended; 246a6993b21SLiviu Dudau 2471cb3cbe7SLiviu Dudau /* track the SE memory writeback state */ 2481cb3cbe7SLiviu Dudau u8 mw_state; 2491cb3cbe7SLiviu Dudau 250a6993b21SLiviu Dudau /* size of memory used for rotating layers, up to two banks available */ 251a6993b21SLiviu Dudau u32 rotation_memory[2]; 252a6993b21SLiviu Dudau }; 253ad49f860SLiviu Dudau 254ad49f860SLiviu Dudau static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 255ad49f860SLiviu Dudau { 25685f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 257ad49f860SLiviu Dudau return readl(hwdev->regs + reg); 258ad49f860SLiviu Dudau } 259ad49f860SLiviu Dudau 260ad49f860SLiviu Dudau static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 261ad49f860SLiviu Dudau u32 value, u32 reg) 262ad49f860SLiviu Dudau { 26385f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 264ad49f860SLiviu Dudau writel(value, hwdev->regs + reg); 265ad49f860SLiviu Dudau } 266ad49f860SLiviu Dudau 267ad49f860SLiviu Dudau static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 268ad49f860SLiviu Dudau u32 mask, u32 reg) 269ad49f860SLiviu Dudau { 270ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 271ad49f860SLiviu Dudau 272ad49f860SLiviu Dudau data |= mask; 273ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 274ad49f860SLiviu Dudau } 275ad49f860SLiviu Dudau 276ad49f860SLiviu Dudau static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 277ad49f860SLiviu Dudau u32 mask, u32 reg) 278ad49f860SLiviu Dudau { 279ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 280ad49f860SLiviu Dudau 281ad49f860SLiviu Dudau data &= ~mask; 282ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 283ad49f860SLiviu Dudau } 284ad49f860SLiviu Dudau 285ad49f860SLiviu Dudau static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 286ad49f860SLiviu Dudau u8 block) 287ad49f860SLiviu Dudau { 288ad49f860SLiviu Dudau switch (block) { 289ad49f860SLiviu Dudau case MALIDP_SE_BLOCK: 290a6993b21SLiviu Dudau return hwdev->hw->map.se_base; 291ad49f860SLiviu Dudau case MALIDP_DC_BLOCK: 292a6993b21SLiviu Dudau return hwdev->hw->map.dc_base; 293ad49f860SLiviu Dudau } 294ad49f860SLiviu Dudau 295ad49f860SLiviu Dudau return 0; 296ad49f860SLiviu Dudau } 297ad49f860SLiviu Dudau 298ad49f860SLiviu Dudau static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 299ad49f860SLiviu Dudau u8 block, u32 irq) 300ad49f860SLiviu Dudau { 301ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 302ad49f860SLiviu Dudau 303ad49f860SLiviu Dudau malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 304ad49f860SLiviu Dudau } 305ad49f860SLiviu Dudau 306ad49f860SLiviu Dudau static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 307ad49f860SLiviu Dudau u8 block, u32 irq) 308ad49f860SLiviu Dudau { 309ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 310ad49f860SLiviu Dudau 311ad49f860SLiviu Dudau malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 312ad49f860SLiviu Dudau } 313ad49f860SLiviu Dudau 314ad49f860SLiviu Dudau int malidp_de_irq_init(struct drm_device *drm, int irq); 315ff8fc26aSAyan Kumar Halder void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev); 316ff8fc26aSAyan Kumar Halder void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev); 31762862cfbSAyan Kumar Halder void malidp_de_irq_fini(struct malidp_hw_device *hwdev); 318ad49f860SLiviu Dudau int malidp_se_irq_init(struct drm_device *drm, int irq); 31962862cfbSAyan Kumar Halder void malidp_se_irq_fini(struct malidp_hw_device *hwdev); 320ad49f860SLiviu Dudau 321ad49f860SLiviu Dudau u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 322ad49f860SLiviu Dudau u8 layer_id, u32 format); 323ad49f860SLiviu Dudau 324fcad73b9SLiviu Dudau static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated) 325a228062cSBrian Starkey { 326fcad73b9SLiviu Dudau /* 327fcad73b9SLiviu Dudau * only hardware that cannot do 8 bytes bus alignments have further 328fcad73b9SLiviu Dudau * constraints on rotated planes 329fcad73b9SLiviu Dudau */ 330fcad73b9SLiviu Dudau if (hwdev->hw->map.bus_align_bytes == 8) 331fcad73b9SLiviu Dudau return 8; 332fcad73b9SLiviu Dudau else 333fcad73b9SLiviu Dudau return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0); 334a228062cSBrian Starkey } 335a228062cSBrian Starkey 33628ce675bSMihail Atanassov /* U16.16 */ 33728ce675bSMihail Atanassov #define FP_1_00000 0x00010000 /* 1.0 */ 33828ce675bSMihail Atanassov #define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */ 33928ce675bSMihail Atanassov #define FP_0_50000 0x00008000 /* 0.5 = 1/2 */ 34028ce675bSMihail Atanassov #define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */ 34128ce675bSMihail Atanassov #define FP_0_25000 0x00004000 /* 0.25 = 1/4 */ 34228ce675bSMihail Atanassov 34328ce675bSMihail Atanassov static inline enum malidp_scaling_coeff_set 34428ce675bSMihail Atanassov malidp_se_select_coeffs(u32 upscale_factor) 34528ce675bSMihail Atanassov { 34628ce675bSMihail Atanassov return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS : 34728ce675bSMihail Atanassov (upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS : 34828ce675bSMihail Atanassov (upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS : 34928ce675bSMihail Atanassov (upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS : 35028ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS; 35128ce675bSMihail Atanassov } 35228ce675bSMihail Atanassov 35328ce675bSMihail Atanassov #undef FP_0_25000 35428ce675bSMihail Atanassov #undef FP_0_36363 35528ce675bSMihail Atanassov #undef FP_0_50000 35628ce675bSMihail Atanassov #undef FP_0_66667 35728ce675bSMihail Atanassov #undef FP_1_00000 3580274e6a0SMihail Atanassov 3590274e6a0SMihail Atanassov static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) 3600274e6a0SMihail Atanassov { 3610274e6a0SMihail Atanassov static const s32 enhancer_coeffs[] = { 3620274e6a0SMihail Atanassov -8, -8, -8, -8, 128, -8, -8, -8, -8 3630274e6a0SMihail Atanassov }; 3640274e6a0SMihail Atanassov u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) | 3650274e6a0SMihail Atanassov MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL); 366a6993b21SLiviu Dudau u32 image_enh = hwdev->hw->map.se_base + 367a6993b21SLiviu Dudau ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 3680274e6a0SMihail Atanassov 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH; 3690274e6a0SMihail Atanassov u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0; 3700274e6a0SMihail Atanassov int i; 3710274e6a0SMihail Atanassov 3720274e6a0SMihail Atanassov malidp_hw_write(hwdev, val, image_enh); 3730274e6a0SMihail Atanassov for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i) 3740274e6a0SMihail Atanassov malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4); 3750274e6a0SMihail Atanassov } 3760274e6a0SMihail Atanassov 377ad49f860SLiviu Dudau /* 378ad49f860SLiviu Dudau * background color components are defined as 12bits values, 379ad49f860SLiviu Dudau * they will be shifted right when stored on hardware that 380ad49f860SLiviu Dudau * supports only 8bits per channel 381ad49f860SLiviu Dudau */ 382ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_R 0x000 383ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_G 0x000 384ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_B 0x000 385ad49f860SLiviu Dudau 3866954f245SMihail Atanassov #define MALIDP_COLORADJ_NUM_COEFFS 12 38702725d31SMihail Atanassov #define MALIDP_COEFFTAB_NUM_COEFFS 64 38802725d31SMihail Atanassov 38902725d31SMihail Atanassov #define MALIDP_GAMMA_LUT_SIZE 4096 39002725d31SMihail Atanassov 3913dae1c09SAyan Kumar Halder #define AFBC_MOD_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_MASK | \ 3923dae1c09SAyan Kumar Halder AFBC_FORMAT_MOD_YTR | AFBC_FORMAT_MOD_SPLIT | \ 3933dae1c09SAyan Kumar Halder AFBC_FORMAT_MOD_SPARSE | AFBC_FORMAT_MOD_CBR | \ 3943dae1c09SAyan Kumar Halder AFBC_FORMAT_MOD_TILED | AFBC_FORMAT_MOD_SC) 3953dae1c09SAyan Kumar Halder 396ad49f860SLiviu Dudau #endif /* __MALIDP_HW_H__ */ 397