1ad49f860SLiviu Dudau /* 2ad49f860SLiviu Dudau * 3ad49f860SLiviu Dudau * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved. 4ad49f860SLiviu Dudau * 5ad49f860SLiviu Dudau * This program is free software and is provided to you under the terms of the 6ad49f860SLiviu Dudau * GNU General Public License version 2 as published by the Free Software 7ad49f860SLiviu Dudau * Foundation, and any use by you of this program is subject to the terms 8ad49f860SLiviu Dudau * of such GNU licence. 9ad49f860SLiviu Dudau * 10ad49f860SLiviu Dudau * ARM Mali DP hardware manipulation routines. 11ad49f860SLiviu Dudau */ 12ad49f860SLiviu Dudau 13ad49f860SLiviu Dudau #ifndef __MALIDP_HW_H__ 14ad49f860SLiviu Dudau #define __MALIDP_HW_H__ 15ad49f860SLiviu Dudau 16ad49f860SLiviu Dudau #include <linux/bitops.h> 17ad49f860SLiviu Dudau #include "malidp_regs.h" 18ad49f860SLiviu Dudau 19ad49f860SLiviu Dudau struct videomode; 20ad49f860SLiviu Dudau struct clk; 21ad49f860SLiviu Dudau 22ad49f860SLiviu Dudau /* Mali DP IP blocks */ 23ad49f860SLiviu Dudau enum { 24ad49f860SLiviu Dudau MALIDP_DE_BLOCK = 0, 25ad49f860SLiviu Dudau MALIDP_SE_BLOCK, 26ad49f860SLiviu Dudau MALIDP_DC_BLOCK 27ad49f860SLiviu Dudau }; 28ad49f860SLiviu Dudau 29ad49f860SLiviu Dudau /* Mali DP layer IDs */ 30ad49f860SLiviu Dudau enum { 31ad49f860SLiviu Dudau DE_VIDEO1 = BIT(0), 32ad49f860SLiviu Dudau DE_GRAPHICS1 = BIT(1), 33ad49f860SLiviu Dudau DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ 34ad49f860SLiviu Dudau DE_VIDEO2 = BIT(3), 35ad49f860SLiviu Dudau DE_SMART = BIT(4), 36ad49f860SLiviu Dudau }; 37ad49f860SLiviu Dudau 386211b486SBrian Starkey struct malidp_format_id { 39ad49f860SLiviu Dudau u32 format; /* DRM fourcc */ 40ad49f860SLiviu Dudau u8 layer; /* bitmask of layers supporting it */ 41ad49f860SLiviu Dudau u8 id; /* used internally */ 42ad49f860SLiviu Dudau }; 43ad49f860SLiviu Dudau 44ad49f860SLiviu Dudau #define MALIDP_INVALID_FORMAT_ID 0xff 45ad49f860SLiviu Dudau 46ad49f860SLiviu Dudau /* 47ad49f860SLiviu Dudau * hide the differences between register maps 48ad49f860SLiviu Dudau * by using a common structure to hold the 49ad49f860SLiviu Dudau * base register offsets 50ad49f860SLiviu Dudau */ 51ad49f860SLiviu Dudau 52ad49f860SLiviu Dudau struct malidp_irq_map { 53ad49f860SLiviu Dudau u32 irq_mask; /* mask of IRQs that can be enabled in the block */ 54ad49f860SLiviu Dudau u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */ 55ad49f860SLiviu Dudau }; 56ad49f860SLiviu Dudau 57ad49f860SLiviu Dudau struct malidp_layer { 58ad49f860SLiviu Dudau u16 id; /* layer ID */ 59ad49f860SLiviu Dudau u16 base; /* address offset for the register bank */ 60ad49f860SLiviu Dudau u16 ptr; /* address offset for the pointer register */ 6183d642eeSMihail Atanassov u16 stride_offset; /* Offset to the first stride register. */ 62ad49f860SLiviu Dudau }; 63ad49f860SLiviu Dudau 64ad49f860SLiviu Dudau /* regmap features */ 65ad49f860SLiviu Dudau #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0) 66ad49f860SLiviu Dudau 67ad49f860SLiviu Dudau struct malidp_hw_regmap { 68ad49f860SLiviu Dudau /* address offset of the DE register bank */ 69ad49f860SLiviu Dudau /* is always 0x0000 */ 7002725d31SMihail Atanassov /* address offset of the DE coefficients registers */ 7102725d31SMihail Atanassov const u16 coeffs_base; 72ad49f860SLiviu Dudau /* address offset of the SE registers bank */ 73ad49f860SLiviu Dudau const u16 se_base; 74ad49f860SLiviu Dudau /* address offset of the DC registers bank */ 75ad49f860SLiviu Dudau const u16 dc_base; 76ad49f860SLiviu Dudau 77ad49f860SLiviu Dudau /* address offset for the output depth register */ 78ad49f860SLiviu Dudau const u16 out_depth_base; 79ad49f860SLiviu Dudau 80ad49f860SLiviu Dudau /* bitmap with register map features */ 81ad49f860SLiviu Dudau const u8 features; 82ad49f860SLiviu Dudau 83ad49f860SLiviu Dudau /* list of supported layers */ 84ad49f860SLiviu Dudau const u8 n_layers; 85ad49f860SLiviu Dudau const struct malidp_layer *layers; 86ad49f860SLiviu Dudau 87ad49f860SLiviu Dudau const struct malidp_irq_map de_irq_map; 88ad49f860SLiviu Dudau const struct malidp_irq_map se_irq_map; 89ad49f860SLiviu Dudau const struct malidp_irq_map dc_irq_map; 90ad49f860SLiviu Dudau 916211b486SBrian Starkey /* list of supported pixel formats for each layer */ 926211b486SBrian Starkey const struct malidp_format_id *pixel_formats; 936211b486SBrian Starkey const u8 n_pixel_formats; 94a228062cSBrian Starkey 95a228062cSBrian Starkey /* pitch alignment requirement in bytes */ 96a228062cSBrian Starkey const u8 bus_align_bytes; 97ad49f860SLiviu Dudau }; 98ad49f860SLiviu Dudau 9983d642eeSMihail Atanassov /* device features */ 10083d642eeSMihail Atanassov /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */ 10183d642eeSMihail Atanassov #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) 10283d642eeSMihail Atanassov 103ad49f860SLiviu Dudau struct malidp_hw_device { 104ad49f860SLiviu Dudau const struct malidp_hw_regmap map; 105ad49f860SLiviu Dudau void __iomem *regs; 106ad49f860SLiviu Dudau 107ad49f860SLiviu Dudau /* APB clock */ 108ad49f860SLiviu Dudau struct clk *pclk; 109ad49f860SLiviu Dudau /* AXI clock */ 110ad49f860SLiviu Dudau struct clk *aclk; 111ad49f860SLiviu Dudau /* main clock for display core */ 112ad49f860SLiviu Dudau struct clk *mclk; 113ad49f860SLiviu Dudau /* pixel clock for display core */ 114ad49f860SLiviu Dudau struct clk *pxlclk; 115ad49f860SLiviu Dudau 116ad49f860SLiviu Dudau /* 117ad49f860SLiviu Dudau * Validate the driver instance against the hardware bits 118ad49f860SLiviu Dudau */ 119ad49f860SLiviu Dudau int (*query_hw)(struct malidp_hw_device *hwdev); 120ad49f860SLiviu Dudau 121ad49f860SLiviu Dudau /* 122ad49f860SLiviu Dudau * Set the hardware into config mode, ready to accept mode changes 123ad49f860SLiviu Dudau */ 124ad49f860SLiviu Dudau void (*enter_config_mode)(struct malidp_hw_device *hwdev); 125ad49f860SLiviu Dudau 126ad49f860SLiviu Dudau /* 127ad49f860SLiviu Dudau * Tell hardware to exit configuration mode 128ad49f860SLiviu Dudau */ 129ad49f860SLiviu Dudau void (*leave_config_mode)(struct malidp_hw_device *hwdev); 130ad49f860SLiviu Dudau 131ad49f860SLiviu Dudau /* 132ad49f860SLiviu Dudau * Query if hardware is in configuration mode 133ad49f860SLiviu Dudau */ 134ad49f860SLiviu Dudau bool (*in_config_mode)(struct malidp_hw_device *hwdev); 135ad49f860SLiviu Dudau 136ad49f860SLiviu Dudau /* 137ad49f860SLiviu Dudau * Set configuration valid flag for hardware parameters that can 138ad49f860SLiviu Dudau * be changed outside the configuration mode. Hardware will use 139ad49f860SLiviu Dudau * the new settings when config valid is set after the end of the 140ad49f860SLiviu Dudau * current buffer scanout 141ad49f860SLiviu Dudau */ 142ad49f860SLiviu Dudau void (*set_config_valid)(struct malidp_hw_device *hwdev); 143ad49f860SLiviu Dudau 144ad49f860SLiviu Dudau /* 145ad49f860SLiviu Dudau * Set a new mode in hardware. Requires the hardware to be in 146ad49f860SLiviu Dudau * configuration mode before this function is called. 147ad49f860SLiviu Dudau */ 148ad49f860SLiviu Dudau void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); 149ad49f860SLiviu Dudau 150ad49f860SLiviu Dudau /* 151ad49f860SLiviu Dudau * Calculate the required rotation memory given the active area 152ad49f860SLiviu Dudau * and the buffer format. 153ad49f860SLiviu Dudau */ 154ad49f860SLiviu Dudau int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt); 155ad49f860SLiviu Dudau 156ad49f860SLiviu Dudau u8 features; 157ad49f860SLiviu Dudau 158ad49f860SLiviu Dudau u8 min_line_size; 159ad49f860SLiviu Dudau u16 max_line_size; 160ad49f860SLiviu Dudau 16185f64218SLiviu Dudau /* track the device PM state */ 16285f64218SLiviu Dudau bool pm_suspended; 16385f64218SLiviu Dudau 164ad49f860SLiviu Dudau /* size of memory used for rotating layers, up to two banks available */ 165ad49f860SLiviu Dudau u32 rotation_memory[2]; 166ad49f860SLiviu Dudau }; 167ad49f860SLiviu Dudau 168ad49f860SLiviu Dudau /* Supported variants of the hardware */ 169ad49f860SLiviu Dudau enum { 170ad49f860SLiviu Dudau MALIDP_500 = 0, 171ad49f860SLiviu Dudau MALIDP_550, 172ad49f860SLiviu Dudau MALIDP_650, 173ad49f860SLiviu Dudau /* keep the next entry last */ 174ad49f860SLiviu Dudau MALIDP_MAX_DEVICES 175ad49f860SLiviu Dudau }; 176ad49f860SLiviu Dudau 177ad49f860SLiviu Dudau extern const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES]; 178ad49f860SLiviu Dudau 179ad49f860SLiviu Dudau static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) 180ad49f860SLiviu Dudau { 18185f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 182ad49f860SLiviu Dudau return readl(hwdev->regs + reg); 183ad49f860SLiviu Dudau } 184ad49f860SLiviu Dudau 185ad49f860SLiviu Dudau static inline void malidp_hw_write(struct malidp_hw_device *hwdev, 186ad49f860SLiviu Dudau u32 value, u32 reg) 187ad49f860SLiviu Dudau { 18885f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended); 189ad49f860SLiviu Dudau writel(value, hwdev->regs + reg); 190ad49f860SLiviu Dudau } 191ad49f860SLiviu Dudau 192ad49f860SLiviu Dudau static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, 193ad49f860SLiviu Dudau u32 mask, u32 reg) 194ad49f860SLiviu Dudau { 195ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 196ad49f860SLiviu Dudau 197ad49f860SLiviu Dudau data |= mask; 198ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 199ad49f860SLiviu Dudau } 200ad49f860SLiviu Dudau 201ad49f860SLiviu Dudau static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, 202ad49f860SLiviu Dudau u32 mask, u32 reg) 203ad49f860SLiviu Dudau { 204ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg); 205ad49f860SLiviu Dudau 206ad49f860SLiviu Dudau data &= ~mask; 207ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg); 208ad49f860SLiviu Dudau } 209ad49f860SLiviu Dudau 210ad49f860SLiviu Dudau static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, 211ad49f860SLiviu Dudau u8 block) 212ad49f860SLiviu Dudau { 213ad49f860SLiviu Dudau switch (block) { 214ad49f860SLiviu Dudau case MALIDP_SE_BLOCK: 215ad49f860SLiviu Dudau return hwdev->map.se_base; 216ad49f860SLiviu Dudau case MALIDP_DC_BLOCK: 217ad49f860SLiviu Dudau return hwdev->map.dc_base; 218ad49f860SLiviu Dudau } 219ad49f860SLiviu Dudau 220ad49f860SLiviu Dudau return 0; 221ad49f860SLiviu Dudau } 222ad49f860SLiviu Dudau 223ad49f860SLiviu Dudau static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, 224ad49f860SLiviu Dudau u8 block, u32 irq) 225ad49f860SLiviu Dudau { 226ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 227ad49f860SLiviu Dudau 228ad49f860SLiviu Dudau malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 229ad49f860SLiviu Dudau } 230ad49f860SLiviu Dudau 231ad49f860SLiviu Dudau static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, 232ad49f860SLiviu Dudau u8 block, u32 irq) 233ad49f860SLiviu Dudau { 234ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block); 235ad49f860SLiviu Dudau 236ad49f860SLiviu Dudau malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); 237ad49f860SLiviu Dudau } 238ad49f860SLiviu Dudau 239ad49f860SLiviu Dudau int malidp_de_irq_init(struct drm_device *drm, int irq); 240ad49f860SLiviu Dudau void malidp_de_irq_fini(struct drm_device *drm); 241ad49f860SLiviu Dudau int malidp_se_irq_init(struct drm_device *drm, int irq); 242ad49f860SLiviu Dudau void malidp_se_irq_fini(struct drm_device *drm); 243ad49f860SLiviu Dudau 244ad49f860SLiviu Dudau u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 245ad49f860SLiviu Dudau u8 layer_id, u32 format); 246ad49f860SLiviu Dudau 247a228062cSBrian Starkey static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev, 248a228062cSBrian Starkey unsigned int pitch) 249a228062cSBrian Starkey { 250a228062cSBrian Starkey return !(pitch & (hwdev->map.bus_align_bytes - 1)); 251a228062cSBrian Starkey } 252a228062cSBrian Starkey 253ad49f860SLiviu Dudau /* 254ad49f860SLiviu Dudau * background color components are defined as 12bits values, 255ad49f860SLiviu Dudau * they will be shifted right when stored on hardware that 256ad49f860SLiviu Dudau * supports only 8bits per channel 257ad49f860SLiviu Dudau */ 258ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_R 0x000 259ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_G 0x000 260ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_B 0x000 261ad49f860SLiviu Dudau 26202725d31SMihail Atanassov #define MALIDP_COEFFTAB_NUM_COEFFS 64 26302725d31SMihail Atanassov 26402725d31SMihail Atanassov #define MALIDP_GAMMA_LUT_SIZE 4096 26502725d31SMihail Atanassov 266ad49f860SLiviu Dudau #endif /* __MALIDP_HW_H__ */ 267