1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP500/DP550/DP650 KMS/DRM driver structures 11 */ 12 13 #ifndef __MALIDP_DRV_H__ 14 #define __MALIDP_DRV_H__ 15 16 #include <linux/mutex.h> 17 #include <linux/wait.h> 18 #include <drm/drmP.h> 19 #include "malidp_hw.h" 20 21 struct malidp_drm { 22 struct malidp_hw_device *dev; 23 struct drm_crtc crtc; 24 wait_queue_head_t wq; 25 struct drm_pending_vblank_event *event; 26 atomic_t config_valid; 27 u32 core_id; 28 }; 29 30 #define crtc_to_malidp_device(x) container_of(x, struct malidp_drm, crtc) 31 32 struct malidp_plane { 33 struct drm_plane base; 34 struct malidp_hw_device *hwdev; 35 const struct malidp_layer *layer; 36 }; 37 38 struct malidp_plane_state { 39 struct drm_plane_state base; 40 41 /* size of the required rotation memory if plane is rotated */ 42 u32 rotmem_size; 43 /* internal format ID */ 44 u8 format; 45 u8 n_planes; 46 }; 47 48 #define to_malidp_plane(x) container_of(x, struct malidp_plane, base) 49 #define to_malidp_plane_state(x) container_of(x, struct malidp_plane_state, base) 50 51 struct malidp_crtc_state { 52 struct drm_crtc_state base; 53 u32 gamma_coeffs[MALIDP_COEFFTAB_NUM_COEFFS]; 54 u32 coloradj_coeffs[MALIDP_COLORADJ_NUM_COEFFS]; 55 struct malidp_se_config scaler_config; 56 /* Bitfield of all the planes that have requested a scaled output. */ 57 u8 scaled_planes_mask; 58 }; 59 60 #define to_malidp_crtc_state(x) container_of(x, struct malidp_crtc_state, base) 61 62 int malidp_de_planes_init(struct drm_device *drm); 63 int malidp_crtc_init(struct drm_device *drm); 64 65 /* often used combination of rotational bits */ 66 #define MALIDP_ROTATED_MASK (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270) 67 68 #endif /* __MALIDP_DRV_H__ */ 69