1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP500/DP550/DP650 KMS/DRM driver 11 */ 12 13 #include <linux/module.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/of_device.h> 17 #include <linux/of_graph.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/pm_runtime.h> 20 21 #include <drm/drmP.h> 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_fb_helper.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_gem_cma_helper.h> 29 #include <drm/drm_gem_framebuffer_helper.h> 30 #include <drm/drm_modeset_helper.h> 31 #include <drm/drm_of.h> 32 33 #include "malidp_drv.h" 34 #include "malidp_regs.h" 35 #include "malidp_hw.h" 36 37 #define MALIDP_CONF_VALID_TIMEOUT 250 38 39 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev, 40 u32 data[MALIDP_COEFFTAB_NUM_COEFFS]) 41 { 42 int i; 43 /* Update all channels with a single gamma curve. */ 44 const u32 gamma_write_mask = GENMASK(18, 16); 45 /* 46 * Always write an entire table, so the address field in 47 * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask 48 * directly. 49 */ 50 malidp_hw_write(hwdev, gamma_write_mask, 51 hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR); 52 for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) 53 malidp_hw_write(hwdev, data[i], 54 hwdev->hw->map.coeffs_base + 55 MALIDP_COEF_TABLE_DATA); 56 } 57 58 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc, 59 struct drm_crtc_state *old_state) 60 { 61 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 62 struct malidp_hw_device *hwdev = malidp->dev; 63 64 if (!crtc->state->color_mgmt_changed) 65 return; 66 67 if (!crtc->state->gamma_lut) { 68 malidp_hw_clearbits(hwdev, 69 MALIDP_DISP_FUNC_GAMMA, 70 MALIDP_DE_DISPLAY_FUNC); 71 } else { 72 struct malidp_crtc_state *mc = 73 to_malidp_crtc_state(crtc->state); 74 75 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id != 76 old_state->gamma_lut->base.id)) 77 malidp_write_gamma_table(hwdev, mc->gamma_coeffs); 78 79 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA, 80 MALIDP_DE_DISPLAY_FUNC); 81 } 82 } 83 84 static 85 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc, 86 struct drm_crtc_state *old_state) 87 { 88 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 89 struct malidp_hw_device *hwdev = malidp->dev; 90 int i; 91 92 if (!crtc->state->color_mgmt_changed) 93 return; 94 95 if (!crtc->state->ctm) { 96 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ, 97 MALIDP_DE_DISPLAY_FUNC); 98 } else { 99 struct malidp_crtc_state *mc = 100 to_malidp_crtc_state(crtc->state); 101 102 if (!old_state->ctm || (crtc->state->ctm->base.id != 103 old_state->ctm->base.id)) 104 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i) 105 malidp_hw_write(hwdev, 106 mc->coloradj_coeffs[i], 107 hwdev->hw->map.coeffs_base + 108 MALIDP_COLOR_ADJ_COEF + 4 * i); 109 110 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ, 111 MALIDP_DE_DISPLAY_FUNC); 112 } 113 } 114 115 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc, 116 struct drm_crtc_state *old_state) 117 { 118 struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state); 119 struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state); 120 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 121 struct malidp_hw_device *hwdev = malidp->dev; 122 struct malidp_se_config *s = &cs->scaler_config; 123 struct malidp_se_config *old_s = &old_cs->scaler_config; 124 u32 se_control = hwdev->hw->map.se_base + 125 ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 126 0x10 : 0xC); 127 u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL; 128 u32 scr = se_control + MALIDP_SE_SCALING_CONTROL; 129 u32 val; 130 131 /* Set SE_CONTROL */ 132 if (!s->scale_enable) { 133 val = malidp_hw_read(hwdev, se_control); 134 val &= ~MALIDP_SE_SCALING_EN; 135 malidp_hw_write(hwdev, val, se_control); 136 return; 137 } 138 139 hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s); 140 val = malidp_hw_read(hwdev, se_control); 141 val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN; 142 143 val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK); 144 val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0; 145 146 val |= MALIDP_SE_RGBO_IF_EN; 147 malidp_hw_write(hwdev, val, se_control); 148 149 /* Set IN_SIZE & OUT_SIZE. */ 150 val = MALIDP_SE_SET_V_SIZE(s->input_h) | 151 MALIDP_SE_SET_H_SIZE(s->input_w); 152 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE); 153 val = MALIDP_SE_SET_V_SIZE(s->output_h) | 154 MALIDP_SE_SET_H_SIZE(s->output_w); 155 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE); 156 157 /* Set phase regs. */ 158 malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH); 159 malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH); 160 malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH); 161 malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH); 162 } 163 164 /* 165 * set the "config valid" bit and wait until the hardware acts on it 166 */ 167 static int malidp_set_and_wait_config_valid(struct drm_device *drm) 168 { 169 struct malidp_drm *malidp = drm->dev_private; 170 struct malidp_hw_device *hwdev = malidp->dev; 171 int ret; 172 173 atomic_set(&malidp->config_valid, 0); 174 hwdev->hw->set_config_valid(hwdev); 175 /* don't wait for config_valid flag if we are in config mode */ 176 if (hwdev->hw->in_config_mode(hwdev)) 177 return 0; 178 179 ret = wait_event_interruptible_timeout(malidp->wq, 180 atomic_read(&malidp->config_valid) == 1, 181 msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT)); 182 183 return (ret > 0) ? 0 : -ETIMEDOUT; 184 } 185 186 static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) 187 { 188 struct drm_pending_vblank_event *event; 189 struct drm_device *drm = state->dev; 190 struct malidp_drm *malidp = drm->dev_private; 191 192 if (malidp->crtc.enabled) { 193 /* only set config_valid if the CRTC is enabled */ 194 if (malidp_set_and_wait_config_valid(drm)) 195 DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n"); 196 } 197 198 event = malidp->crtc.state->event; 199 if (event) { 200 malidp->crtc.state->event = NULL; 201 202 spin_lock_irq(&drm->event_lock); 203 if (drm_crtc_vblank_get(&malidp->crtc) == 0) 204 drm_crtc_arm_vblank_event(&malidp->crtc, event); 205 else 206 drm_crtc_send_vblank_event(&malidp->crtc, event); 207 spin_unlock_irq(&drm->event_lock); 208 } 209 drm_atomic_helper_commit_hw_done(state); 210 } 211 212 static void malidp_atomic_commit_tail(struct drm_atomic_state *state) 213 { 214 struct drm_device *drm = state->dev; 215 struct drm_crtc *crtc; 216 struct drm_crtc_state *old_crtc_state; 217 int i; 218 219 pm_runtime_get_sync(drm->dev); 220 221 drm_atomic_helper_commit_modeset_disables(drm, state); 222 223 for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { 224 malidp_atomic_commit_update_gamma(crtc, old_crtc_state); 225 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state); 226 malidp_atomic_commit_se_config(crtc, old_crtc_state); 227 } 228 229 drm_atomic_helper_commit_planes(drm, state, 0); 230 231 drm_atomic_helper_commit_modeset_enables(drm, state); 232 233 malidp_atomic_commit_hw_done(state); 234 235 drm_atomic_helper_wait_for_vblanks(drm, state); 236 237 pm_runtime_put(drm->dev); 238 239 drm_atomic_helper_cleanup_planes(drm, state); 240 } 241 242 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = { 243 .atomic_commit_tail = malidp_atomic_commit_tail, 244 }; 245 246 static const struct drm_mode_config_funcs malidp_mode_config_funcs = { 247 .fb_create = drm_gem_fb_create, 248 .output_poll_changed = drm_fb_helper_output_poll_changed, 249 .atomic_check = drm_atomic_helper_check, 250 .atomic_commit = drm_atomic_helper_commit, 251 }; 252 253 static int malidp_init(struct drm_device *drm) 254 { 255 int ret; 256 struct malidp_drm *malidp = drm->dev_private; 257 struct malidp_hw_device *hwdev = malidp->dev; 258 259 drm_mode_config_init(drm); 260 261 drm->mode_config.min_width = hwdev->min_line_size; 262 drm->mode_config.min_height = hwdev->min_line_size; 263 drm->mode_config.max_width = hwdev->max_line_size; 264 drm->mode_config.max_height = hwdev->max_line_size; 265 drm->mode_config.funcs = &malidp_mode_config_funcs; 266 drm->mode_config.helper_private = &malidp_mode_config_helpers; 267 268 ret = malidp_crtc_init(drm); 269 if (ret) { 270 drm_mode_config_cleanup(drm); 271 return ret; 272 } 273 274 return 0; 275 } 276 277 static void malidp_fini(struct drm_device *drm) 278 { 279 malidp_de_planes_destroy(drm); 280 drm_mode_config_cleanup(drm); 281 } 282 283 static int malidp_irq_init(struct platform_device *pdev) 284 { 285 int irq_de, irq_se, ret = 0; 286 struct drm_device *drm = dev_get_drvdata(&pdev->dev); 287 288 /* fetch the interrupts from DT */ 289 irq_de = platform_get_irq_byname(pdev, "DE"); 290 if (irq_de < 0) { 291 DRM_ERROR("no 'DE' IRQ specified!\n"); 292 return irq_de; 293 } 294 irq_se = platform_get_irq_byname(pdev, "SE"); 295 if (irq_se < 0) { 296 DRM_ERROR("no 'SE' IRQ specified!\n"); 297 return irq_se; 298 } 299 300 ret = malidp_de_irq_init(drm, irq_de); 301 if (ret) 302 return ret; 303 304 ret = malidp_se_irq_init(drm, irq_se); 305 if (ret) { 306 malidp_de_irq_fini(drm); 307 return ret; 308 } 309 310 return 0; 311 } 312 313 DEFINE_DRM_GEM_CMA_FOPS(fops); 314 315 static struct drm_driver malidp_driver = { 316 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC | 317 DRIVER_PRIME, 318 .lastclose = drm_fb_helper_lastclose, 319 .gem_free_object_unlocked = drm_gem_cma_free_object, 320 .gem_vm_ops = &drm_gem_cma_vm_ops, 321 .dumb_create = drm_gem_cma_dumb_create, 322 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 323 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 324 .gem_prime_export = drm_gem_prime_export, 325 .gem_prime_import = drm_gem_prime_import, 326 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 327 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 328 .gem_prime_vmap = drm_gem_cma_prime_vmap, 329 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 330 .gem_prime_mmap = drm_gem_cma_prime_mmap, 331 .fops = &fops, 332 .name = "mali-dp", 333 .desc = "ARM Mali Display Processor driver", 334 .date = "20160106", 335 .major = 1, 336 .minor = 0, 337 }; 338 339 static const struct of_device_id malidp_drm_of_match[] = { 340 { 341 .compatible = "arm,mali-dp500", 342 .data = &malidp_device[MALIDP_500] 343 }, 344 { 345 .compatible = "arm,mali-dp550", 346 .data = &malidp_device[MALIDP_550] 347 }, 348 { 349 .compatible = "arm,mali-dp650", 350 .data = &malidp_device[MALIDP_650] 351 }, 352 {}, 353 }; 354 MODULE_DEVICE_TABLE(of, malidp_drm_of_match); 355 356 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev, 357 const struct of_device_id *dev_id) 358 { 359 u32 core_id; 360 const char *compatstr_dp500 = "arm,mali-dp500"; 361 bool is_dp500; 362 bool dt_is_dp500; 363 364 /* 365 * The DP500 CORE_ID register is in a different location, so check it 366 * first. If the product id field matches, then this is DP500, otherwise 367 * check the DP550/650 CORE_ID register. 368 */ 369 core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID); 370 /* Offset 0x18 will never read 0x500 on products other than DP500. */ 371 is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500); 372 dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500, 373 sizeof(dev_id->compatible)) != NULL; 374 if (is_dp500 != dt_is_dp500) { 375 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n", 376 dev_id->compatible, is_dp500 ? "is" : "is not"); 377 return false; 378 } else if (!dt_is_dp500) { 379 u16 product_id; 380 char buf[32]; 381 382 core_id = malidp_hw_read(hwdev, 383 MALIDP550_DC_BASE + MALIDP_DE_CORE_ID); 384 product_id = MALIDP_PRODUCT_ID(core_id); 385 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id); 386 if (!strnstr(dev_id->compatible, buf, 387 sizeof(dev_id->compatible))) { 388 DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n", 389 dev_id->compatible, product_id); 390 return false; 391 } 392 } 393 return true; 394 } 395 396 static bool malidp_has_sufficient_address_space(const struct resource *res, 397 const struct of_device_id *dev_id) 398 { 399 resource_size_t res_size = resource_size(res); 400 const char *compatstr_dp500 = "arm,mali-dp500"; 401 402 if (!strnstr(dev_id->compatible, compatstr_dp500, 403 sizeof(dev_id->compatible))) 404 return res_size >= MALIDP550_ADDR_SPACE_SIZE; 405 else if (res_size < MALIDP500_ADDR_SPACE_SIZE) 406 return false; 407 return true; 408 } 409 410 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr, 411 char *buf) 412 { 413 struct drm_device *drm = dev_get_drvdata(dev); 414 struct malidp_drm *malidp = drm->dev_private; 415 416 return snprintf(buf, PAGE_SIZE, "%08x\n", malidp->core_id); 417 } 418 419 DEVICE_ATTR_RO(core_id); 420 421 static int malidp_init_sysfs(struct device *dev) 422 { 423 int ret = device_create_file(dev, &dev_attr_core_id); 424 425 if (ret) 426 DRM_ERROR("failed to create device file for core_id\n"); 427 428 return ret; 429 } 430 431 static void malidp_fini_sysfs(struct device *dev) 432 { 433 device_remove_file(dev, &dev_attr_core_id); 434 } 435 436 #define MAX_OUTPUT_CHANNELS 3 437 438 static int malidp_runtime_pm_suspend(struct device *dev) 439 { 440 struct drm_device *drm = dev_get_drvdata(dev); 441 struct malidp_drm *malidp = drm->dev_private; 442 struct malidp_hw_device *hwdev = malidp->dev; 443 444 /* we can only suspend if the hardware is in config mode */ 445 WARN_ON(!hwdev->hw->in_config_mode(hwdev)); 446 447 hwdev->pm_suspended = true; 448 clk_disable_unprepare(hwdev->mclk); 449 clk_disable_unprepare(hwdev->aclk); 450 clk_disable_unprepare(hwdev->pclk); 451 452 return 0; 453 } 454 455 static int malidp_runtime_pm_resume(struct device *dev) 456 { 457 struct drm_device *drm = dev_get_drvdata(dev); 458 struct malidp_drm *malidp = drm->dev_private; 459 struct malidp_hw_device *hwdev = malidp->dev; 460 461 clk_prepare_enable(hwdev->pclk); 462 clk_prepare_enable(hwdev->aclk); 463 clk_prepare_enable(hwdev->mclk); 464 hwdev->pm_suspended = false; 465 466 return 0; 467 } 468 469 static int malidp_bind(struct device *dev) 470 { 471 struct resource *res; 472 struct drm_device *drm; 473 struct malidp_drm *malidp; 474 struct malidp_hw_device *hwdev; 475 struct platform_device *pdev = to_platform_device(dev); 476 struct of_device_id const *dev_id; 477 /* number of lines for the R, G and B output */ 478 u8 output_width[MAX_OUTPUT_CHANNELS]; 479 int ret = 0, i; 480 u32 version, out_depth = 0; 481 482 malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL); 483 if (!malidp) 484 return -ENOMEM; 485 486 hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL); 487 if (!hwdev) 488 return -ENOMEM; 489 490 hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev); 491 malidp->dev = hwdev; 492 493 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 494 hwdev->regs = devm_ioremap_resource(dev, res); 495 if (IS_ERR(hwdev->regs)) 496 return PTR_ERR(hwdev->regs); 497 498 hwdev->pclk = devm_clk_get(dev, "pclk"); 499 if (IS_ERR(hwdev->pclk)) 500 return PTR_ERR(hwdev->pclk); 501 502 hwdev->aclk = devm_clk_get(dev, "aclk"); 503 if (IS_ERR(hwdev->aclk)) 504 return PTR_ERR(hwdev->aclk); 505 506 hwdev->mclk = devm_clk_get(dev, "mclk"); 507 if (IS_ERR(hwdev->mclk)) 508 return PTR_ERR(hwdev->mclk); 509 510 hwdev->pxlclk = devm_clk_get(dev, "pxlclk"); 511 if (IS_ERR(hwdev->pxlclk)) 512 return PTR_ERR(hwdev->pxlclk); 513 514 /* Get the optional framebuffer memory resource */ 515 ret = of_reserved_mem_device_init(dev); 516 if (ret && ret != -ENODEV) 517 return ret; 518 519 drm = drm_dev_alloc(&malidp_driver, dev); 520 if (IS_ERR(drm)) { 521 ret = PTR_ERR(drm); 522 goto alloc_fail; 523 } 524 525 drm->dev_private = malidp; 526 dev_set_drvdata(dev, drm); 527 528 /* Enable power management */ 529 pm_runtime_enable(dev); 530 531 /* Resume device to enable the clocks */ 532 if (pm_runtime_enabled(dev)) 533 pm_runtime_get_sync(dev); 534 else 535 malidp_runtime_pm_resume(dev); 536 537 dev_id = of_match_device(malidp_drm_of_match, dev); 538 if (!dev_id) { 539 ret = -EINVAL; 540 goto query_hw_fail; 541 } 542 543 if (!malidp_has_sufficient_address_space(res, dev_id)) { 544 DRM_ERROR("Insufficient address space in device-tree.\n"); 545 ret = -EINVAL; 546 goto query_hw_fail; 547 } 548 549 if (!malidp_is_compatible_hw_id(hwdev, dev_id)) { 550 ret = -EINVAL; 551 goto query_hw_fail; 552 } 553 554 ret = hwdev->hw->query_hw(hwdev); 555 if (ret) { 556 DRM_ERROR("Invalid HW configuration\n"); 557 goto query_hw_fail; 558 } 559 560 version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID); 561 DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16, 562 (version >> 12) & 0xf, (version >> 8) & 0xf); 563 564 malidp->core_id = version; 565 566 /* set the number of lines used for output of RGB data */ 567 ret = of_property_read_u8_array(dev->of_node, 568 "arm,malidp-output-port-lines", 569 output_width, MAX_OUTPUT_CHANNELS); 570 if (ret) 571 goto query_hw_fail; 572 573 for (i = 0; i < MAX_OUTPUT_CHANNELS; i++) 574 out_depth = (out_depth << 8) | (output_width[i] & 0xf); 575 malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base); 576 577 atomic_set(&malidp->config_valid, 0); 578 init_waitqueue_head(&malidp->wq); 579 580 ret = malidp_init(drm); 581 if (ret < 0) 582 goto query_hw_fail; 583 584 ret = malidp_init_sysfs(dev); 585 if (ret) 586 goto init_fail; 587 588 /* Set the CRTC's port so that the encoder component can find it */ 589 malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); 590 591 ret = component_bind_all(dev, drm); 592 if (ret) { 593 DRM_ERROR("Failed to bind all components\n"); 594 goto bind_fail; 595 } 596 597 ret = malidp_irq_init(pdev); 598 if (ret < 0) 599 goto irq_init_fail; 600 601 drm->irq_enabled = true; 602 603 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 604 if (ret < 0) { 605 DRM_ERROR("failed to initialise vblank\n"); 606 goto vblank_fail; 607 } 608 pm_runtime_put(dev); 609 610 drm_mode_config_reset(drm); 611 612 ret = drm_fb_cma_fbdev_init(drm, 32, 0); 613 if (ret) 614 goto fbdev_fail; 615 616 drm_kms_helper_poll_init(drm); 617 618 ret = drm_dev_register(drm, 0); 619 if (ret) 620 goto register_fail; 621 622 return 0; 623 624 register_fail: 625 drm_fb_cma_fbdev_fini(drm); 626 drm_kms_helper_poll_fini(drm); 627 fbdev_fail: 628 pm_runtime_get_sync(dev); 629 vblank_fail: 630 malidp_se_irq_fini(drm); 631 malidp_de_irq_fini(drm); 632 drm->irq_enabled = false; 633 irq_init_fail: 634 component_unbind_all(dev, drm); 635 bind_fail: 636 of_node_put(malidp->crtc.port); 637 malidp->crtc.port = NULL; 638 init_fail: 639 malidp_fini_sysfs(dev); 640 malidp_fini(drm); 641 query_hw_fail: 642 pm_runtime_put(dev); 643 if (pm_runtime_enabled(dev)) 644 pm_runtime_disable(dev); 645 else 646 malidp_runtime_pm_suspend(dev); 647 drm->dev_private = NULL; 648 dev_set_drvdata(dev, NULL); 649 drm_dev_put(drm); 650 alloc_fail: 651 of_reserved_mem_device_release(dev); 652 653 return ret; 654 } 655 656 static void malidp_unbind(struct device *dev) 657 { 658 struct drm_device *drm = dev_get_drvdata(dev); 659 struct malidp_drm *malidp = drm->dev_private; 660 661 drm_dev_unregister(drm); 662 drm_fb_cma_fbdev_fini(drm); 663 drm_kms_helper_poll_fini(drm); 664 pm_runtime_get_sync(dev); 665 malidp_se_irq_fini(drm); 666 malidp_de_irq_fini(drm); 667 component_unbind_all(dev, drm); 668 of_node_put(malidp->crtc.port); 669 malidp->crtc.port = NULL; 670 malidp_fini_sysfs(dev); 671 malidp_fini(drm); 672 pm_runtime_put(dev); 673 if (pm_runtime_enabled(dev)) 674 pm_runtime_disable(dev); 675 else 676 malidp_runtime_pm_suspend(dev); 677 drm->dev_private = NULL; 678 dev_set_drvdata(dev, NULL); 679 drm_dev_put(drm); 680 of_reserved_mem_device_release(dev); 681 } 682 683 static const struct component_master_ops malidp_master_ops = { 684 .bind = malidp_bind, 685 .unbind = malidp_unbind, 686 }; 687 688 static int malidp_compare_dev(struct device *dev, void *data) 689 { 690 struct device_node *np = data; 691 692 return dev->of_node == np; 693 } 694 695 static int malidp_platform_probe(struct platform_device *pdev) 696 { 697 struct device_node *port; 698 struct component_match *match = NULL; 699 700 if (!pdev->dev.of_node) 701 return -ENODEV; 702 703 /* there is only one output port inside each device, find it */ 704 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); 705 if (!port) 706 return -ENODEV; 707 708 drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev, 709 port); 710 of_node_put(port); 711 return component_master_add_with_match(&pdev->dev, &malidp_master_ops, 712 match); 713 } 714 715 static int malidp_platform_remove(struct platform_device *pdev) 716 { 717 component_master_del(&pdev->dev, &malidp_master_ops); 718 return 0; 719 } 720 721 static int __maybe_unused malidp_pm_suspend(struct device *dev) 722 { 723 struct drm_device *drm = dev_get_drvdata(dev); 724 725 return drm_mode_config_helper_suspend(drm); 726 } 727 728 static int __maybe_unused malidp_pm_resume(struct device *dev) 729 { 730 struct drm_device *drm = dev_get_drvdata(dev); 731 732 drm_mode_config_helper_resume(drm); 733 734 return 0; 735 } 736 737 static const struct dev_pm_ops malidp_pm_ops = { 738 SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \ 739 SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL) 740 }; 741 742 static struct platform_driver malidp_platform_driver = { 743 .probe = malidp_platform_probe, 744 .remove = malidp_platform_remove, 745 .driver = { 746 .name = "mali-dp", 747 .pm = &malidp_pm_ops, 748 .of_match_table = malidp_drm_of_match, 749 }, 750 }; 751 752 module_platform_driver(malidp_platform_driver); 753 754 MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>"); 755 MODULE_DESCRIPTION("ARM Mali DP DRM driver"); 756 MODULE_LICENSE("GPL v2"); 757